A 0.8-V 230- W 98-dB DR Inverter-Based Modulator for Audio Applications

2430 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 A 0.8-V 230- W 98-dB DR Inverter-Based Modulator for Audio Applications Hao Luo, Yan Han, Ray C.C. Cheung, Member, IEEE, Xiaopeng Liu, and Tianlin Cao Abstract This paper presents a modulator based on a gain-boost class-c inverter for audio applications. The gain-boost class-c inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm.the experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230- W power, which demonstrates that the gain-boost class-c inverter is particularly suitable for low-voltage micro-power high-resolution applications. Index Terms Class-C inverter, gain boost, on-chip body bias. I. INTRODUCTION modulator, T HE rapid development of the portable electronics market has forced an explosive growth in the demand for low-voltage micro-power IC design. With the continuous scaling of CMOS technology, the supply voltage of the digital IC is reduced to be below 1 V, and the corresponding power consumption is effectively reduced. For analog or mixed-signal IC, the low-voltage micro-power design faces significant challenges [1] [6]. In particular, as the key building block in analog IC, the operational transconductance amplifier (OTA) is the main bottleneck for the reduction of supply voltage and power dissipation with the reasons as follows: 1) the MOS threshold voltage is not scaled as aggressively as the supply voltage due to the leakage current consideration, which limits the application of some traditional OTAs to low-voltage environment; Manuscript received February 07, 2013; revised July 10, 2013; accepted July 13, 2013. Date of publication August 19, 2013; date of current version September 20, 2013. This paper was approved by Associate Editor Eric Klumperink. This work was supported by a grant from National Natural Science Foundation of China (General Program, No. 61274035) and Ph.D. Programs Foundation of Ministry of Education of China (No. 20100101110063). H. Luo, Y. Han, X. Liu, and T. Cao are with the Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China (e-mail: hany@zju.edu.cn). R. C. C. Cheung is with the Department of Electrical Engineering, City University of Hong Kong, Hong Kong 999077, China (e-mail: r.cheung@cityu.edu. cn). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2013.2275659 2) the supply voltage reduction directly affects the amplitude of the processed signal in OTA, thereby reducing the DR; 3) how to achieve high dc gain in low-voltage, low-power applications is a design issue; and 4) to keep the DR specification in low-voltage design, large capacitance is usually needed to reduce thermal noise, which may increase OTA load; therefore, how to obtain relatively high slew rate (SR) with low current consumption is also a design issue. A class-c inverter is recently reported to replace traditional OTA in a low-voltage micro-power single-loop modulator [1]. The input transistors of the class-c inverter operate in a subthreshold region in steady state, so the inverter is able to operate at very low supply with small static current. When the inverter enters into a slewing period, one of the two input transistors is turned on, while the other is completely off. Therefore, a high SR is obtained with minimum short-circuit current (from the supply terminal to the ground). However, the dc gain of a traditional class-c inverter is finite (below 60 db), causing the leaking and nonlinearity of inverter-based integrators, which disadvantageously affects its application to cascaded modulator [7] [10]. Moreover, the inverter specifications (such as bandwidth and SR) degrade significantly at a slow process corner or low supply voltage because of its subthreshold characteristics and push pull structure. In this paper, a gain-boost class-c inverter is proposed, which boosts the inverter dc gain to 83 db in the typical condition. An on-chip body bias technique is introduced for effective compensation of the inverter performance at a slow process corner or low supply. As a result, the inverter-based design methodology can be applicable to most high-performance occasions. To demonstrate the practicality of the proposed gain-boost class-c inverter, an audio 2-1 cascaded inverter-based modulator is designed. The modulator chip is implemented in SMIC 65-nm CMOS process and achieves 91-dB peak SNDR, 94-dB peak SNR, and 98-dB DR over 20-KHz audio bandwidth at 0.8-V supply consuming only 230- Wpower. This paper is organized in the following manner. Section II introduces an inverter-based modulator and proposes the specification requirements in the design of the class-c inverter and the inverter-based integrator. Section III describes the principle and circuit implementation of the gain-boost class-c inverter and analyzes the inverter specifications, including dc gain, output swing, bandwidth, slew rate, PSRR, CMRR, and noise. Moreover, the proposed micro-power on-chip body bias technique and its applications to the inverter-based design are presented in detail. Section IV reports the measurement result. The final conclusion is drawn in Section V. 0018-9200 2013 IEEE

LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2431 Fig. 1. Block diagram of 2-1 cascaded modulator. is sampled in the sampling capacitor, and the inverters are kept in a steady state. The inverter input is close to (plus a small inverter offset, so the inverter acts as a micro-power amplifier. At the beginning of p2, the is instantaneously changed to. Depending on the polarity of the, one of the input transistors in the inverter is biased at a saturated (or linear) region while the other is completely off. As a result, a high SR is obtained for the setup of the inverter-based integrator (the charge is transferred from to the integrator capacitor ) with minimum static current. When the integrator output is set up to its ultimate value, the returns to due to the capacitor feedback, and the inverter enters back to the subthreshold state. In the integrator, the compensate capacitor samples the at phase p1 and holds the at phase p2, so the left plate of the serves as virtual ground at p2, which is named as the autozeroing technique. The autozeroing technique is mainly used to reduce a mismatch in pseudo-differential circuit and remove the 1/f noise [11]. A common-mode feedback (CMFB) loop is realized through the capacitors [12]. Fig. 3 shows the 2-1 cascaded modulator circuit using the proposed inverter-based integrator. The real modulator is pseudo-differential structure, but only one branch is shown in Fig. 3 for simplification. The modulator feedback reference voltages are selected as VDD and GND, which avoids on-chip reference voltage buffers, and meanwhile enlarges the input range of the modulator. The switches are controlled by two-phase, nonoverlapping clocks, p1 and p2, advanced falling edge clocks, p1a and p2a, in which p1a and p2a are designed to suppress the signal-dependent channel charge injection. For the application of the modulator, two nonidealities of the inverter-based integrator are analyzed in the following subsections. Fig. 2. Pseudo-differential inverter-based integrator. II. INVERTER-BASED MODULATOR A. Modulator Architecture and Circuit Topology Fig. 1 shows the block diagram of the proposed inverterbased modulator. A 2-1 cascaded architecture with a sampling frequency of 5 MHz is adopted, including three inverterbased integrators. Fig. 2 shows the circuit of the proposed pseudo-differential inverter-based switched-capacitor integrator, in which a pair of inverters is placed symmetrically in differential branches. For the inverter, the supply voltage is chosen to be slightly lower than the sum of the threshold voltage of PMOS and NMOS input transistors. When the inverter input is around the common-mode voltage, both of the input transistors operate in a subthreshold region (assuming that PMOS and NMOS transistors have similar ). Thus, the inverter behaves as a micro-power class-c amplifier [1]. The inverter-based integrator operates with a sampling phase p1 and an integration phase p2. During p1, the integrator input B. Finite Inverter dc gain The analysis of the finite dc-gain effect can be found in literatures such as [1] and [13] [15]. Fig. 4 shows the inverter-based integrator model, where is the compensation capacitor associated with autozeroing technique, and represents the parasitic capacitor at the inverter input. As we known, the transfer function of a SC integrator with finite dc-gain is where is gain error and is phase error. The phase error is more critical than the gain error because it can shift the zero of the noise transfer function, causing the loss of the integrator. Therefore, the phase error of the proposed integrator needs to be calculated first, and then the required inverter dc gain can be obtained. From Fig. 4, the voltages of node and are given as (1) (2)

2432 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Fig. 3. Inverter-based 2-1 cascaded modulator. The noise increment due to and is obtained as (5) In order to satisfy 1dB,wehave (6) Fig. 4. Inverter-based integrator model with autozeroing technique. where is the inverter output, and is the inverter dc gain. Since charge conservation law is followed at integrator phase p1 and p2, the integrator phase error is obtained as We find that the introduction of degrades the phase error. For the 2-1 cascaded modulator, suppose all of the three integrators are lossy, and their phase errors are,and, respectively, the power of the quantization noise in the modulator is given as [16] where is oversampling ratio, is modulator coefficient, and are quantization noise power in the first and second stages, respectively. From (4), the phase errors of the first and second integrators have a significant influence on the quantization noise, and thus the gain-boost inverters need to be utilized. By comparison, the noise contribution of the third integrator can be ignored due to noise shaping, so the gain-boost module can be removed. (3) (4) In this design,,so. Suppose that 5pF, 1pF, 5pF and 25 pf in the first integrator, the required inverter dc gain is calculated to be 61.6 db through (3). Therefore, to suppress the integrator leak in the 2-1 cascaded modulator with an oversampling ratio of 128, a 60-dB dc gain is generally required in the integrators of the first stage. For an OTA design, it may be not hard to attain a dc gain of 60 db. For a class-c inverter, however, such a dc-gain requirement is a design challenge. The detailed analysis and solution will be introduced in Section III-A. C. Finite Inverter Bandwidth and SR The setup behavior of class-c inverter is different from that of traditional OTA. Fig. 5 shows the setup behavior of traditional OTA and class-c inverter when the input step is large enough. For traditional OTA, the output current in the slewing period is constant, generating a ramp output with an SR equal to ( is effective load capacitance). However, for class-c inverter, the is not constant and relative to the inverter input, displaying a curved slewing process, as shown in Fig. 5. We name the curved slewing process as the approximate slewing period. Meanwhile, a concept of effective SR is introduced that is equal to ( is the average output current in the approximate slewing period). To model the setup behavior of class-c inverter, the working status transition of the PMOS and NMOS input transistors are analyzed according to the value, as listed in Table I. Suppose that and are the effective SR at approximate

LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2433 Fig. 5. Setup behavior of traditional OTA and class-c inverter. TABLE I DIVISION OF WORKING AREA Fig. 6. (a) Traditional cascode class-c inverter and (b) gain-boost class-c inverter. slewing I and II period, respectively, we can modify the integrator setup function in the Simulink model of [17] for behavior simulation. If the integrator setup is not limited by SR, the integrator output at the period is given by where. For behavior modeling of the inverter-based modulator, (7) (11) is used to replace the previous setup function in the Simulink model of [17]. Table III lists the requirements of the inverter bandwidth and SR in different integrators according to behavior simulation. where is phase error, is feedback factor, and is the unity-gain bandwidth. Take the derivative of (7) and find the maximum value when, as follows: If, the inverter will enter in approximate slewing II period first,andthenswitchto linear settling period due to the capacitor feedback. Therefore, the integrator output expression is changed as According to the derivative continuity of (9), we can obtain (7) (8) (9) (10) Similarly, if, the inverter will experience approximate slewing I and II period and linear settling period in turn. Thus, the integrator output can be changed as (11) III. GAIN-BOOST CLASS-C INVERTER As we known, class-c inverter acts as a subthreshold amplifier, which is the most important module in the inverter-based design. In this section, the design and application of a gain-boost class-c inverter will be introduced in detail. A. Circuit Analysis A traditional cascode class-c inverter is shown in Fig. 6(a), anditsnominalsupplyvoltageis0.8v.tocopywiththe requirement of the class-c inverter (the supply voltage is slightly lower than the sum of the of PMOS and NMOS input transistors), both of the input transistors M1 and M2 use regular- core devices. At typical corner, M1 is 0.4262 V, and M2 is 0.4026 V. However, the inverter dc-gain is insufficient (52 db in our simulation) for some high-resolution applications. Fig. 6(b) adds a gain-boost module to the class-c inverter. The gain-boost module, including transistors from M5 to M8, build up two current-voltage feedback loops together with transistors M3 and M4, respectively. As a result, the output impedance and the dc gain of the gain-boost class-c inverter are enhanced. Fig. 7(a) shows the simulated dc gain and phase margin of the cascode and gain-boost class-c inverters with a 5.75-pF load capacitor. The gain-boost class-c inverter achieves 83-dB dc gain as compared with a 52-dB dc gain in the traditional cascode inverter of the same size at an 0.8-V supply. To avoid the loss of output swing, transistors M5 and M6 in the gain-boost inverter employ the low- core devices (The other transistors use regular- core devices). At a typical corner, M5 is 0.30 V, and M6 is 0.25 V. As shown in Fig. 7(b), when

2434 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 TABLE II INVERTER REQUIREMENTS IN DIFFERENT INTEGRATORS Therefore, for margin consideration, the minimum and at different s are kept to be larger than the corresponding value listed in Table II in our design. To obtain the minimum and,the threshold values for the inverter status transition in the setup period are needed. According to dc simulation at typical corner, when 0.226 V or 0.558 V, the gain-boost class-c inverter is located in approximate slewing I period; when 0.226 0.337 V or 0.558 V, the inverter is located in approximate slewing II period; when 0.337 0.430 V, the inverter enters in linear settling period. Suppose that 0.226 V initially and the inverter is in approximate slewing I period; then the minimum happens when 0.226 V, which can be obtained by dc simulation. The related mathematic equation is given as (12) Fig. 7. Cascode and gain-boost class-c inverters: (a) Frequency response and (b) dc gain versus output swing. Inverter sizes: 192 m/0.15 m, 64 m/0.15 m. the inverter output varies from 0.16 to 0.62 V, the gain-boost inverter keeps a dc gain larger than 60 db, while a worst 37-dB dc gain is obtained by the cascade inverter. In our design, the inverter output swing is controlled to be within 0.4 V. According to Section II-A, a 60-dB dc gain is generally required for the application of the 2-1 cascaded modulator. The gain-boost class-c inverter fully satisfies the dc-gain requirement, while the traditional cascade inverter fails. In addition, the gain-boost inverter consumes 34.5 W at a 0.8-V supply, where the gainboost modules consume only 3.2 W (9.3% power overhead). B. Setup Behavior In Section II-B, the setup behavior of the class-c inverter is described, and the required inverter bandwidth and are provided to satisfy the requirements of the inverterbased modulator. For the gain-boost class-c inverter, although the gain-boost modules introduce their own poles and zeros, nearly the same setup behavior can be attained by pole and bandwidth optimization [18]. In the behavior modeling of Section II-B, the and keep constant. In fact, the and vary with the initial inverter input in the setup period. where is related to transistor mobility, gate oxide capacitor and size, is the minimum slewing current in approximate slewing I period, and and are the threshold voltage and source drain voltage of PMOS input transistor, respectively. Similarly, the minimum is obtained when 0.337 V. At a typical corner, the gain bandwidth product (GBW) of the gain-boost class-c inverter is 49.45 MHz, which satisfies the bandwidth requirement in the linear settling period (as listed in Table II). Fig. 8 shows the step response of pseudo-differential integrator using a gain-boost class-c inverter with a 0.8-V supply, 5-MHz sampling frequency and 1-pF capacitive load. When the differential input step is 0.8 V, the setup process experiences approximate slewing I, and II period and linear settling period, and the setup time (to 0.01% setup error) of the inverter is less than 50 ns at typical corner. If the inverter-based integrator can setup completely, its setup accuracy mostly depends on the inverter dc gain. Fig. 9 shows the setup accuracy of the integrator based on cascade and gainboost class-c inverter. Due to the dc-gain improvement, the integrator based on the gain-boost inverter achieves the best 99.97% setup accuracy for 100-mV differential output voltage transition and keeps the setup accuracy better than 99.9% when the inverter output varies from 0.45 to 0.45 V. In contrast, a worst 2.5% setup error is produced in the integrator using the

LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2435 Fig. 8. Simulated step response of pseudo-differential class-c inverter. Fig. 10. Pseudo-differential class-c inverter: (a) PSRR simulation circuit and (b) PSRR versus frequency. Fig. 9. Setup accuracy of inverter-based integrators versus differential output swing. cascade inverter within 0.45-V output amplitude, which is inadequate for some high-resolution applications. It is noted that the simulated setup behavior above is based on a typical corner. At a slow process corner or low power supply, the inverter confronts a significant bandwidth and SR degradation, which will be analyzed in detail in Section III-E. C. PSRR and CMRR The single-ended class-c inverter has a relatively high supply voltage gain,leadingtoabadpsrr. Fortunately, pseudo-differential structure can improve the inverter PSRR specification. Fig. 10(a) shows the PSRR simulation circuit of pseudo-differential class-c inverter. If the two single-ended branches are ideally the same, their output variations induced by power supply disturbance tend to be cancelled out by each other, achieving an infinitely high PSRR. In other words, the real PSRR of the pseudo-differential inverter depends on mismatch. As seen in Fig. 10(b), the PSRR of the single-ended inverter is only 5.7 db over audio bandwidth (20 20 khz). By contrast, the pseudo-differential inverter with 2% transistor mismatch achieves 64.5-dB PSRR, which is comparable with a differential OTA. As we known, the common-mode voltage gain of a single-ended class-c inverter is equal to its differential-mode voltage gain. Therefore, for a single-ended inverter, CMRR. However, the inverter CMRR can be also improved by the pseudo-differential structure. In the pseudo-differential inverter, the CMRR specification is also dependent on the mismatch. Fig. 11(a) shows the simulation circuit of the inverter CMRR ( 5pF, 25 pf, 1 pf), in which the dc operation point of the inverter input is set to be through 1T-H inductance. The inverter CMRR versus frequency is shown in Fig. 11(b). The pseudo-differential inverter with 2% transistor mismatch achieves a CMRR better than 94 db over audio band, while a 34-dB CMRR is obtained when considering 2% mismatch. Therefore, the match between Cs and is important for CMRR optimization (the mismatch of directly affects the cancellation of common-mode disturbance in two single-ended branches). Generally, the mismatch is expected to be less than 0.5%. By comparison, the CMRR is less sensitive to the transistor mismatch, because both of two inverters behave as decent amplifiers in spite of transistor mismatch.

2436 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 TABLE III NOISE COMPARISON OF OTA AND INVERTERS Fig. 11. (a) CMRR simulation circuit and (b) CMRR versus frequency. D. Noise Assuming that both PMOS and NMOS input transistors have the same transconductance, the input referred noise voltage of the inverter is obtained as (13) where is a coefficient that is assumed to be one half for a subthreshold transistor and two thirds for a saturated transistor, is process-related coefficient, is gate oxide capacitor. The noise contribution of the gain-boost modules can be neglected approximately because the noise factors of transistors M3 and M4 are usually much smaller than those of the input transistors M1 and M2. Spectre simulation shows only 3% of the overall output noise power is generated by the PMOS and NMOS gain-boost modules. Table III lists the noise comparison among the class-c inverter and the OTA (telescopic structure, half circuit) whose transistors operate in subthreshold and saturated region, respectively. In Table III,, are the transconductances of the input transistor in the saturated and subthreshold region, respectively., are the transconductances of the OTA load transistor in the saturated and subthreshold region, respectively. Reference [1] provides that the transconductance in the subthreshold region is almost five times of that in the saturated region for a given drain source current. In our fabrication process, the ratio is changed to be 2.5. At this time, the W/L of the subthreshold transistor is almost 15 times that of the saturated transistor for the same length. If, we found the thermal noise and 1/f noise of the class-c inverter are 7.5% and 1.67% compared with those of the saturated OTA, respectively. When compared with the subthreshold OTA, the two corresponding percentages are both changed to be 25%. Some might said that such an improvement in the inverter noise characteristics is obtained at the price of increased transistor W/L, but the size of the subthreshold input transistors is still acceptable if a relatively short channel length is adopted. In our inverter design, the maximum W/L of the subthreshold PMOS and NMOS input transistors is 192 m/0.15 mand 64 m/0.15 m, respectively. Furthermore, even if the W/L of the subthreshold transistor is set as same as that of the input transistor in saturated OTA (and thus is satisfied), the thermal noise and 1/f noise of the class-c inverter is not bad in many applications (112.5% and 25% of those of the saturated OTA). E. On-Chip Body Bias Because of its subthreshold characteristics and push-pull structure, the class-c inverter is sensitive to process and variations [1], [19]. Especially when slow process corner or low is encountered, the transconductance and the drain current of M1 and M2 reduce, and thus the bandwidth and

LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2437 Fig. 12. Gain-boost class-c inverter with on-chip body bias. SR of the inverter are critically degraded, which may cause inverter-based circuits loss of function. Recent techniques have implemented body bias to compensate for parameter variations [20] [22]. However, these techniques are expensive in power and die area overhead when applied in low-power low-cost design. This paper proposes a micro-power on-chip body bias technique, which is used to compensate for the parameter degradation of the class-c inverter at slow process corner or low. As shown in Fig. 12, on-chip body bias modules (including transistors M9 and M10 and off-chip resistors R1 and R2) are introduced to compensate for the bandwidth and SR degradation, wherein M9 and M10 are biased at a subthreshold region to detect the parameter fluctuation of M1 and M2, respectively. Taking transistor M2 for example, M2 is designed to receive a NMOS body bias voltage close to GND at typical process corner. If fabrication process meets with slow process corner, the of transistors M2 and M10 increases, leading to a reduction in the drain current of the two transistors. The across resistor R2 increases, and implements forward body bias (FBB) to reduce the of transistor M2. Thus, the parameter degradation of M2 can be effectively compensated through body bias modulation. According to spectre simulation, the gain-bandwidth product (GBW) of the gain-boost inverter with/without on-chip body bias at typical process corner is 49.45 and 44.11 MHz, respectively. When at slow corner, the GBW of the inverter without body bias is only 18.85 MHz (57% reduction), while the inverter with body bias keeps a GBW of 43.73 MHz. Similarly, the inverter degradation at low can be also compensated by the body bias. In addition, the is also imposed at the body terminalsoftransistorm3(m4)andm7(m8).m3andm4receive corresponding body bias to reduce their gate-source voltages at slow process corner or low, and leave relatively larger voltage headroom for the drain-source voltages of M7 and M8. Therefore, the overdrive voltages of M7 and M8 increase, ensuring accurate bias currents for gain-boost modules. The body biases of M7 and M8 reduce the threshold voltages at slow process corner or low, and thus the inverter output Fig. 13. Simulated step response of integrators using gain-boost class-c inverter (a) without on-chip body bias and (b) with on-chip body bias. swing is improved, which is important in 0.8-V design. The drawback of the additional body bias is the increase of the body current, but the body current can be negligible if the FBB voltage is controlled to be less than 0.4 V in our fabrication process. For the integrator application, the inverter with on-chip body bias can satisfy the bandwidth requirements (as seen in Table II) under all corners, while the inverter without body bias fails at slow corner. Fig. 13 shows the simulated step response of inverter-based integrators for 100-mV differential output voltage transition under different process corners. At slow process corner, the integrator without body bias cannot setup completely, while the integrator with body bias operates normally, achieving 45.9-ns setup time. In the following, some specifications of the proposed on-chip body bias are introduced. Body Bias Range: The range is slightly less than,andthe range is slightly less than GND. Body Bias Accuracy: AsshowninFig.12,the can be expressed as (14) where is the mobility of PMOS transistor, is the capacitor of depletion area, is thermal voltage, and is subthreshold slope factor. First, from (14), the R1 accuracy directly affects the accuracy. In our design, R1 adopts off-chip resistor.

2438 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 Second, inherent error exists in the detecting-feedback loop. Suppose that the sofm1(beforebodybias)andm9 both increase due to a sow process corner, the of M9 leads to the exponential reduction of the [see (14)], while the reduction of M1 is a square root of the amount of the reduction [19]. Thus, an inherent error is produced in the process of compensation. For the inverter-based design, unexpectedly high will seriously degrade inverter specifications, so a bit more FBB is designed for margin in this paper. In addition, four ctrl bits are used to trim the output current of M9, and thus the can be calibrated for a higher accuracy. Third, to reduce the mismatch between M1 and M9, M9 is laid out adjacent to M1, and the two transistors share the same channel length. Meanwhile, the width of M9 is designed with the compromise of matching, chip area and power consumption. In addition, some filtering capacitors are added on the line around the body bias circuit, which reduces the impact of disturbance on the body bias accuracy. Lastly, the in (14) cannot be negligible when the is closely to (satisfying ), which tends to reduce the. Fortunately, the reduction leads to some FBB, which is acceptable in our design. Power and Area Overhead: The proposed on-chip body bias circuit builds up the detecting-feedback loop with only a subthreshold transistor and a resistor, which is conducive to reducing power and area overhead. The power consumption of the body bias depends on the required driven current at the body terminals. In our modulator design, a single on-chip body bias circuit generates a combination to all the class-c inverters. The body bias circuit consumes only 10 W under typical process corner, which is 4.2% of the overall power consumption of the modulator (236 W according to spectre simulation). In addition, the body bias circuit occupies 200 m, which is 0.067% of the total chip area (0.3 mm ). Noise Issue of the On-Chip Body Bias: A drawback of the body bias is that transistors M9 and M10 introduce additional noise through the body terminals of the input transistors. However, this part of the noise is acceptable in our design because: First, when the FBB voltage 0.5 V, the body transconductance is relatively smaller than the gate transconductance [23], which reduces the noise transmission to the inverter output; second, this part of the noise is mainly 1/f noise in audio design, which is largely suppressed by the autozero technique of the integrator [11]. Fig. 14. Layout of proposed modulator. IV. TEST RESULTS The inverter-based modulator is fabricated in SMIC 65-nm mixed-signal CMOS process. The die layout is shown in Fig. 14. It occupies a core area of 0.3 mm.inlayout, the class-c inverters are placed together closely to mitigate within-die PVT-variations. The sampling frequency of the proposed modulator is 5 MHz. Fig. 15(a) plots the output spectrum of the inverter-based modulator for a 3-dBFS, 2.14-kHz input at 0.8-V supply, and Fig. 15(b) shows the measured SNDR and SNR versus input Fig. 15. (a) Measured output spectrum. (b) Measured SNDR versus input amplitude at 0.8-V supply. amplitude. An input level of 0 dbfs corresponds to a sinusoidal input whose peak-to-peak differential voltage is 1.6 V. The modulator chip has a noise floor lower than 120 dbfs and achieves 91-dB peak-sndr, 94-dB peak-snr, and 98-dB DR over 20-KHz bandwidth at 0.8-V supply. The total power consumption of the modulator is 230 W at 0.8-V supply. During a

LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2439 Fig. 17. Measured peak-sndr and peak-snr versus supply voltage. TABLE IV MEASURED BODY BIAS VOLTAGES AT DIFFERENT SUPPLY VOLTAGES Fig. 16. Measured output spectrum: (a) with body bias and (b) without body bias at 0.7-V supply. temperature range of 0 C 70 C (commercial rank), the peak- SNDR and peak-snr keep above 90.5 and 93 db, respectively. At 0.8-V supply, both of the modulator chips with/without on-chip body bias can normally work. To verify the effectiveness of the on-chip body bias, both types of the modulator chips are tested at 0.7-V supply. Fig. 16 shows the modulator output spectrum at 0.7-V supply. The modulator with body bias achieves 89-dB peak-sndr and 92-dB peak-snr, while 64-dB peak-sndr and 84-dB peak-snr are obtained by the modulator without body bias. For 12 test chips with body bias, the SNDR specifications are all above 87 db, which shows a high parametric yield. By contrast, none of the chips without body bias achieve a SNDR above 65 db. Fig. 17 shows the peak-sndr and peak-snr of the modulator with/without on-chip body bias when the supply voltage ranges from 0.65 to 0.88 V. The measured body bias voltages at different supply voltages are listed in Table IV. Fig. 18 shows the measured PSRR and CMRR of the proposed modulator for a 3-dBFS (566-mV pp), 2.14-kHz input. For PSRR measurement, a 10% (160-mV pp) sine wave is added on the 0.8-V power supply without filtering Fig. 18. Measured PSRR and CMRR. capacitor, and the sine frequency is changed from 50 Hz, 1, 20, to 100 khz, respectively. By watching the modulator output spectrum, we can measure the magnitude difference ( mag) of input signal bin (2.14 khz) and the bin caused by power supply sine wave. Then, the original difference of these two signals at input terminals is subtracted from mag, and the real PSRR is obtained. Similarly, for the CMRR measurement, we add a 10% (80-mV pp) sine wave on the 0.4-V common-mode voltage without filtering capacitor. From Fig. 18, the PSRR is larger than 55 db in audio band ( 20 khz), and the CMRR is larger than 50 db, which is comparative to the OTA-based design. Table V summarizes the specifications of the inverter-based modulator and compares them with other recently pub-

2440 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013 TABLE V MODULATOR PERFORMANCE SUMMARY AND COMPARISON lished modulators [1], [4] [6], [24] [32]. Two Figures of Merit (FOMs) [6], [25] are defined as Power BW (15) FOM BW Power (16) Compared to other published modulators, the proposed modulator shows good performance in terms of FOM. V. CONCLUSION This paper proposed an audio modulator based on a gain-boost class-c inverter in SMIC 65-nm CMOS process. The gain-boost class-c inverter replaces traditional OTA to achieve excellent power efficiency and boosts its dc gain for high-resolution applications. Furthermore, on-chip body bias is used to compensate the performance degradation of the class-c inverter under slow process corner or at low. The inverter-based modulator achieves 91-dB peak-sndr, 94-dB peak-snr, and 98-dB DR over 20-KHz bandwidth at 0.8-V supply, consuming only 230 W. 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LUO et al.: A 0.8-V 230- W 98-DB DR INVERTER-BASED MODULATOR FOR AUDIO APPLICATIONS 2441 [27] Z.Yang,L.Yao,andY.Lian, A0.5-V35- W 85-dB DR doublesampled modulator for audio applications, IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 722 735, Mar. 2012. [28] Y. Chen et al., A 0.5-V 90-dB SNDR 102 db-sfdr audio-band continuous-time delta-sigma modulator, Analog Integr. Circuits Signal Process., Aug. 2011. [29] H. Park et al., A 0.7-V 870- W digital-audio CMOS sigma-delta modulator, IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1078 1088, Apr. 2009. [30] S. Pavan and P. Sankar, A 110 W single bit audio continuous-time oversampled converter with 92.5 db dynamic range, in Proc. Eur. Solid-State Circuits Conf., Sep. 2009, pp. 320 323. [31] L. Dörrer et al., A continuous time Adc for voice coding with 92 db DR in 45 nm CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 502 503, 631. [32] T. Christen, A 15-bit 140- W scalable-bandwidth inverter-based modulator for a MEMS microphone with digital output, IEEE J. Solid-State Circuits, vol. 48, no. 7, pp. 1 11, Jul. 2013. Hao Luo received the B.S. degree in electronic engineering from Huazhong University of Science andtechnology,hubei,china,in2007andtheph.d. degree in electronic engineering from Zhejiang University, Zhejiang, China, in 2012. His doctoral work focused on the design of low-voltage micro-power high-performance delta-sigma Adcs. Since 2012, he has been with Analog Devices, Beijing, China, working on high-speed high-performance DACs. Ray C. C. Cheung (M 07) received the B.Eng. and M.Phil. degrees in computer engineering and computer science and engineering from the Chinese University of Hong Kong (CUHK), Hong Kong, in 1999 and 2001, respectively, and the Ph.D. degree and D.I.C. degree in computing from Imperial College London, London, U.K., in 2007. After completing his Ph.D. study, he received the Hong Kong Croucher Foundation Fellowship for his postdoctoral study in the Electrical Engineering Department at the University of California, Los Angeles (UCLA). In 2009, he worked as a visiting research fellow in the Department of Electrical Engineering, Princeton University, Princeton, NJ, USA. He is currently an Assistant Professor in the Department of Electronic Engineering at City University of Hong Kong (City U). He is the author of 20 journal papers and over 30 conference papers. His research team, City U Architecture Lab for Arithmetic and Security (CALAS) focuses on the following research topics: reconfigurable trusted computing, SoC VLSI designs, cryptography, and embedded biomedical VLSI designs. Xiaopeng Liu received the B.S. degree in electronic science and technology from Zhejiang University, Hangzhou, China in 2009. He is currently working toward the Ph.D. degree in microelectronics at the Zhejiang University, Hangzhou. His research interests are low-power and high-reliability digital integrated circuits. Yan Han received the B.S., M.S., and Ph.D. degrees from the Electrical Engineering Department, Zhejiang University, China, in 1982, 1990, and 1995, respectively. She is currently with the Institute of Microelectronics and Optoelectronics, Zhejiang University, where she was appointed an Associate Professor in 1996, Professor in 2002, and Ph.D. supervisor in 2003. She has engaged in the teaching and scientific research in the fields of microelectronics, IC design and power devices for 30 years. She has published four textbooks and more than 100 papers, and also has 60 patent applications, and authorized more than 20 patents for invention (two PCT patents). Prof. Han is also the member of the council of China Semiconductor Industry Association (IC branch) and executive member of the council of Zhejiang Province Power Supply Society and Semiconductor Industry Association. She has undertaken more than 40 projects, such as the National 863 IC Design Major Project, the National Science & Technology Major Project of China, the National Natural Science Fund, the Zhejiang Province Natural Science Fund, and the R&D projects from corporation. Tianlin Cao is currently working toward the Ph.D. degree at the Institute of Microelectronics and Optoelectronics, Zhejiang University, Hangzhou, China. His current research mainly focuses on CMOS mixed-signal integrated circuits. His ongoing work includes high-precision bandgap reference and 18 bit sigma-delta DAC.