Measurement Results for a High Throughput MCM Funding: Paul Franzon Toby Schaffer, Alan Glaser, Steve Lipa North Carolina State University paulf@ncsu.edu www.ece.ncsu.edu/erl
Outline > Heterogeneous System Integration > DES MCM module u Package enabled power, ground and clock distribution u Measurement and simulation results > Other Chip-Package Codesign projects u SHOCC-based DSP u VLSI-centric design > Conclusions Franzon 2
Heterogeneous Systems Integration CMOS VLSI Full Custom RF Telemetry ASIC Embedded Core Novel Systems and Capabilities Smart sensors and actuators Biocomplexity Human-computer interfaces Enhanced conventional capabilities MEMS Bulk Surface Emboss Other Advanced Packaging Seamless integration Embedded Passives Franzon 3
Co-Design for Flip Chip & thin-film Impact 5% - 30% IC size reduction 150 ps clock skew reduction 25% clock power reduction Improved noise management High bandwidth memory for DSP New Ideas Use low-r HDI copper for: on-chip power/ground distn 1-level clock distribution Build high BW memory systems 512-bit buses 4 Gbps I/O signalling Toby Schaffer, Alan Glaser, Steve Lipa, Paul Franzon Franzon 4
Triple-DES Module Data Encryption Standard Module - Encrypt, Decrypt, and Cracking Franzon 5
Available Interconnect Mix u Low-cost, high-density interconnect technologies + 30 Franzon 6
Circuit Partitioning > Place key critical circuits onto substrate u Look for circuits that minimize test impact I.e. Resistant to independent process variations > Good candidates: u Global Power, Ground and Clock Franzon 7
IC Implementation > CMOS three metal, 0.6µm technology > Test structures: full scan, PRNG, SAR > 123,104 transistors > 210 pads used u inputs: 18 clock, 15 control, 64 data u outputs: 67 u power: 23, ground: 23 > 5.78mm X 3.67mm (21.2mm 2 ) > Global P/G/C distribution is provided by MCM Franzon 8
Implementation: The Chip Franzon 9
Area Array P/G/Clock Distribution Area Array P/G/Clock Distribution > eliminates large global rails Franzon 10
Power Distribution Architecture Integrated Decoupling Capacitors MCM = 700-10,000 pf/sq.cm. IC = 2.5-5.0 pf/sq.mm. (at 5% fill : 12.5-25 pf/sq.cm) Would not work for MCM-C/L: - via inductance too high (0.05 nh vs. 0.5 nh) Franzon 11
Power Supply Distribution VDD GND VDD GND Voltage drop is given by the equation: IR = J ρ Z (100 / %)( p / 8)(1 W / ) ln( p / W 2 2 2 m, sh P P Given the maximum allowed IR drop, it is possible to solve for %, the required metal coverage, iteratively. p ) Adapted from: p W p Power Supply Distribution and Other Wiring Issues for Deep-Submicron ICs by W.T. Lynch of Semiconductor Research Corporation Franzon 12
Power Distribution - IR Drop Copper Metallization High density solder bumping releases on-chip wiring resources. 100 Current Density % Metal fill for P/G 10 1 0.1 0.01 Requirements to keep IR drop to 15 mv. 100 200 500 1000 Ground Solder Bump Pitch (µm) Franzon 13
Noise Control Low MCM-D via inductance and integrated decoupling capacitor reduces on-chip resources required for AC noise control. Conventional 35x35 mm flip-chip BGA Package 35 x 35 mm flip-chip MCM-D Franzon 14
Global Clock Distribution > Distribute Global Clock on low-r MCM layers u Reduced clock skew (shallower clock tree) u Reduced clock power (smaller crowbar current) u Transmission line distribution schemes Franzon 15
Global Clock Distribution > i.e. For conventional clock trees: Franzon 16
Obtaining Test Results High-impedance active probe for measuring Vdd noise and clock skew Franzon 17
Measured IC Performance (Speed) 140 120 100 Speed (MHz) 80 60 40 20 IC 1 IC 2 IC 3 0 B C F G MCM ID Franzon 18
Measured DES MCM Performance (Speed) 120 100 Speed (MHz) 80 60 40 20 IC1 - IC2 IC2 - IC3 0 C F G MCM ID > 110 MHz 3DES @ 7 Gb/s Franzon 19
Clock Distribution - DES MCM Franzon 20
DES MCM Clock Distribution Franzon 21
DES Clock Distribution Franzon 22
GCLK Distribution on MCM > 25% GCLK Power Reduction when GCLK distributed on MCM Franzon 23
DES MCM - Substrate Mesh 12,000 components λ/10 rule 9 mω/square 890 pf/sq.cm. 4.4 ph/square 20 min sim time Substrate IC Franzon 24
DES IC - Pipeline Stage Noise Model Solder bump On-chip decoupling (including ESR) PWL macromodel of core noise Clock buffer and load DC macromodel of core Franzon 25
DES MCM Vdd Plane Noise Franzon 26
Conclusions > Using MCM for global power, ground and clock distribution u Low clock skew u Low clock power u Reduces on-chip metal demands u Acceptable IR drop and di/dt noise > Simulation results correspond well with measurement > High density packaging useful for solving large DSP problems > Codesign requires a common environment Franzon 31