A Digital Self-Sustained Phase Shift Modulation Contol JPE??-??-?? http://dx.doi.og/0.6/jpe.??? A Digital Self-Sustained Phase Shift Modulation Contol Stategy fo Full-Bidge LLC Resonant Convete Kai Zheng, Dongfang Zhou *, Jianbing Li *, Li Li *, and Yujing Zhao * * Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China Abstact A digital self-sustained phase shift modulation (DSSPSM) stategy that allows fo good soft switching and dynamic esponse pefomance in the context of step vaiations is pesented in this pape. The woking pinciple, soft switching chaacteistics, and voltage gain fomulae of the LLC convete with DSSPSM have been povided sepaately. Futhemoe, the method fo ealizing DSSPSM is poposed. Specifically, some key components of the DSSPSM ae caefully investigated, including paamete vaiation analysis, stat-up pocess, and zeo-cossing captue of the esonant cuent. The simulation and expeiment esults veify the feasibility of the poposed contol method; it is obseved that the zeo voltage switching of the switches and zeo cuent switching of the ectifie diodes can be easily ealized in context of step load vaiations. Key wods: LLC esonant convete, Soft switching, Dynamic esponse, Step load vaiations, Taveling-wave tube micowave tansmitte, Phase shift modulation I. INTRODUCTION The taveling-wave tube (TWT) micowave tansmitte has a wide bandwidth and a high gain, and it can be used fo vaious applications, including communication, ada, electonic countemeasue, and space applications. The powe convete is one of the key modules of micowave tansmitte, which is used to powe the TWT. With the development of moden micowave systems, some paamete citeions of TWT powe convete ae gadually inceasing, including efficiency, powe density, and dynamic esponse []-[]. The esonant convete topologies ae usually adopted to meet the high efficiency equiement of the TWT powe convete, such as the paallel esonant convete, LCC esonant convete, and full-bidge phase-shift convete [4]-[5]. Moeove, LLC esonant convete has been attacting moe and moe attention fo its inheent meits, including high efficiency, high powe density, soft switching, and low EMI [6]-[0]. Theefoe, the LLC convete is a pefeed Manuscipt eceived Sep. 0, 05; accepted Jan. 6, 06 Recommended fo publication by Associate Edito???. Coesponding Autho: 4055@qq.com Tel: +86-86-55-08, Zhengzhou Infomation Science and Technology Institute * Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China candidate fo a micowave tansmitte. The TWT is a special load fo the powe convete. The TWT load is pone to sudden and epeated change with pulse modulation of pulsed micowave tansmitte. Consideing these step load vaiations, the powe convete should be of good dynamic esponse and soft switching chaacteistics. At pesent, the powe convete has not been studied in context of such step load vaiations widely, especially with espect to tansient soft switching. To ovecome these dawbacks, the convete topology should be impoved, and the novel applicable contol stategy should be developed []-[4]. The self-sustained phase shift modulation (SSPSM) has been poposed fo esonant convetes in [5] and [6]. This contol scheme is inspied by the timing signal fom the esonant cuent. In this manne, the contol system is insensitive to the paamete uncetainties, and the gate pulses of the switches can be changed adaptively accoding to the opeating condition. As opposed to the conventional fequency modulation (FM) contol, SSPSM has much smalle fequency vaiation ange [5], which makes it easy to optimize the magnetic components and ealize miniatuization. As opposed to the conventional phase shift modulation (PSM) contol, SSPSM can impove the soft switching in a wide opeation ange, which can achieve highe efficiency [5]. Thee has been consideable eseach on the SSPSM
Jounal of Powe Electonics, Vol.??, No.??,?? [6]-[8]. The woking pinciple and design method of full-bidge LCC convete unde SSPSM have been poposed in [5]-[7]. The sliding-mode contol of full-bidge LCC convete unde SSPSM has been intoduced in [8]. These efeences mainly concentate on the basic woking pinciples of full-bidge LCC convete unde SSPSM, in which the chaacteistics of SSPSM associated with the paamete vaiations have not been widely analyzed. Besides, in these efeences, the SSPSM is ealized by analog cicuits, which ae quite complicated, and some contol functions ae difficult to implement. Fo example, the loop fo compensating the sawtooth wave adaptively is difficult to achieve. Consequently, the digital self-sustained phase shift modulation (DSSPSM) used fo othe novel convete topologies in context of paamete vaiations need to be investigated futhe. The majo contibution of this pape is the design and development of a novel DSSPSM contol stategy. Some new technical factos of DSSPSM, which ae used fo the LLC convete in context of the step load vaiations have been poposed. Fist, the woking pinciple of LLC convete with DSSPSM is discussed, which povides new insights into the impovement of soft switching and dynamic esponse chaacteistics of LLC convetes. Second, the paamete design method of DSSPSM is pesented, which is used to implement the soft switching. Thid, the concete ealization method of DSSPSM is elaboated, especially in the applications associated with paamete vaiations. Finally, the tansient soft switching of esonant convete is analyzed and evaluated. The est of this pape is oganized as follows. We discuss the full bidge LLC esonant convete unde DSSPSM in Section II. Afte that, we pesent the hadwae and softwae ealization of the DSSPSM in Section III. Then, we elaboate key pats of the DSSPSM design in Section IV. Simulation and expeimental esults ae given in Section V. Finally, some concluding emaks ae povided in Section VI. II. FULL BRIDGE LLC RESONANT CONVERTER UNDER DSSPSM A. Cicuit Analysis Fig. shows the schematic of the poposed full-bidge LLC convete with voltage multiplie ectifie unde DSSPSM. Switches pais Q and Q as well as Q and Q 4 fom the full-bidge invete. The esonant inducto L, tansfome magnetic inducto L m, and esonant capacito C fom the LLC esonant tank. The diodes D 5, D 6, and capacitos C 5 and C 6 fom the symmetical multiplie ectifie. The DSSPSM and popotional plus integal (PI) contol ae adopted to implement the feedback contol. Fig.. Schematic of the poposed full-bidge LLC convete. The main featues of the poposed convete can be summaized as follows. ) Because the phase-shifting angle is the main contol vaiable to egulate the convete unde DSSPSM, the switching fequency of the convete with DSSPSM has minimalistic vaiance, which can optimize the magnetic components and passive filtes with espect to volume and losses [5]. ) The timing signal of DSSPSM is deived fom the esonant cuent, which can fom a contol loop. In this way, the contol scheme can eliminate the sensitivity to the paamete vaiations, and the contol system can compensate fo the vaiations. ) The contol scheme can ensue that the esonant cuent i L lags behind the invete output voltage v ab unde any opeating condition to ealize zeo voltage switching (ZVS) of the switches by adjusting the shifting-phase angle, which esults in inceased efficiency and impoved eliability. Besides, the zeo cuent switching (ZCS) of the ectifie diodes can be easy to ealize unde DSSPSM. 4) A symmetical voltage multiplie ectifie is poposed, which benefits the ealization of high-voltage output and miniatuization of powe convete. B. Woking Pinciple Fig. shows the woking pinciple of the DSSPSM. γ a is the phase angle between the evese esonant cuent i L and dain-souce voltage v ao of Q, and γ b is the phase angle between the esonant cuent i L and dain-souce voltage v bo of Q 4. The sawtooth wave v st is a modulation wave, whose amplitude should be almost constant. v ca and v cb ae the two modulation lines; v ca is the uppe modulation line, v cb is the unde modulation line, and v ca v cb. If the gadient k of v st is assumed to be constant, v ca and v cb can be descibed by the following functions, v ca = kγ a, v cb = kγ b. Usually, v ca is kept constant, and v cb is used as the contol vaiable to egulate the convete.
A Digital Self-Sustained Phase Shift Modulation Contol Fig.. Woking pinciple of DSSPSM. Fig. shows the typical wavefoms of LLC convete unde DSSPSM. In tems of the timing diagams, thee ae ten switching modes in a complete switching cycle, and the esonance mode between two components (L and C ) and esonance mode between thee components (L, L m and C ) ae involved. i L is the esonant cuent, and i Lm is the magnetizing cuent. When i L > i Lm, the two component esonance occus. When i L = i Lm, the thee component esonance occus. The stating moment of the two component esonance (the stopping moment of thee component esonance) coesponds to the time that the switches ae tuned on o off, such as the time t 0 and t. The stopping moment of two component esonance (the stating moment of thee component esonance) is ielevant to the time that the switches ae tuned on and off, such as the time t and t. The enegy of the esonant tank is sent to the load by the fom (i L i Lm ). Q Q Q Q 4 Q v ab Q i Lm Q Q Q 4 Q C. Soft-Switching Analysis ) ZVS Analysis of the Switches In ode to ealize ZVS of the switches, accoding to Fig., the polaity of the esonant cuent i L should be kept in the dead time T d between Q & Q o Q & Q 4, and the limited condition is given by Td tb ta () The function can be futhe expessed as v T () d ( ca V ) p fs whee, fs is the switching fequency, V p is the amplitude of the sawtooth wave v st. Function () can be ealized by selecting suitable paametes. In this situation, the esonant cuent i L lags behind the invete output voltage v ab, and the zeo cossing points of the esonant cuent ae within the invete output voltage pulse v ab. When one switch is tuned on, the esonant cuent flows though the antipaallel body diode of this switch, and then the dain-souce voltage of the switch is clamped to zeo. In this case, the ZVS can be implemented. ) ZCS Analysis of the Rectifie Diodes Unde DSSPSM, if γ a γ b > 0, the peiod that v ab = 0 is cetain to exit in one switch cycle. In Fig., T z epesents the peiod that v ab = 0. At the beginning of v ab = 0 (such as the moment t c in Fig. ), if i L = i Lm, the convete has enteed into the thee component esonance. If i L > i Lm, the load powe is supplied by the LC (L and C ) esonant tank, the esonant cuent i L will decease fast, and soon i L = i Lm. T epesents this deceasing peiod, and if T z > T, the convete will ente into the thee-component esonance. In ode to ealize ZCS of the ectifie diodes, the thee component esonance should always exit in one switch cycle, and the limited condition is given by T t t () The function can be futhe expessed as vcb T ( ) V f (4) Function (4) can be ealized by selecting suitable paametes. In this situation, all ectifie diodes will be switched off with zeo cuent educing the evese ecovey losses of diodes which contibutes to inceased efficiency. d c ca s i L i L- i Lm t 0 t t t t 4 t 5 t 6 t 7 t 8 t 9 Fig.. Typical wavefoms of LLC convete unde DSSPSM. v C D. Modeling Analysis In ode to guide the cicuit analysis and paamete design, based on Fist Hamonic Appoximation (FHA) method [9]-[ 0], the LLC convete model unde DSSPSM is built. The fundamental component v ab of the invete output voltage v ab can be expessed as a b a b vab Vin cos sin st 4 (5)
4 Jounal of Powe Electonics, Vol.??, No.??,?? Effective value V ab of v ab is descibed as V a b ab Vin cos The symmetical multiplie ectifie can be simplified as Fig. 4. The fundamental component v s of the invete voltage v s can be expessed as V o vs sin( st R ) (7) The RMS value (V s ) of v s is descibed as (6) Vs Vo / (8) The fundamental component i s of the invete cuent i s can be expessed as is Io sin st R (9) The equivalent eflected impedance R eq of multiplie ectifie can be deived as vs 4Ro R eq i (0) Though the above analysis, the equivalent cicuit of the LLC convete can be shown as Fig. 4. The equivalent eflected impedance R ac on the pimay side of the tansfome can be expessed as R ac s () n Req The open loop tansfe function of LLC esonant tank can be given as s G j j L s j L R j L R js Lm R ac s m ac s m ac j C j L R s s m ac () Consideing (6), (8), and (), the DC gain of the esonant tank can be obtained as nvs Vo n G js () Vab Vin cos a b / The DC gain of the LLC convete can be expessed as V M k F Q Vin n cos a b n [ ( / F ) / k ] Q ( F / F ) o a b,, cos G j fs L L whee, F, m C k, Q f L 4R n, o s (4) f. L C Fig. 4. Equivalent cicuit of the LLC convete ( Symmetical multiplie ectifie and Equivalent cicuit of the LLC convete). Accoding to (5), the voltage gain cuves of full-bidge LLC convete with DSSPSM ae plotted, as shown in Fig. 5. Accoding to this figue, the voltage gain M inceases with espect to the incease of phase b. By contolling the phase b, v cb is contolled, and the convete can be egulated. In addition, as the fequency atio F deceases, the phase b vaies little with the same gain change, and the gain ange gets wide, as shown in Fig. 5. As the quality facto Q inceases, the voltage gain M gets little, as shown in Fig. 5..5 F=0.7 F=0.8 F=0.9.5 0.5 0.5 0.5 0 F= F=. F=. 0 0.5.5.5 Q=0. 0 0.5.5.5 b Q=0.6 Q= b Q=.5 Q= Fig. 5. Voltage gain cuves vesus b ( Q =0., a =0.9, n= and F=0.8, a =0.9, n=). III. REALIZATION OF DSSPSM A. Hadwae Realization Fig. 6 shows the hadwae ealization schematic of DSSPSM. Fig. 7 illustates the main wavefoms of DSSPSM based on DSP. DSP boad by Texas Instuments, TMS0F8, is pimaily used to implement the contol scheme. Geneal time of DSP event manage is set to the continuous incemental mode, and used to geneate the sawtooth wave v st. The compaison unit egiste CMPR and CMPR sepaately epesent the modulation line v ca and v cb. The logic signal v and v ae sepaately obtained by compaing v st with v ca and v cb. The zeo-cossing moment of esonant cuent can be captued by DSP, and then the signal v can be easily geneated. In Fig. 6, the logic signals v, v, and v can be conveted to the dive signals LQ LQ4, though logic opeation of NOT gate, NAND gate, and RS flip-flop. Afte that, the dead-time of LQ-LQ4 is geneated by the RCD cicuit. Lastly, two dive chips Si85 ae used to dive the switches.
A Digital Self-Sustained Phase Shift Modulation Contol 5 Zeo-cossing NOT 4 CAP V GPIOA5 V PWM V PWM DSP LQ Rq 5v Cq Dq LQ Rq C 4 Cq 0u 5 Dq 6 7 Disable 8 VIN VIB VDDI GNDI DISABLE RC VDDI NAND NAND NAND NAND U4 SI85 Si85 VDDA VOA GNDA VDDB VOB GNDB R Q' S Q RS- R Q' S Q LQ LQ LQ4 LQ RS- v D 6 5 VG 4 C VS 0u 9 C VG 9 0u The pogam flowchat of time undeflow inteupt is elatively simple. The time undeflow inteupt is stimulated, when the time counte becomes zeo. The zeo-cossing squae wave v is geneated in this pogam, and then the ADC convete is stimulated by the time undeflow inteupt flag. Fig. 8(c) shows the ADC inteupt pogam flowchat. The ADC inteupt is stimulated by ADC flag. Afte the sampled value is obtained, the feedback contol signal can be calculated by the digital position PI contol algoithm, and then the compaison egiste CMPR is updated by the feedback contol value. v LQ LQ4 Rq Dq R4q D4q Cq C4q 5v C6 0u Disable 4 5 6 7 8 VIN VIB VDDI GNDI DISABLE RC VDDI U5 SI85 Si85 VDDA VOA GNDA VDDB VOB GNDB Fig. 6. Hadwae schematic of DSSPSM. 6 5 4 9 9 D VG C4 VS 0u C5 VG4 0u Stat Obtaining the captued peiod Fig. 7. Main wavefoms of DSSPSM based on DSP. B. Softwae Realization Fig. 8 shows the softwae ealization flowchats of DSSPSM. The softwae is mainly composed of the main pogam and the inteupt pogams, and the inteupt pogams consist of captue inteupt, time-undeflow inteupt, and analog-to-digital convesion (ADC) inteupt. Fig. 8 shows the main pogam flowchat. The pogam initialization is caied out fist, and then the main pogam will wait to espond to the inteupt flags. Fig. 8 shows the captue inteupt pogam flowchat. The captue inteupt is stimulated at the zeo-cossing moment of the esonant cuent. The zeo-cossing moment can be captued, and the zeo-cossing peiod can be calculated. If the captued peiod belongs to the pedetemined scope, the time counte will etun to zeo. If the captued peiod does not belong to the pedetemined scope, the time peiod egiste will be updated. Does captued peiod belong to pedetemined scope? Time counte etuns to zeo End Yes No Updating the time peiod egiste (c) Fig. 8. Softwae flowchats of DSSPSM ( Main pogam, Captue inteupt pogam, and (c) ADC inteupt pogam). IV. KEY PARTS OF DSSPSM DESIGN A. DSSPSM Design Regading Paamete Vaiations Paamete vaiations of the convete, such as step load vaiations, will bing some poblems to the DSSPSM design. Fo instance, the sawtooth wave may have distotions. Fig. 9 shows the simulation esults of the sawtooth wave when the load is changed epeatedly between 600 Ω and 00 Ω evey
4 5 6 6 Jounal of Powe Electonics, Vol.??, No.??,??.5 ms. We can find that the amplitude of the sawtooth wave begins to change at the load change moment. This phenomenon may lead to some mistakes, and some measues should be taken. Fig. 9. Simulation esults of sawtooth wave changes with espect to step load vaiations. Fig. 0 shows the two concete mistakes associated with the sawtooth wave of DSSPSM. As shown in Fig. 0, duing the peiod T (k+), fo the zeo-cossing moment of the esonant cuent advances, the captued zeo-cossing peiod T (k+) is less than the nomal value T (k), and the amplitude V p of the sawtooth wave is less than the nomal amplitude T PR of sawtooth wave v st in the peiod T (k+). In this situation, if the modulation line v ca is lage than the amplitude V p, the logic signal v can not be obtained in a coect manne. As a esult, the gate pulses of switches will be wong. As shown in Fig. 0, duing the peiod T (k+), fo the zeo-cossing moment of the esonant cuent delays, the captued zeo-cossing peiod T (k+) is lage than the nomal value T (k), and two sawtooth waves will appea in the peiod T (k+). In this situation, the logic signal v will be wong. Besides, if the amplitude V p of the second sawtooth wave in the peiod T (k+) is lage than the modulation line v cb, the logic signal v can not be obtained in a coect manne. As a esult, the gate pulses of switches will be wong. Fig. 0. Concete mistakes of sawtooth wave of DSSPSM ( The fist mistake and The second mistake). In ode to solve the two mistakes as shown in Fig. 0, some measues should be taken. ) Fo the mistake as shown in Fig. 0, the paamete vaiations should be concened when selecting the value of v ca peviously. The value of v ca should be always less than the nomal amplitude T PR of sawtooth wave v st. Moeove, if the captued amplitude V p is less than v ca, the value of v ca should be immediately updated as v ca V (5) p ) Fo the mistake as shown in Fig. 0, if the captued zeo-cossing peiod T (k+) is lage than the nomal value T (k), the value of T PR should be immediately updated as T V (6) B. Stat-up Pocess PR Thee ae seveal situations that waant consideation in the stat-up pocess. ) The esonant cuent may not be egula and stable in the stat-up pocess, and the DSSPSM may become uneliable. ) The sudden powe-on may impact the convete hadwae, and fo this, soft stating should be ealized. In ode to solve these two poblems, following measues should be taken. ) In the stat-up peiod, the taditional phase shift contol is adopted at fist. When the convete becomes stable, the DSSPSM contol begins to wok. ) The contol signal v cb vaies slowly fom zeo to the pedetemined value, and the pulse width of the invete output voltage v ab becomes wide gadually. In this way, soft stating can be ealized. C. Zeo-Cossing Captue Zeo-cossing captue is a vital pat of the DSSPSM design. If the zeo-cossing moment can not be captued coectly, the DSSPSM may not wok. Fig. shows the zeo-cossing detection cicuit. The hall-effect cuent senso TBC06DS. is adopted to sample the esonant cuent, and the zeo-cossing squae-wave of the esonant cuent is obtained though the ultafast compaato LT70. Howeve, the ising edge and falling edge of the squae-wave may have some chatteing. Theefoe, the figuation function of this squae-wave needs to be achieved though RC filte and NOT gate 74LS4. In this way, the zeo-cossing signal can be obtained in a coect manne, and sent to the captue pot of the DSP. Iin U0 + 0 OUT.V TBC06DS. Iout.V D D K K.V R R 4 U DIA+ VCC DIA- OUTA DIB- OUTB DIB+ GND p LT70 Fig.. Zeo-cossing detection cicuit. 8 7 6 5.V K R4 K R 00pF C 4 5 6 7 A Y A Y A Y GND U0 74HC4 VCC A6 Y6 A5 Y5 A4 Y4 4 0 9 8.V 74LS4 Zeo-cossing V. SIMULATION AND EXPERIMENTAL RESULTS A. Simulation Results In ode to evaluate the pefomance of the poposed DSSPSM contol stategy, diffeent simulation esults ae
A Digital Self-Sustained Phase Shift Modulation Contol 7 pesented in this section. The simulations ae pefomed in MATLAB/SIMULINK softwae. The simulation and expeiment ae caied out on a 40 W LLC esonant convete with an input voltage of 70 V. The esonant fequency is set to 5 khz with L as 64.6 μh and C as 0 nf. The magnetic inducto L m is set to 00 μh, and, thus, L /L m is.. The main paametes of the designed convete ae shown in Table I. TABLE I CONVERTER PARAMETERS Input voltage (V in ) Output voltage (V o ) Resonant inducto (L ) Resonant capacito (C ) Tansfome magnetic inducto (L m ) Tansfome tuns atio (n) Output capacito (C o ) Constant angle (γ a ) 70 V 450 V 64.6 μh 0 nf 00 μh : 0 μf 70 Fig. shows the typical simulation wavefoms of DSSPSM, including the esonant cuent i L, sawtooth wave v st, the dain-souce voltage v ao of switch Q, the dain-souce voltage v bo of switch Q 4, and the invete output voltage v ab. As can be seen, the simulation esults ae in accodance with the theoetical analysis. i L (A) v st (V) v ao (V) v bo (V) v ab (V) vaiations. As can be seen, i L can keep lagging behind v ab when the load esistance becomes lage o less. In this situation, when one switch is tuned on, the esonant cuent flows though the antipaallel body diode, the dain-souce voltage is clamped to zeo, and then the ZVS can be ealized. il(a), vab/00(v) il(a), vab/00(v) vab 00 vab 00 Fig. 4. Simulation wavefoms of esonant cuent i L and invete output voltage v ab with espect to step load vaiations ( Fom 600 Ω to 00 Ω and Fom 00 Ω to 600 Ω). B. Expeimental Results In ode to investigate the pefomance of the poposed DSSPSM contol stategy, a laboatoy pototype has been built, as shown in Fig. 5. The paametes of the convete ae listed in Table. t(s) Fig.. Typical simulation wavefoms of DSSPSM. Fig. shows the simulation wavefom of output voltage v o with espect to step load vaiations. The load esistance is changed between 600 Ω and 00 Ω evey.5 ms. As can be seen, the output voltage v o has a little ipple against the step load changes, and the convete stays stable in the entie pocess. Fig. 5. Laboatoy pototype. v o R=00Ω R=600Ω t(s) Fig.. Simulation wavefom of output voltage v o with espect to step load vaiations. ) Steady State Pefomance Fig. 6 shows the expeimental wavefoms of esonant cuent i L and zeo-cossing squae signal v at full load. As can be obseved, thee is no chatteing in the ising edge and falling edge of v, and the zeo-cossing moment can be coectly captued by DSP. Fig. 4 shows the simulation wavefoms of esonant cuent i L and invete output voltage v ab egading step load 0 s/div, v : V/div, i L : A/div
8 Jounal of Powe Electonics, Vol.??, No.??,?? Fig. 6 Expeimental wavefoms of esonant cuent i L and zeo-cossing squae wave v. Fig. 7 shows the expeimental wavefoms of esonant cuent i L and invete output voltage v ab at full load, half load and light load (0% load). As can be seen, in diffeent load conditions, i L can lag behind v ab, and all switches can implement ZVS which educes switching losses of switches. Fig. 8. Expeimental cuent wavefoms of the ectifie diodes D 5 and D 6 ( Full load, Half load and (c) Light load (0% load)). ) Dynamic State Pefomance Fig. 9 shows the tansient wavefoms of the evese esonant cuent -i L and invete output voltage v ab unde conventional PSM in context of step load vaiations. As can be seen, the cuent i L cannot keep lagging behind the voltage v ab, and sometimes the soft switching chaacteistic of the convete is not so good fo the step load vaiations. v ab i L (c) 5 s/div, v ab : 70 V/div, i L : 4 A/div Fig. 7. Expeimental wavefoms of esonant cuent i L and invete output voltage v ab ( Full load, Half load and (c) Light load (0% load)). Fig. 8 shows the expeimental cuent wavefoms of the ectifie diodes D 5 and D 6 at full load, half load, and light load (0% load). All ectifie diodes can implement ZCS which educes evese ecovey losses of ectifie diodes. 0 s/div, v ab : 70 V/div, i L : 4 A/div Fig. 9. Tansient wavefoms unde PSM fo the step load vaiations. Fig. 0 shows the tansient wavefoms of the esonant cuent i L, invete output voltage v ab and the output voltage v o unde DSSPSM egading step load vaiations. Fig. 0 shows the wavefoms when the load esistance inceases. Fig. 0 shows the wavefoms when the load esistance deceases. The load esistance is changed between 600 Ω and 00 Ω, and the load changing tansition time is less than 00 ns. As can be seen, i L can keep lagging behind v ab fo the step load vaiations, and ZVS can be always implemented. Also, the convete is of good dynamic pefomance, and the output voltage v o can be tightly egulated to 450 V. The esponse time is less than 50 s, and the output voltage oveshoot and undeshoot ae about 4 V, which is less than % of 450 V. (c) 0 s/div, i D5 : 0.5 A/div
A Digital Self-Sustained Phase Shift Modulation Contol 9 REFEREES 00 s/div, v ab : 70 V/div, i L : 4 A/div, v o : 5 V/div Fig. 0. Tansient wavefoms unde DSSPSM fo the step load vaiations ( Fom 600 Ω to 00 Ω and Fom 00 Ω to 600 Ω). ) Efficiency Analysis Fig. shows the efficiency cuve accoding to the load. The figueindicates that the efficiencies unde diffeent load conditions ae highe than 9%, and thei vaiance is minimalistic. The soft switching of LLC convete with DSSPSM can be ealized unde diffeent load conditions leading to an impoved efficiency in a wide opeation ange. Fig.. Efficiency cuve accoding to load. VI. COLUSIONS In this pape, a novel DSSPSM contol stategy is poposed, and a full bidge LLC esonant convete with multiplie ectifie unde DSSPSM is intoduced. The woking pinciple, soft-switching chaacteistic, and ealization pocedue of DSSPSM ae sepaately analyzed. Simulation and expeimental esults validate that the poposed LLC convete unde DSSPSM has good dynamic pefomance and soft switching chaacteistics in context of the step load vaiations. Theefoe, the poposed DSSPSM contol stategy is valuable fo impoving the efficiency and powe density of the powe convete. In addition, the simulated esistance load is used to epesent a TWT in the simulation and expeiment, which is easy to test the steady-state and dynamic-state pefomance of DSSPSM. In futue wok, we will be aiming fo pactical application of DSSPSM in the TWT micowave tansmitte. [] N. V. Bijeev, A. Malhota, and V. Kuma, Design and ealization challenges of powe supplies fo space TWT, in Poc. IEEE Vacuum Electonics Confeence, pp. 4-4, 0. [] I. Babi and R. Gules, Isolated DC-DC convetes with high-output voltage fo TWTA Telecommunication Satellite Applications, IEEE Tans. Powe Electon., Vol. 8, No. 4, pp. 975-984, July 00. [] D. Spingmann, D. Chan, and T. Schoemehl, A 50W Ka-band NanoMPM, in Poc. IEEE Vacuum Electonics Confeence, pp. -4, 04. [4] A. K. Singh, P. Das, and M. Pahlevaninezhad, A novel high output voltage DC-DC LLC esonant convete with symmetic voltage quaduple ectifie fo RF communications, in Poc. IEEE Telecommunications Enegy Confeence, pp. -6, 04. [5] G. Zhang, D. Zhou, and L. Yang, Development of novel type of two-stage high voltage convete, Chinese Jounal of Vacuum Science and Technology, Vol., No. 5, pp. 49-45, May 0. [6] B. Yang, Topology investigation fo font end DC/DC powe convesion fo distibuted powe system, Ph.D. Dissetation, Vigina Polytechnic Institute and State Univesity, USA, 00. [7] R. Beianvand, B. Rashidian, M.R. Zolghadi, and S. M. H. Alavi, A design pocedue fo optimizing the LLC esonant convete as a wide output ange voltage souce, IEEE Tans. Powe Electon., Vol. 7, No. 8, pp. 749-76, Aug. 0. [8] W. Feng, F. C. Lee, and P. Mattavelli, Simplified optimal tajectoy contol (SOTC) fo LLC esonant convetes, IEEE Tans. Powe Electon., Vol. 8, No. 5, pp. 45-46, May 0. [9] X. D. Li, LLC-type dual-bidge esonant convete: Analysis, design, simulation, and expeimental esults, IEEE Tans. Powe Electon., Vol. 9, No. 8, PP. 4-4, Aug. 04. [0] Y. Zhao, X. Xiang, W. Li, and X. He, Advanced symmetical voltage quaduple ectifies fo high step-up and high output-voltage Convetes, IEEE Tans. Powe Electon., Vol. 8, No. 4, PP. 6-6, Ap. 0. [] H. Pan, C. He, and F. Ajmal, Pulse-width modulation contol stategy fo high efficiency LLC esonant convete with light load applications, IET Powe Electon., Vol. 7, No., PP. 887 894, Nov. 04. [] N. Shafiei, M. Odonez, M. Cacium, and M. Edington, High powe LLC battey chage: Wide egulation using phase-shift fo ecovey mode, in Poc. IEEE Enegy Convesion Congess and Exposition, PP. 07-04, 04. [] X. F. Sun, Y. F. Shen, Y. Zhu, and X. Guo, Inteleaved boost-integated LLC esonant convete with fixed-fequency PWM contol fo enewable enegy geneation applications, IEEE Tans. Powe Electon., Vol. 0, No. 8, PP. 4-46, Aug. 05. [4] C. Buccella, C. Cecati, H. Latafat, and P. Pape, Obseve-based contol of LLC DC/DC esonant convete using extended descibing functions, IEEE Tans. Powe Electon., Vol. 0, No. 0, PP. 588-589, Oct. 05. [5] Z. Y. Mohamed, and K. J. Paveen, A eview and pefomance evaluation of contol Techniques in esonant convetes, in Poc. IEEE Industial Electonics Society,
0 Jounal of Powe Electonics, Vol.??, No.??,?? PP. 5-, 004. [6] Z. Y. Mohamed, P. Humbeto, and K. J. Paveen, Self-sustained phase shift modulated esonant convetes: Modeling, design, and pefomance, IEEE Tans. Powe Electon., Vol., No., PP. 40-44, Ma. 006. [7] Z. Y. Mohamed, Contol and modeling of high fequency esonant DC/DC convetes fo poweing the next geneation micopocessos, Ph. D. Dissetation, Queen s Univesity, Canada, 005. [8] L. S. Joge, C. Miguel, and M. Jaume, Modeling and pefomance analysis of the DC/DC seies paallel esonant convete opeating with discete self-sustained phase-shift modulation technique, IEEE Tans. Ind. Electon., Vol. 56, No., PP. 697-705, Ma. 009. [9] X. Fang, H. Hu, J. Shen, and I. Bataseh, Opeation mode analysis and peak gain appoximation of the LLC esonant convete, IEEE Tans. Powe Electon., Vol. 7, No. 4, PP. 985-995, Ap. 0. [0] Y. J. Pak, H. J. Kim, J. Y. Chun, J. Y. Lee, Y. G. Pu, and K. Y. Lee, A wide fequency ange LLC esonant contolle IC with a phase-domain esonance deviation pevention cicuit fo LED backlight units, Jounal of Powe Electonics, Vol. 5, No. 4, pp. 86-875, July 007. Kai Zheng was bon in Henan Povince, China. He eceived his B.S. and M.S. degees in Electical Engineeing fom New Sta Reseach Institute of Applied Technology, Hefei, China, in 005 and 009, espectively. He is pesently woking towad his Ph.D. degee in Electical Engineeing at Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China. His cuent eseach inteests include modeling and contol of esonant powe convetes. include powe electonics and contol. Li Li was bon in Henan Povince, China. She eceived his B.S. degee in Electical Engineeing fom Noth China Univesity of Wate Resouces and Electic Powe, Zhengzhou, China, in 0. She is pesently woking towad his M.S. degee in Electical Engineeing at Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China. He cuent eseach inteests include topology and contol of powe convetes. Yujing Zhao was bon in Henan Povince, China. He eceived his B.S. degee in Electical Engineeing fom Tianjin Univesity, Tianjin, China, in 0. He is pesently woking towad his M.S. degee in Electical Engineeing at Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China. His cuent eseach inteests include topology and contol of powe convetes. Dongfang Zhou was bon in Zhejiang Povince, China. He eceived his B.S. degee in Electical Engineeing fom Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China, in 98. He eceived his M.S. degee in Electical Engineeing fom Xidian Univesity, Xi an, China, in 989. He eceived his Ph.D. degee in Electical Engineeing fom Zhejiang Univesity, Hangzhou, China, in 005. He is cuently a Pofesso in Zhengzhou Infomation Science and Technology Institute. His cuent eseach inteests include powe electonics and contol fo micowave systems. Jianbing Li was bon in Hubei Povince, China. He eceived his B.S., M.S. and Ph.D. degees in Electical Engineeing fom Zhengzhou Infomation Science and Technology Institute, Zhengzhou, China, in 999, 00 and 006, espectively. He is cuently an Associate Pofesso in Zhengzhou Infomation Science and Technology Institute. His cuent eseach inteests