current is ultimately chosen according to the conversion speed.

A Circuit for All Seasons Behzad Razavi The Flash ADC Flash analogtodigital converters (ADCs) find wide application both as standalone components and as building blocks of more complex systems. This architecture dates back to at least the early 1960s. For example, in a patent filed in 1963, Stephenson [1] describes the parallel ADC as a known technique. In this article, we study the properties and design issues of this topology. Basic Architecture To convert an analog signal to digital form, we can compare its value against a number of equally spaced reference voltages that span the expected range of input amplitudes. Shown in Figure 1, an Nbit flash ADC employs N comparators along with a resistor ladder consisting of N equal segments. The sampling function, which is necessary for conversion from continuous time to discrete time, can be realized within the comparators or as an explicit operation preceding this circuit. In response to j 1 in 1 j 1, comparators number one through j produce a logical one at their outputs and the remaining, a logical zero. This thermometer code is then converted to a binary or gray output. The simplicity and elegance of this architecture make it suitable for various conversion rates so long as the speedpower tradeoff remains linear. A favorable tradeoff is obtained if the ADC incorporates a comparator topology with zero static power a StrongArm latch [][4], for example. As explained below, the ladder s static Digital Object Identifier 10.1109/MSSC.017.71998 Date of publication: 5 August 017 current is ultimately chosen according to the conversion speed. Design Issues The principal drawback of the flash ADC is the exponential growth of its cost as a function of resolution. The cost includes power consumption, input capacitance, comparator kickback noise, chip area, and difficulties in routing the signals. We elaborate on some of these issues here. Suppose we wish to double the resolution of a 5b flash stage. The analog leastsignificant bit (LSB) value is halved and so must be the comparator voltage. Using the MOS threshold mismatch equation D TH = ATH/ WL, where ATH is a constant and WL denotes j1 j Figure 1: The flash architecture. N Comparators A j1 A j A the channel area, we observe that WL must quadruple. Since the number of comparators is also doubled, the input capacitance rises by a factor of eight. This trend underscores the need for comparator offset cancellation for resolutions of 4 b and above. The kickback noise of the comparators also becomes problematic as the resolution increases. This noise arises on each clock edge, as the comparators input transistors couple internal transitions to the input terminals. Consider, as an example, the StrongArm latch input path shown in Figure. We identify two kickback mechanisms: 1) when nodes and fall, they draw a transient current from the inputs through CGD 1 and Decoder Digital Output IEEE SOLIDSTATE CIRCUITS MAGAZINE Summer 017 9

1 CK C GD1 C GS1 C GD7 M P M CK C GS C GD a continuoustime differential pair to reduce both the inputreferred offset and the kickback noise, but at the cost of considerable power penalty. The kickback noise currents in Figure 3 ultimately flow from REF and, demanding that these voltages have a low impedance. This issue translates to a high power dissipation in the reference buffers. One can place a capacitor between these two nodes, but the value of such a capacitor must be very large; otherwise, it slows down the settling of the ladder voltages. Another difficulty in flash ADC design relates to the appearance of bubbles in the thermometer code. Suppose the offset of comparator number j, osj, in Figure 1 exceeds 1 LSB. Then, for Figure : The input stage of a StrongArm latch. CGD, a significant effect as M1 and M enter the triode region and these capacitances increase, and ) when CK goes high, MCK turns on, drawing a transient current from CGS 1 and CGS before P falls enough to turn M1 and M on. Note that both effects intensify as M1 and M are chosen wider so as to reduce the comparator offset. The trouble with kickback noise is that it corrupts the conversion of the present sample and/or lasts long enough to affect the next sample. The kickback noise currents drawn from in 1 and in in Figure contain a significant differential component, leading to a differential error voltage if this component flows through a finite impedance. This is inevitable as the kickback sees either the ladder or the ADC input buffer. Consider the singleended model shown in Figure 3, where I1, f, In model the REF comparators kickback noise and are assumed approximately equal. Using superposition, it can be shown that the voltage disturbance at node j on the ladder is given by ( n j) j j = I u R u, (1) where Iu is the value of I1, f, In, and Ru the ladder unit resistance. The greatest error occurs at j = n/ and is equal to ( n / 8) IuRu. To maintain this disturbance below 1 LSB, Ru must be sufficiently small, dictating a lower bound for the ladder s power consumption. It is interesting to note that this power is, in fact, proportional to the sampling rate because, at higher speeds, the kickback noise has less time to subside, and vice versa. One can precede a comparator design such as the StrongArm latch with R u 1 R u j R u n 1 R u I 1 Figure 3: A model of kickback noise injected into the ladder. I j I n REF j 1 1 in 1 j osj, () this comparator and comparator number j 1 produce a zero and a one, respectively, leading to a thermometer code of the form f11010f. Called a bubble, the outofplace zero generated by comparator number j can create large errors as it travels through the decoder. We generally employ some means of bubble correction; for example, we can detect this situation and swap the outputs of comparators j and j 1 [5]. Alternatively, the decoder can simply count the total number of ones in the thermometer code and deliver the result as the final output. Fully Differential Design In most applications, the ADC must digitize a differential analog input, necessitating that the comparators compare this signal to a differential reference. Figure 4 illustrates one approach, where a StrongArm latch incorporates two differential pairs that produce currents proportional to in1 r1 and in r, with r1 and r representing differential reference voltages. These currents are summed at the drains of M1 M4 to y ield I1 I? ( in1 r) ( in r1) = ( in1 in) ( r1 r). The topology of Figure 4 entails three issues. First, the commonmode (CM) level of r1 and r must 10 Summer 017 IEEE SOLIDSTATE CIRCUITS MAGAZINE

CM I 1 I 1 1 S1 c 1 S 3 S 4 1 M CK M CK1 r1 A S 5 r1 r1 M 3 M 4 S 6 B CK M CK c t 1 t S (c) CK M M CK Figure 4: A comparator input stage based on two differential pairs, the effect of different CM levels, and an alternative input stage. accurately track that of in 1 and in. To see this point, we note in Figure 4 that, even if in1 in. r1 r at t = t1, each differential pair experiences a heavy imbalance and suffers from a low transconductance. As a result, the mismatches at nodes and and beyond contribute a higher inputreferred offset. Second, the circuit introduces four devices, M1M4 at the input and must therefore deal with the offsets of two differential pairs. Specifically, we have I1 I? ( in1 in) [( r1 os1) ( r os)], where os 1 and os denote the offset voltages of, and M 34,, respectively. Third, the input CM range of the circuit has a lower bound given by GS1 4 and the voltage headroom necessary for MCK 1 and MCK. This issue limits the flash ADC s fullscale range, especially at low supply voltages. Shown in Figure 4(c) is an alternative fully differential input stage that ameliorates the foregoing difficulties. Here, a single differential pair senses an input difference produced by the input switching network and given by ( in1 in) ( r1 r). In other words, this circuit performs the subtraction in the voltage domain [while in Figure 4, it is done in the current domain]. The comparator operates in three phases. First, CK is low, S1 S4 are on, and the input network samples the analog signal on C1 and C. Next, these switches turn off and S5 and S6 turn on, producing at A and B a voltage difference nearly equal to ( in1 in) ( r1 r). With a slight delay, CK then goes high to activate the comparator core circuit. This delay is necessary to guarantee that A B departs significantly from zero before M1 and M begin to amplify. In contrast to the structure of Figure 4, the input stage shown in Figure 4(c) deals with the offset of only one differential pair and does not require accurate tracking between the input and reference CM levels. Furthermore, capacitive coupling in this arrangement allows railtorail input swings. et another advantage The principal drawback of the flash ADC is the exponential growth of its cost as a function of resolution. is that the analog sampling provided by C1 and C in Figure 4(c) obviates the need for a lumped frontend sampler for the ADC. On the other hand, the clocking and and discharge ac tions in Figure 4 tend to integrate the input and hence smear the sampling point, generally necessitating that the ADC employ an explicit sampleandhold circuit. The use of the sampling network in Figure 4(c) does raise the input capacitance presented to the analog input. To ensure negligible attenuation of ( in1 in) ( r1 r), C1 and C must be chosen much greater than the capacitances seen at A and B. For example, suppose C1 = C = 5 Cin, where Cin includes the gate capacitance of the differential pair and the drain capacitance of S3 (or S4 ). This means that the input capacitance in the sampling mode is more than five times that in Figure 4. When S5 and S6 turn on, AB reaches [( in1in) ( r1 r)][ C1/( C1 Cin)] = (5/6)[( in1in) ( r1 r)], exhibiting a loss of about 17%. It is possible to reduce the capacitance presented to the analog input by changing the switching sequence in Figure 4(c). We first turn on S3S6 to sample the differential reference on the capacitors and then turn off these switches and turn on S1 and S. The differential voltage thus generated between A and B is the same as before, but the capacitance seen by in 1 and in is now given by the series combination of the input capacitors and Cin. This ap proach, however, faces two drawbacks: 1) C1 and C load the resistor ladder, causing a long settling time for r1 and r, and ) the circuit no longer samples the analog input, requiring a frontend sampler for the ADC. A similar timing is described in [6]. Flash ADC ariants A number of architecture and circuit techniques have been invented to ease the tradeoffs in flash stages. We study two here. Recall that the input capacitance of the converter grows rapidly with IEEE SOLIDSTATE CIRCUITS MAGAZINE Summer 017 11

A 1 1 1 r1 r1 m 1 r1 A 1 1 (c) Figure 5: A flash stage showing comparators input differential pairs, characteristics provided by the differential pairs, and (c) a flash stage using interpolation. F F CK 1 CK Flash ADC F F Figure 6: A flash stage preceded by a polarity detector and the resulting characteristic. (s) Pipelined ADC res (c) SAR ADC Flash ADC DAC SAR Logic Figure 7: The use of flash stages in pipelined converters, SAR ADCs, and (c) DR modulators. (s) the resolution. It is possible to alleviate this issue through the use of interpolation. In this context, we view each comparator as a differential pair followed by a latch. Let us first examine the differential pair outputs in Figure 5 as in varies from below r1 to above r. Noting that 1 = 1 for in = r1 and = for in = r, we can construct the characteristics shown in Figure 5. Now, we recognize that 1 = at in = m = ( r1 r)/. That is, a latch sensing these two voltages (or 1 and ) can detect when in crosses midway between r1 and r. As depicted in Figure 5(c), the interpolating flash [7] architecture doubles the resolution without doubling the number of differential pairs. The performance improvement afforded by interpolation appears almost free, but it does require that the comparators include a differential pair and suffer from its power dissipation. In particular, a simple StrongArm latch would not suffice for the comparator design in this environment. Another approach to reducing the complexity and power is illustrated in Figure 6 [8]. Here, a frontend comparator detects, under the command of CK1, the polarity of in in and accordingly routes the inputs through two of the switches such that the flash stage always senses a positive differential value. Plotted in Figure 6, the resulting characteristic 1 Summer 017 IEEE SOLIDSTATE CIRCUITS MAGAZINE

P T 1 R 1 R C 1 C Figure 8: The MOS crystal oscillators patented by Luscher. C C R b M DD R 0 is an example of folding and produces the most significant bit. Once F F settles, CK strobes the flash ADC so as to generate the remaining bits. We observe that the overall input capacitance, power, and complexity are approximately halved as the number of comparators drops from N N/ to 1. These benefits accrue at the cost of more than twofold reduction in speed: not only must the frontend comparator respond to an input difference of, say, 0.5 LSB and activate the proper Q C C Q 1 Q Figure 9: A threepoint oscillator using an inverter and its simplified model. switches, but also F F must also settle while the switches drive the input capacitance of the flash stage. Note that the offset of the frontend comparator must remain lower than 1 LSB. Applications Flash ADCs exhibit a favorable tradeoff between speed and power dissipation at low resolutions, e.g., in the range of 46 b. As such, they prove useful in extremely highspeed applications, e.g., in optical communication receivers that deal with highorder modulation schemes such as 64 quadrature amplitude modulation. Moreover, flash stages can augment other ADC architectures. As shown in Figure 7, a flash stage preceding a pipelined converter considerably reduces the magnitude of the residue generated by the first op amp, res, thereby relaxing its gain, linearity, and output swing requirements. Similarly, as depicted in Figure 7, a flash front end can 1) save some clock periods in the convergence of a successive approximation (SAR) ADC and ) reduce the digitaltoanalog converter settling time in the remaining SAR cycles. Another application is in DR modulators [Figure 7(c)], where a multibit (flash) quantizer lowers both the overall quantization noise and the integrator output swing. As standalone circuits, flash ADCs perform full conversion in one clock cycle with the aid of massive comparator redundancy, the extreme opposite of how a SAR structure operates. For resolutions up to about 6 or 7 b, the flash topology provides a powerefficient, highspeed solution. Questions for the Reader 1) In Figure 4, why can we not apply in 1 and in to M1 and M and r1 and r to M3 and M4? ) How does the characteristic shown in Figure 6 change if the frontend comparator has an offset equal to 1.5 LSB? Answers to Last Issue s Questions 1) Estimate the oscillation frequency of Figure 8 if R1 and R are large. The impedance presented to the crystal consists of the series combination of C1 and C and a negative resistance. This net capacitance must be added to the parallel crystal capacitance in the parallel resonance frequency equation. ) How does the finite output impedance of M1 and M in Figure 9 affect the oscillator s performance? Since M1 and M are in parallel, we can return to the threepoint oscillator model shown in Figure 9 and ask how the finite resistance R0 affects the startup condition. If R0 is large, we can transform the parallel combination of R0 and C to a series combination having an equivalent resistance approximately equal to 1/( R0C ~ ). Thus, this positive resistance weakens the effect of the negative resistance provided by the transistors. References [1] B. Stephenson, Analog to digital converter, U.S. Patent 3 98 014, Jan. 10, 1967. [] J. Montanaro, R. Witek, K. Anne, and A. Black, 60MHz 3b 0.5W CMOS RISC microprocessor, IEEE J. SolidState Circuits, vol. 31, pp. 17031714, Nov. 1996. [3] T. Kobayashi, K. Nogami, T. Shirotori, and. Fujimoto, A currentmode latch sense amplifier and a static power saving input buffer for lowpower architecture, in Proc. LSI Circuits Symp. Dig. Tech. Papers, June 199, pp. 89. [4] B. Razavi, The StrongArm latch, IEEE SolidState Circuits Mag., vol. 7, pp. 117, Spring 015. [5]. Garuts,. u, E. Traa, and T. amaguchi, A dual 4bit GS/s full Nyquist analogtodigital converter using a 70ps silicon bipolar technology with borosenicpoly process and coupling implant, IEEE J. SolidState Circuits, vol. 4, pp. 16, Apr. 1989. [6] I. Mehr and L. Singer, A 55mW 10bit 40Msample/s Nyquistrate CMOS ADC, IEEE J. SolidState Circuits, vol. 35, pp. 31835, Mar. 000. [7] C. Lane, 0bit 60 Msps flash ADC, in Proc. Bipolar Circuits and Technology Meeting, Sept. 1989, pp. 4447. [8] B. erbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and G. van der Plas, A.6 mw 6 bit. GS/s fully dynamic pipeline ADC in 40nm digital CMOS, IEEE J. Solid State Circuits, vol. 45, pp. 080090, Oct. 010. IEEE SOLIDSTATE CIRCUITS MAGAZINE Summer 017 13