nvidia GeForce FX 5700 Ultra (NV36) Graphics Processor Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0515 www.chipworks.com
Table of Contents Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Analysis 3.1 Package Cross-Section 3.2 Solder Bumps 3.3 Package 3.4 External Solder Balls 4 Process Analysis 4.1 General 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 MOS Transistors and Poly 4.7 Resistors 4.8 Isolation 4.9 Wells and Epi 5 Materials Analysis 5.1 TEM EDS Analysis of Dielectrics, Metals and Transistors 5.2 FESEM EDS Analysis Die and Package 5.3 Spreading Resistance Profiles
Table of Contents Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package Photograph 2.1.2 Bottom Package Photograph 2.1.3 Side View Package Photograph 2.1.4 Package X-Ray Top View 2.1.5 Die Photograph 2.1.6 Die Markings A 2.1.7 Die Markings B 2.1.8 Die Markings C 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Die Edge Seal 2.2.6 Typical Bond Pads 2.2.7 Typical Bond Pad 2.2.8 Minimum Spaced Bond Pads 3 Package Analysis 3.1.1 Top View Package X-Ray Showing Cross-Section Location 3.1.2 Full Package Cross-Section 3.1.3 General Structure of Package 3.1.4 Die Attach Compound 3.1.5 FESEM Image of Die Edge Saw Cut Notch 3.2.1 Solder Bump 3.2.2 FESEM Image of Solder Bump 3.2.3 Solder Bump Bond Pad Interface 3.2.4 FESEM Image of Solder Bump Bond Pad Interface 3.2.5 Solder Bump Package Interface 3.2.6 FESEM Image of Solder Bump Package Interface 3.3.1 PWB Package 3.3.2 PWB Package Through Hole Via 3.3.3 PWB Package Via 3.4.1 Package External Solder Ball
Overview 1-2 3.4.2 FESEM Image of Package External Solder Ball 3.4.3 Package External Solder Ball Package Interface 3.4.4 FESEM Image of Package External Solder Ball Package Interface 3.4.5 Package External Solder Ball Circuit Board Interface 3.4.6 FESEM Image of Package External Solder Ball Circuit Board Interface 4 Process Analysis 4.1.1 General Structure 4.1.2 Die Edge 4.1.3 Die Edge Seal 4.2.1 Bond Pad 4.2.2 Bond Pad Edge 4.2.3 Bond Pad Open Window Edge 4.3.1 Passivation 4.3.2 ILD 8 and Passivation 4.3.3 TEM Image of ILD 8 and Passivation 4.3.4 ILD 7 4.3.5 TEM Image of ILD 7 4.3.6 ILD 6 4.3.7 TEM Image of ILD 6 4.3.8 ILD 5 4.3.9 TEM Image of ILD 5 4.3.10 ILD 4 4.3.11 TEM Image of ILD 4 4.3.12 ILD 3 4.3.13 TEM Image of ILD 3 4.3.14 ILD 2 4.3.15 TEM Image of ILD 2 4.3.16 ILD 1 4.3.17 TEM Image of ILD 1 4.3.18 PMD and STI 4.3.19 TEM Image of PMD 4.4.1 Metal 9 Minimum Space 4.4.2 TEM Image of Metal 9 Barrier 4.4.3 Metal 8 Minimum Pitch 4.4.4 Metal 7 Minimum Pitch
Overview 1-3 4.4.5 Metal 6 Minimum Pitch 4.4.6 Metal 5 Minimum Pitch 4.4.7 Metal 4 Minimum Pitch 4.4.8 Metal 3 Minimum Pitch 4.4.9 Metal 2 Minimum Pitch 4.4.10 Metal 1 Minimum Pitch 4.4.11 TEM Image of Metal 1 4.5.1 Via 8 Minimum Pitch 4.5.2 Via 8 4.5.3 Via 7 Minimum Pitch 4.5.4 Via 6 Minimum Pitch 4.5.5 Via 5 Minimum Pitch 4.5.6 Via 4 Minimum Pitch 4.5.7 Via 3 Minimum Pitch 4.5.8 Via 2 Minimum Pitch 4.5.9 Via 1 Minimum Pitch 4.5.10 TEM Image of Via 1 4.5.11 Contacts to Polycide 4.5.12 Contacts to Substrate 4.5.13 Minimum Pitch Contacts 4.5.14 TEM Image of Top of Contact 4.5.15 TEM Image of Bottom of Contact to Gate 4.5.16 TEM Image of Bottom of Contact to Substrate 4.6.1 Minimum Space NMOS Transistors (Silicon Etch) 4.6.2 Minimum Space PMOS Transistor (Silicon Etch) 4.6.3 MOS Transistor (Glass Etch) 4.6.4 TEM Image of MOS Transistor 4.6.5 TEM Image of MOS Transistor Gate 4.6.6 TEM Image of Gate Oxide 4.7.1 Poly Resistor Cross-Section 4.8.1 Minimum Width Isolation 4.9.1 N-Well 4.9.2 Edge of N-Well Beneath STI 4.9.3 SCM of N-well and P-Epi
Overview 1-4 5 Materials Analysis 5.1.1 FESEM Image of the NV36 General Structure 5.1.2 TEM EDS Spectrum of Passivation Nitride 5.1.3 TEM EDS Sprectrum of ILD 8-1 Silicon Nitride 5.1.4 TEM EDS Spectrum of ILD 8-2 Silicon Oxide 5.1.5 TEM EDS Spectrum of ILD Nitride 5.1.6 TEM EDS Spectrum of ILD Oxide 5.1.7 TEM EDS Spectrum of ILD FSG 5.1.8 TEM EDS Spectrum of PMD FSG 5.1.9 TEM EDS Spectrum of PMD PSG 5.1.10 TEM EDS Spectrum of PMD Nitride 5.1.11 TEM EDS Spectrum of Metal 9 Barrier (Bottom) Tantalum 5.1.12 TEM EDS Spectrum of Metal 9 Barrier (Top) TiN 5.1.13 TEM EDS Spectrum of Metal 1 Ta Liner 5.1.14 TEM EDS Spectrum of Via Ta Liner 5.1.15 TEM EDS Spectrum of Transistor Sidewall Spacer Nitride 5.1.16 TEM EDS Spectrum of Transistor Gate Cobalt Silicide 5.1.17 TEM EDS Spectrum of Contact Cobalt Silicide 5.2.1 FESEM EDS Spectrum of Metal 4 Copper 5.2.2 FESEM EDS Spectrum of Metal 1 Copper 5.2.3 FESEM EDS Spectrum of Tungsten Contact 5.2.4 FESEM EDS Spectrum of Bond Pad Metals 5.2.5 FESEM EDS Spectrum of Package PbSn Solder Bump 5.2.6 FESEM EDS Spectrum Solder Bump Package Nickel Plate 5.2.7 FESEM EDS Spectrum Package Copper Metal 5.2.8 FESEM EDS Spectrum Package Solder Ball Nickel UBM 5.2.9 FESEM EDS Spectrum Package PbSn Solder Ball 5.3.1 SRP of N-Well 5.3.2 SRP of P-Well 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions
Overview 1-5 1.2 List of Tables 2.1.1 Package and Die Dimensions 3.1.1 Package Composition and Dimensions 4.3.1 Dielectric Composition and Vertical Dimensions 4.4.1 Metallization Vertical Dimensions 4.4.2 Metallization Horizontal Dimensions 4.5.1 Via and Contact Dimensions 4.6.1 Transistor and Polycide Horizontal Dimensions 4.6.2 Transistor and Polycide Vertical Dimensions 4.8.1 Isolation Horizontal Dimension 4.9.1 Wells and Epi Vertical Dimensions
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