MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Power Module> TEGRATED POWER FUNCTIONS TYPE TYPE 600/30A low-loss CSTBT TM inverter bridge with N-side three-phase output DC-to-AC power conversion TEGRATED DRIE, PROTECTION AND SYSTEM CONTROL FUNCTIONS r upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (U) protection. r lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (U), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a U fault (Lower-side supply). Input interface : 3, 5 line (High Active) UL Approved : Yellow Card No. E80276 APPLICATION AC00~200 three-phase inverter drive for small power motor control. Fig. PACKAGE OUTLES 3 2.7 5.5 7. (.78).78 ±0.2 A =.78 ±0.2 B = 4.32 ±0.2 2.04 ±0.3 5.6 B A B A B A B A B A 2 D 28 27 26 25 24 23 22 2 2098 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2 3 29 30 Type name, Lot No. QR C CODE 32 33 34 35 36 37 38 2-φ3.3 6.6 ±0.3 7.62 ±0.3 7.62 ±0.3 7.62 ±0.3 7.62 ±0.3 3.3 ±0.3 3.95 ±0.3 3.3 ±0.3 46 ±0.2 3.25 52.5 E 0.5.5 2 C 5-φ2.2(DEPTH2.6) C-C 35.9 ±0.5 (φ3.5) φ3.3 (φ3.7) Note: All outer lead terminals are with lead free solder (Sn-Cu) plating. 7.7 7.7 (.96) (5.5) 0.5 (3.5) (.75) 0.5 ().55 3. ±0. (2.9) (.6) (0.75) DETAIL D.5 F (2.78) (3.5) 2.2 (2.8) (.7) (3) (2.2) HEAT SK SIDE (0.6) () () DETAIL E (0 ~5 ) Dimensions in mm (2.2) (.7) TERMAL CODE UFS 20 NO 2 (UPG) 2 UN 3 UFB 22 N 4 P 23 WN 5 () 24 FO 6 UP 25 CFO 7 FS 26 C 8 (PG) 27 NC 9 FB 28 N 0 P 29 (WNG) () 30 (NG) 2 P 3 NW 3 WFS 32 N 4 (WPG) 33 NU 5 WFB 34 W 6 P 35 7 () 36 U 8 WP 37 P 9 (UNG) 38 NC
MAXIMUM RATGS (Tj = 25 C, unless otherwise noted) ERTER PART CC CC(surge) CES ±IC ±ICP PC Tj Note : TC measurement point Applied between P-NU, N, NW Applied between P-NU, N, NW Tc = 25 C Tc = 25 C, less than ms Tc = 25 C, per chip 2 Symbol Ratings Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature CONTROL (PROTECTION) PART 450 500 600 30 60 90.9 20~+50 Symbol Ratings D Control supply voltage Applied between P-NC, N-NC 20 DB Control supply voltage Applied between UFB-UFS, FB-FS, WFB-WFS 20 FO IFO SC Input voltage Fault output supply voltage Fault output current Current sensing input voltage Applied between UP, P, WP, UN, N, WN- NC Applied between FO-NC Sink current at FO terminal Applied between C-NC 0.5~D+0.5 0.5~D+0.5 0.5~D+0.5 ma TOTAL SYSTEM Symbol Ratings CC(PROT) Self protection supply voltage limit D = 3.5~6.5, Inverter part (short circuit protection capability) Tj = 25 C, non-repetitive, less than 2 400 Tc Tstg Module case operation temperature Storage temperature (Note ) 20~+00 40~+25 C C iso Isolation voltage 60Hz, Sinusoidal, AC minute, All pins to heat-sink plate 2500 rms 8mm IGBT Chip position FWDi Chip position Control Terminals 8mm Power Terminals Groove Tc point Heat sink side A A W C
THERMAL RESISTANCE Symbol Rth(j-c)Q Rth(j-c)F Symbol CE(sat) EC ton trr tc(on) toff tc(off) ICES Junction to case thermal resistance (Note 2) Inverter IGBT part (per /6 module) Inverter FWD part (per /6 module) ELECTRICAL CHARACTERISTICS (Tj = 25 C, unless otherwise noted) ERTER PART Collector-emitter saturation voltage FWDi forward voltage Switching times Collector-emitter cut-off current D = DB = 5 IC = 30A, Tj = 25 C = 5 IC = 30A, Tj = 25 C Tj = 25 C, IC = 30A, = 0 CC = 300, D = DB = 5 IC = 30A, Tj = 25 C, = 0 5 Inductive load (upper-lower arm) CE = CES 3 Tj = 25 C Tj = 25 C Min. Note 2 : Grease with good thermal conductivity should be applied evenly with about +00µm~+200µm on the contacting surface of and heat-sink. The contacting thermal resistance between case and heat sink (Rth(c-f)) is determined by the thickness and the thermal conductivity of the applied grease. r reference, Rth(c-f) (per /6 module) is about 0.3 C/W when the grease thickness is 20µm and the thermal conductivity is.0w/m k Limits Typ. Max.. 2.8 Limits Min. Typ. Max. 0.70.60.70.50.30 0.30 0.50.50 0.40 2.0 2.20 2.00.90 0.80 2.0 0.60 0 CONTROL (PROTECTION) PART Symbol Limits Min. Typ. Max. D = DB = 5 Total of P-NC, N-NC 7.00 ma ID Circuit current = 5 UFB-UFS, FB-FS, WFB-WFS 0.55 ma D = DB = 5 Total of P-NC, N-NC 7.00 ma = 0 UFB-UFS, FB-FS, WFB-WFS 0.55 ma FOH SC = 0, FO terminal pull-up to 5 with 0kΩ 4.9 Fault output voltage FOL SC =, IFO = ma 0.95 SC(ref) Short circuit trip level Tj = 25 C, D = 5 (Note 3) 0.43 0.48 0.53 I Input current = 5.0.5 2.0 ma UDBt Trip level 0.0 2.0 UDBr Control supply under-voltage Reset level 0.5 2.5 Tj UDt protection 25 C Trip level 0.3 2.5 UDr Reset level 0.8 3.0 tfo th(on) Fault output pulse width ON threshold voltage CFO = 22nF (Note 4).0.8 2.3 2.6 ms th(off) th(hys) OFF threshold voltage ON/OFF threshold hysteresis voltage Applied between UP, P, WP, UN, N, WN-NC 0.8 0.5.4 0.9 Note 3 : Short circuit protection is functioning only at the low-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating. 4:Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions works. The fault output pulsewidth tfo depends on the capacitance of CFO according to the following approximate equation : CFO = 2.2 0-6 tfo [F]. C/W C/W ma
MECHANICAL CHARACTERISTICS AND RATGS Mounting torque Weight Heat-sink flatness Note 5 : Flatness measurement position REMENDED OPERATION CONDITIONS CC D DB D, DB tdead fpwm IO PW(on) PW(off) NC Tj Symbol + Heat sink side Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Output r.m.s. current Minimum input pulse width NC voltage variation Junction temperature Mounting screw : M3 Measurement position + 4 Recommended : 0.78 N m (Note 5) Applied between P-NU, N, NW Applied between P-NC, N-NC Applied between UFB-UFS, FB-FS, WFB-WFS r each input signal, Tc 00 C Tc 00 C, Tj 25 C CC = 300, D = DB = 5, fpwm = 5kHz P.F = 0.8, sinusoidal PWM fpwm = 5kHz Tc 00 C, Tj 25 C (Note 6) (Note 7) 200 CC 350, Below rated current 3.5 D 6.5, 3.0 DB 8.5, Between rated current and 20 C Tc 00 C,.7 times of rated current N-line wiring inductance less Between.7 times and than 0nH (Note 8) 2.0 times of rated current Between NC-NU, N, NW (including surge) Min. 0.59 50 Limits Typ. 2 Max. 0.98 00 Recommended value Min. Typ. Max. 0 3.5 3.0 2 0.3 300 5.0 5.0 400 6.5 8.5 20 2 6 Note 6 : The allowable r.m.s. current value depends on the actual application conditions. 7:Input signal with ON pulse width less than PW(on) might make no response. 8:IPM might make delayed response (less than about 2ec) or no response for the input signal with off pulse width less than PW(off). Please refer Fig. 2 about delayed response and Fig. 6 about N-line inductance. 3mm Heat sink side.5 3.0 3.6 5.0 20 5.0 25 N m g µm / khz Arms C
Fig. 2 ABOUT DELAYED RESPONSE AGAST SRTER PUT OFF SIGNAL THAN PW (off) (P side only) P side control input Internal IGBT gate Output current Ic Fig. 3 THE TERNAL CIRCUIT UFB UFS P UP FB FS P P WFB WFS P P N UN N WN NC CC UN N WN GND HIC CC HIC2 CC HIC3 CC LIC B S B S B S UOUT OUT WOUT NO C CFO CFO 5 t2 t Real line... off pulse width > PW(off) : turn on time t Broken line... off pulse width < PW(off) : turn on time t2 IGBT IGBT2 IGBT3 IGBT4 IGBT5 IGBT6 C Di Di2 Di3 Di4 Di5 Di6 P U W NU N NW NO
Lower-arms control input Protection circuit state Internal IGBT gate Output current Ic Sense voltage of the shunt resistor Fault output Control input Protection circuit state Control supply voltage D Output current Ic Fault output Fig. 4 TIMG CHARTS OF THE PROTECTIE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter) a. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input L : IGBT OFF. a7. Input H a8. IGBT OFF state in spite of input H. [B] Under-oltage Protection (Lower-arm, UD) a UDr SET b a2 SC a5 a3 SC reference voltage UDt 6 a4 CR circuit time constant DELAY b2 a6 a7 a8 SET b3 b4 b5 b6 b. Control supply voltage rising : After the voltage level reaches UDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UDt). b4. IGBT turns OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UDr). b7. Normal operation : IGBT ON and carrying current. b7
[C] Under-oltage Protection (Upper-arm, UDB) c. Control supply voltage rises : After the voltage level reaches UDBr, the circuits start to operate. c2. Protection circuit state reset : IGBT ON and carrying current. c3. Normal operation : IGBT ON and carrying current. c4. Under-voltage trip (UDBt). c5. IGBT OFF inspite of control input condition, but there is no FO signal output. c6. Under-voltage reset (UDBr). c7. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage DB Output current Ic Fault output Fig. 5 REMENDED MCU I/O TERFACE CIRCUIT MCU UDBr High-level (no fault output) 5 line 0kΩ UDBt 7 UP,P,WP,UN,N,WN NC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application s printed circuit board. The input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. Fig. 6 REMENDED WIRG AROUND THE SHUNT RESISTOR NC NO NU N NW c c2 c3 SET c4 c5 c6 c7 Each wiring inductance should be less than 0nH Equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=00µm, length=7mm Shunt resistor The GND wiring from NO, NC should be as close to the shunt resistors as possible
Fig. 7 TYPICAL APPLICATION CIRCUIT EXAMPLE C: Tight tolerance temp-compensated electrolytic type C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering CONTROLLER 5 line 5 line C3 C3 C3 C3 C2 C C2 C C2 C UFB UFS P UP FB FS P P WFB WFS P WP N UN N WN NC NO N WN CC UN CC CC CC GND HIC HIC2 HIC3 LIC B S B S B S UOUT OUT WOUT CFO NO C C4(CFO) Long GND wiring here might generate noise to input and cause IGBT malfunction. 8 Note : Input drive is High-active type. There is a 2.5kΩ(Min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 2 :Thanks to HIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 3 :FO output is open drain type. It should be pulled up to the positive side of a 5 power supply by a resistor of about 0kΩ. FO output pulse width is determined by the external capacitor (CFO) between CFO and NC terminals (e.g CFO = 22nF tfo =.8ms (typ.)) 4 :To prevent erroneous protection, the wiring of A, B should be as short as possible. 5 :The time constant RC5 of the protection circuit should be selected in the range of.5-2. SC interrupting time might vary with the wiring pattern. Tight tolerance, temp-compensated type is recommended for R, C5. 6 :All capacitors should be mounted as close to the terminals of the as possible. (C: good temperature, frequency characteristic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.) 7 :To prevent surge destruction, the wiring between the smoothing capacitor and the P, N terminals should be as short as possible. Generally a 0.-0.22µF snubber between the P-N terminals is recommended. 8 :It is recommended to insert a Zener diode (24/W) between each pair of control supply terminals to prevent surge destruction. 9 :If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point. 0 : The reference voltage ref of comparator should be set up the same rating of short circuit trip level (sc(ref): min.0.43 to max.0.53). : OR logic output high level should exceed the maximum short circuit trip level (sc(ref): max.0.53). CFO A C + - + - + ref ref - ref Comparator B R B R P U W NW Too long wiring here might cause short-circuit. If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. OR Logic C5 C5 B R C5 NU N M N C Shunt resistors External protection circuit