Unit 3: Integrated-circuit amplifiers (contd.) COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is grounded, also the drain resistor R D replaced by a constant-current source I. The currentsource load can be implemented using a PMOS transistor and is therefore called an active load, and the CS amplifier of Fig. 1(a) is said to be active-loaded. Before we consider the small-signal operation of the active-loaded CS amplifier, it is important to know that Q 1 is biased to have I D = I. But the DC voltages at the drain and at the gate are developed by a circuit which is a part of a larger circuit in which negative feedback is utilized to fix the values of V DS and V GS. We shall assume that these circuits are in such a way that they bias the MOSFET in operate in the saturation region. Fig.1 (a) Active-loaded common-source amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit diagram and using the smallsignal model explicitly. Since we analyse the circuit to obtain input impedance, voltage gain, current gain & output impedance in the view of small-signal, the biasing arrangement in the circuit is not shown. Small-signal analysis of the current-source-loaded CS amplifier is straightforward and is illustrated in Fig. 1(b). Here, along with the equivalent circuit model, we show the transistor with its r 0 extracted and displayed separately and with the analysis performed directly on the circuit. From Fig. 1(b) we see that for this CS amplifier, 1
R in =, A VO = -g m r o (since v i = v gs and v o = - g m r o v gs ) and R 0 =r 0... (1) We note that A vo is the maximum voltage gain available from a common-source amplifier, namely the intrinsic gain of the MOSFET, A 0 = g m r o Common-Source Amplifier implemented using CMOS A CMOS circuit implementation of the common-source amplifier is shown in Fig. 2(a) This circuit is based on that shown in Fig. 1(a) with the load current-source I implemented using transistor Q 2. This is the output transistor of the current mirror formed by Q 2 and Q 3 and fed with the bias current I REF. We shall assume that Q 2 and Q 3 are matched; therefore the Fig.2 The CMOS common-source amplifier : (a) circuit: (b) i-v characteristic of the active-loadq 2 ; (c) graphical construction to determine the transfer characteristic: and (d) transfer characteristic. i-v characteristic of the load device will be as shown in Fig. 2(b). This is simply the i D -v SD characteristic curve of the p-channel transistor Q 2 for a constant source-gate voltage V SG. The value of V SG is set by passing the reference bias current I REF through Q 3. Observe 2
that, Q 2 behaves as a current source when it operates in saturation, which in turn is obtained when v = v SD exceeds (V SG - V tp ), which is the magnitude of the overdrive voltage at which Q 2 and Q 3 are operating. Q 2 exhibits a finite incremental resistance r o2, when it is in saturation and is given by,.. (2) Where V A2 is the Early voltage of Q 2. In other words, the current-source load is not ideal but has a finite output resistance equal to the transistor r 0. The circuit s transfer characteristic, v o versus v i, needs to be observed before analyzing the circuit to calculate voltage gain. This can be obtained using the graphical construction shown in Fig. 2 (c). Here we have sketched the i D -v DS characteristics of the amplifying transistor Q 1 and superimposed the load curve on them. The latter is simply the i-v curve in Fig. 2(b) "flipped around" and shifted V DD volts along the horizontal axis. Now, since v GS1 =v i, each of the i D -v DS curves corresponds to a particular value of v i. The intersection of each particular curve with the load curve gives the corresponding value of V DS1, which is equal to v 0. Thus, in this way, we can obtain the v 0 -v i characteristic, point by point. The resulting transfer characteristic is sketched in Fig. 2(d). As indicated, it has four distinct segments, labeled I, II, III, and IV, each of which is obtained for one of the four combinations of the modes of operation of Q 1 and Q 2, which are also indicated in the diagram. Note also that we have labeled two important break points on the transfer characteristic (A and B) in correspondence with the intersection points (A and B) in Fig. 2 (c). For amplifier operation segment III is the one of interest. Observe that in region III the transfer curve is almost linear and is very steep, indicating large voltage gain. In region III both the amplifying transistor Q 1 and the load transistor Q 2 are operating in saturation. The end points of region III are A and B: At A, defined by v 0 = V DD - V 0V2, Q2 enters the triode region, and at B, defined by v 0 = v i V tn, Q 1 enters the triode region. When the amplifier is biased at a point in region III, the small-signal voltage gain can be determined by replacing Q 1 with its small-signal model and Q 2 with its output resistances r o2. The output resistance of Q 2 constitutes the load resistance of Q 1. The voltage gain A v can be found from Eq. below (3) to obtain 3
(4) indicating that, as expected, A v will be lower in magnitude than the intrinsic gain of Q 1, g m1 r o1. For the case r o2 = r ol, A v will be g m1 r ol /2. The CMOS common-source amplifier can be designed to provide voltage gains ranging from 15 to 100. It offers a very high input resistance; however, its output resistance is also high. Two final comments need to be made before leaving the common-source amplifier: 1. The circuit is not affected by the body effect since the source terminals of both Q 1 and Q 2 are at signal ground. 2. The circuit is usually part of a larger amplifier circuit and negative feedback is utilized to ensure that the circuit in fact operates in region III of the amplifier transfer characteristic. EXAMPLE Consider the CMOS common-source amplifier in Fig. 2 (a) for the case V DD = 3 V, V tn = V tp = 0.6 V, µ n C 0X = 200 µa / V 2, and µ p C 0x = 65 µa / V 2. For all transistors, L = 0.4 µm and W=4 µm. Also, V An = 20 V, V Ap = 10 V, and I REF = 100 µa. Find the small-signal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic that is, points A and B in the transfer characteristic. Solution 4
The extremities of the amplifier region of the transfer characteristic(region III) are found as follows (Fig. 2): First, we determine V SG of Q 2 and Q 3 corresponding to I D = I REF = 100 µa Where V 0V3 i s the magnitude of the overdrive voltage at which Q 3 and Q 2 are operating, and we have used the fact that, for Q 3, V SD = V SG. Thus, and V SG = 0.6 + 0.53 = 1.13 V V OA = V DD V ov2 = 2.47 V Noting that in region III Q 1, and Q 2 are in saturation and obviously conduct equal currents, When v in = V IB, v o = V OB, V DSn =0 and V DSp = V OA -V OB 5
V OA V OB = V OA (V GSn V tn ) =2.47-V IB +0.6 =3.07 - V IB 6
The width of the amplifier region is therefore Δv i = V IB -V IA = 0.05 V and the corresponding output range is ΔV 0 =V OB - V OA = -2.14 V Thus the "large-signal" voltage gain is which is very close to the small-signal value of -42, indicating that segment III of the transfer characteristic is quite linear. 7
The Common-Emitter Circuit FIGURE 3(a) Active-loaded common-emitter amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit and using the hybrid-π model explicitly. The active-loaded common-emitter amplifier, in Fig. 3(a), is similar to the active-loaded common-source circuit studied above. Here also, the bias-stabilizing circuit is not shown. Small-signal analysis is similar to that for the MOS case and is shown in Fig. 3(b). The results are R i = r π A vo = -g m r o (5) R o = r o which except for the rather low input resistance r π are similar to the MOSFET case. Recall, however, from the comparison, that the intrinsic gain g m r 0 of the BJT is much higher than that for the MOSFET. This advantage, however, is counterbalanced by the practically infinite input resistance of the common-source amplifier. HIGH-FREQUENCY RESPONSE OF THE CS AND CE AMPLIFIERS Consider the high-frequency response of the active-loaded common-source and commonemitter amplifiers. Figure4 shows the high-frequency equivalent circuit of the commonsource amplifier. This equivalent circuit applies equally well to the CE amplifier with C gs being replaced by C π, C gd by C µ, and V gs by V π. 8
Figure4: High-frequency equivalent-circuit model of the common-source amplifier. For the common-emitter amplifier, the values of V sig and R sig are modified to include the effects of r π and r x ; C gs is replaced by C π,v gs by V π and C gd by C µ. The input-signal source is represented by V sig and R sig. In some cases, V sig and R sig would be modified values of the signal-source voltage and internal resistance, taking into account other resistive components such as a bias resistor R G or R B, the BJT resistances r x and r π, etc. The load resistance R L represents the combination of an actual load resistance (if connected) and the output resistance of the current-source load. To avoid loss of gain; R L is usually of the same order as r 0. We combine R L with r 0, and denote their parallel equivalent R L. The load capacitance C L represents the total capacitance between drain (or collector) and ground; it includes the drain-to-body capacitance C db (collector-tosubstrate capacitance), the input capacitance of a succeeding amplifier stage, and in some cases, a deliberately introduced capacitance. In IC MOS amplifiers, C L can be relatively a very high value. Analysis Using Miller's Theorem When R sig is relatively large and C L is relatively small. Miller's theorem can be used to obtain a quick but approximate estimate of the 3-dB frequency f H. Figure5 shows the approximate equivalent circuit obtained for the CS case, from which we see that the amplifier has a dominant pole formed by R sig and C in. 9
g m v gs FIGURE 5 Approximate equivalent circuit obtained by applying Miller's theorem while neglecting C L and the load current component supplied by C gd. This model works reasonably well when R sig is large and amplifier high-frequency response is dominated by the pole formed by R sig and C in. (6) (7) (8) (9) Analysis Using Open-Circuit Time Constants The method of open-circuit time constants can be applied to the CS equivalent circuit of Fig. 4, as illustrated in Fig. 6 from which we see that the resistance seen by C gs, R gs = R sig and that seen by C L is R L. The resistance R gd seen by C gd can be found by analyzing the circuit in Fig. 6(b) with the result that R gd = R sig (1+g m R L ) + R L (10) 10
Fig. 6 The open-circuit time constant method to the CS equivalent circuit of Fig.4 Thus the effective time-constant b, or τ H can be found as (11) and the 3-dB frequency f H is (12) In those cases in which C L is relatively high, this approach results in a better estimate of f H than that obtained using the Miller equivalence (because in the latter case we completely neglected C L ). Exact Analysis The approximate analysis presented above provides insight about the limit in highfrequency gain of the CS (and CE) amplifiers. Nevertheless, given that the circuit of Fig. 4 is relatively simple, it will be good if we perform an exact analysis. This is illustrated in Fig.7. 11
A node equation at the drain provides (13) which can be manipulated to the form (14) A loop equation at the input yields V sig = I i R sig + V gs (15) in which we can substitute for I i from a node equation at G, I i = sc gs V gs + sc gd (V gs -V 0 ) (16) FIGURE 7 Analysis of the CS high-frequency equivalent circuit to obtain V sig = V gs [1+s(C gs +C gd )R sig ] - sc gd R sig V o (17) We can now substitute in this equation for V gs from Eq. (14) to obtain an equation in V 0 and V sig that can be arranged to yield the amplifier gain as (18) 12
The transfer function in Eq. 18 indicates that the amplifier has a second-order denominator, and hence two poles. Now, since the numerator is of the first order, it follows that one of the two transmission zeros is at infinite frequency. This is readily verifiable by noting that as s approaches, (V 0 / V sig ) approaches zero. The second zero is at (19) That is, it is on the positive real axis of the s-plane and has a frequency w z, ω z = g m /C gd (19a) Since g m is usually large and C gd is usually small, f z is normally a very high frequency and thus has negligible effect on the value of f H. It is useful at this point to show a simple method for finding the value of s at which V 0 = 0 that is, s z. Figure 8 shows the circuit at S = s z. By definition, V 0 = 0 and a node equation at D yields S z C sd V gs = g m V gs (20) we can divide both sides by V gs to obtain (21) We should note that in Eq. (18), as s goes toward zero, V 0 /V sig approaches the dc gain (-g m R L ) as should be the case. In the denominator polynomial, we observe that the coefficient of the s term is equal to the effective time-constant τ H obtained using the open-circuit time-constants method as given by Eq. (11). Fig8: The CS Ckt, at s=s z the output voltage V o =0. 13
Denoting the frequencies of the two poles ω p1 and ω p2, we can express the denominator polynomial D(s) as (22) If ω P2 >ω P1 that is, the pole at ω PI is dominant we can approximate D(s) as (23) Equating the coefficients of the s term in denominator polynomial of Eq. (18) to that of the S term in Eq. (23) gives (24) where the approximation is that involved in Eq. (18). Note that the expression in Eq. (24) is identical to the result obtained using open-circuit time constants and a little different from the result obtained using the Miller equivalence, the difference being the term (C L + C gd )R L related to the capacitance at the output, which was ignored in the original (simple) Miller derivation. Equating the coefficients of s 2 in Eqs. (18) and (23), and using Eq. (24), frequency of the second pole: (25) EXAMPLE A CMOS common-source amplifier of the type shown in Fig. 2(a) has W/L = 7.2 µm/0.36 µm for all transistors, µ n C 0x = 387 µa/v 2, n p C ox = 86 µa/ V 2, I REF = 100 µa, V' An = 5 V/µm and V' Ap = 6 V/µm. For Q 1, C gs = 20 ff, C gd = 5 ff, C L = 25 ff. and R sig = 10k Assume that C L includes all the capacitances introduced by Q 2 at the output node. Find f H using both the Miller equivalence and the open-circuit time constants. Also, determine the exact values of f P1, f P2, and f z and hence provide another estimate for f H. Solution 14
Thus, which results in V ov = 0.16 V Using the Miller equivalence: Using the open-circuit time-constants method: Thus 15
which can be summed to obtain τ H as from which we find the 3-dB frequency f H, We note that this is about 25% lower than the estimate obtained using the Miller equivalence. The discrepancy is mostly a result of neglecting C L in the Miller approach. Note that C L here has a substantial magnitude and that its contribution to τ H is significant (246 ps of the total 1160 ps, or 21%). To determine the exact locations of zero and the poles, we use the transfer function in eq(18). The frequency of the zero is given by eq(19a) : f z = g m /(2πC gd ) = 40 GHz. The frequencies w p1 and w p2 are found as the roots of the equation obtained by equating the denominator polynomial of eq(18) to zero: 1 + 1.16 X 10-9 s + 0.0712 X 10-18 s 2 =0 and, the result is f p1 = 145.3 MHz And f p2 = 2.45GHz. since f Z, f p2 >> f p1, a good estimate for f H f p1 =145.3MHz. CE amplifier In the case of CE amplifier, the above formulae are straightaway adapted. 16
Fig.9: (a) High frequency equivalent circuit of the common-emitter amplifier. (b) equivalent circuit obtained after the Thevenin theorem is employed to simplify the resistive circuit at the input. Fig.9(a) represent the high frequency equivalent circuit of the common-emitter amplifier. The V sig and R sig are modified to take into account the effect of r x and r π. V sig = V sig r π /(R sig + r x +r π ).. (26) R sig = r π // (R sig +r x ). The DC gain is given by A M = -(r π )(g m R L ) /(R sig + r x +r π )... (27) Using the Miller s theorem we get, C in = C π + C μ (1+ g m R L )... (28) The 3-dB frequency, f H can be estimated from f H = 1 /(2πC in R sig )... (29) Using the method of open-circuit time constants yields τ H = C π R π + C μ R μ + C L R L = C π R sig + C μ [(1+g m R L ) R sig + R L ] + C L R L.. (30) f H can be estimated as f H. Exact analysis yields the following zero frequency: f z = g m /(2πC μ )... (31) Assuming that a dominant pole exists, 17
.. (32).. (33) The Situation When R sig is Low In the applications where the CS amplifier is fed with a low-resistance signal source, the high-frequency gain will no longer be limited by the source resistance and the input capacitance. The high-frequency limitation happens at the amplifier output, as shown below: Figure 10(a) shows the high-frequency equivalent circuit of the common-source amplifier in when R sig is zero. The voltage transfer function V o /V Sig = V o /V gs can be found by setting R sig = 0 in Eq. (18). The result is.. (34) Thus, while the dc gain and the frequency of the zero do not change, the high-frequency response is now determined by a pole formed by C L + C gd together with R' L. Thus the 3- db frequency is now given by.. (35) To see how this pole is formed, refer to Fig. 10(b), which shows the equivalent circuit with the input signal source set to zero. Observe that the circuit reduces to a capacitance (C L + C gd ) in parallel with a resistance R' L. As we have seen above, the transfer-function zero is usually at a very high frequency and thus does not play a significant role in shaping the high-frequency response. The gain of the CS amplifier will therefore fall off at a rate of-6 db/octave (-20 db/decade) and reaches 18
FIGURE 10 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance, (b) The circuit with V sig reduced to zero, (c) Bode plot for the gain of the circuit in (a). unity (0 db) at a frequency f t which is equal to the gain-bandwidth product, Thus,.. (36) Figure 10(c) shows a sketch of the high-frequency gain of the CS amplifier. Example: Consider the CS amplifier specified when fed with a signal source having a negligible resistance (i.e. R sig = 0). Find A M, f 3dB, f t, and f z. If the amplifying transistor is to be operated at twice the original overdrive voltage while Wand L remain unchanged, what value of I REF is needed? What are the new values of A M, f 3dB, f t and f z? Solution A M = g m R L = -12.3 V/V 19
The 3-dB frequency can be found using Eq. (35) and the unity-gain frequency, which is equal to the gain-bandwidth product, can be determined as f t = A M f H = 12.3 x 540 = 6.6 GHz The frequency of the zero is Now, to increase V ov from 0.16 V to 0.32 V, I D must be quadrupled by changing I REF to I REF = 400 µa The new values of g m, r ol, r o2, and R L can be found as follows: Thus the new value of A M becomes A M = -g m R' L = - 2.5 x 2.45 = -6.15 V/V That of f H becomes 20
and the unity-gain frequency (i.e., the gain-bandwidth product) becomes f t = 6.15 x 2.16 = 13.3 GHz We note that doubling V ov results in reducing the dc gain by a factor of 2 and increasing the bandwidth by a factor of 4. Thus, the gain-bandwidth product is doubled. THE COMMON-GATE AND COMMON-BASE AMPLIFIERS WITH ACTIVE LOADS The Common-Gate Amplifier Figure 11(a) represents the basic IC MOS common-gate amplifier. The transistor has its gate grounded and its drain connected to an active load, given as an ideal constant-current source I. The input signal source v sig with a generator resistance R s is connected to the source terminal. The MOSFET source is not connected to the substrate, hence the substrate terminal, B, is shown explicitly and indicate that it is connected to the lowest voltage in the circuit, i.e., to ground in this case. We may observe that except for showing the current-source I, which determines the dc bias current I D of the transistor, no other bias detail is shown. How the DC voltage V GS will be established and how V DS is determined are not of concern to us here. However, it should be known that bias stability is assured through the application of negative feedback to the larger circuit of which the CG amplifier is a part. In this case, we assume that the MOSFET is operating in the saturation region and concentrate exclusively on its small-signal operation. The Body Effect: Since the substrate (i.e. body) is not connected to the source, the body effect plays a role in the operation of the common-gate amplifier. However, it turns out, that considering the body effect in the analysis of the CG circuit is very simple. 21
FIGURE 11 (a) Active-loaded common-gate amplifier, (b) MOSFET equivalent circuit for the CG case in wn.ch the body and gate terminals are connected to ground, (c) Small-signal analysis performed directly on the circuit diagram with the T model of (b) used implicitly, (d) Operation with the output open-circuited. Recall that the body terminal acts, in effect, as a second gate for the MOSFET. Thus, just as a signal voltage v gs between the gate and the source gives rise to a drain current signal g m v gs, a signal voltage v bs between the body and the source gives rise to a drain current 22
signal g mb v bs. Thus the drain signal current becomes (g m v gs + g mb v bs ) where the body transconductance g mb is a small fraction χ of g m ; g mb = χg m and χ = 0.1 to 0.2. Since in the CG circuit of Fig. 11(a) both the gate and the body terminals are connected to ground, v bs = v gs, and the signal current in the drain becomes (g m + g mb )v gs. It follows that the body effect in the common-gate circuit can be fully accounted for by simply replacing g m of the MOSFET by (g m + g mb ). As an example, Fig. 11(b) shows the MOSFET T-model modified in this way. Small-Signal Analysis The small-signal analysis of the CG amplifier can be performed either on an equivalent circuit obtained by replacing the MOSFET with its T model of Fig. 11(b) or directly on the circuit diagram with the model used implicitly. The latter approach is opted in order to gain greater insight into circuit operation. Figure 11(c) shows the CG circuit prepared for small-signal analysis. Here we observe "extracted" r 0 of the MOSFET and shown it separately from the device. The resistance 1 /(g m + g mb ), which appears in effect between gate and source looking into the source is also indicated. Note that a resistance R L is shown at the output; it is assumed to include the output resistance of the current-source load I as well as any load resistance if connected. The circuit of Fig. 11(c) is analysed to determine the various parameters that characterize the CG amplifier. The CG amplifier is not a unilateral circuit; the resistance r Q connects the output node to the input node. As a result we should expect the amplifier input resistance R in to depend on R L and the output resistance R out to depend on R s. Input Resistance To determine the input resistance R in, we must find a way to express i i in terms of v i. Inspection of the circuit in Fig. 11(c) reveals a key observation. The input current i i splits at the source node into two components: the source current i = (g m + g mb )v i and the current through r 0, i ro These two components combine at the drain to constitute the current i o supplied to R L, ; thus i o = i i, and v o = i 0 R L = i i R L. Now we can write at the source node i i =(g m + g mb )v i + i r0. (37) and express i ro as. (38) Equations (37) and (38) can be combined to obtain 23
from which the input resistance R in can be found as. (39) Observe that for r 0 =, R in reduces to 1 /(g m + g mb ) which is indeed the input resistance with r 0 neglected. When r 0 is taken into account, this value of input resistance is obtained approximately only for R L = 0. For the usual case of R L = r o, R in = 2/(g m + g mb ). Interestingly, for large values of R L approaching infinity, R in =. Operation with R L = Figure 11(d) shows the CG amplifier with R L removed; that is, R L = and the amplifier is operating with the output open-circuited. We note that since i o =0, i i, must also be zero; the current i in the source terminal, i = (g m + g mb )v i, simply flows via the drain through r o and back to the source node. It follows that the input resistance with no load, R i, is infinite: R i = We can also use the circuit in Fig. 11(d) to determine the open-circuit voltage gain A vo between the input (source) and output (drain) terminals as follows: v o = ir o + v i = (g m + g mb ) v i r o + v i. (40) Thus, A vo = 1 + (g m + g mb) r o. (41) This is a very important quantity that appears in almost all formulas that characterize the CG amplifier. We observe that A vo differs from the intrinsic gain of the MOSFET in two minor respects: First, there is an additional term of unity, and second, g mb is added to g m. Typically A vo is 10% to 20% larger than A 0. We should also note that the gain of the CG circuit is positive. That is, unlike the CS amplifier, the CG amplifier is non-inverting. From Eqs. (39) and (41), we can express the input resistance of the CG amplifier in the form as shown:. (42) 24
That is, the CG circuit divides the total resistance (r o + R L ) by the open-circuit voltage gain, which is approximately equal to the intrinsic gain of the MOSFET. Furthermore, since A vo = (g m + g mb )r 0 A 0, the expression for R in can be simplified to. (43) This expression says that taking r 0 into account adds a component (R L /A 0 ) to the input resistance. This additional component becomes significant only when R L is large. Another interesting result that follows directly from the fact that i i = 0 in the circuit of Fig. 11(d): The voltage drop across R s will be zero. Thus V i = V sig, and the open-circuit overall voltage gain, v o /v sig will be equal to A vo, G vo = A vo = 1+(g m + g mb )r 0. (44) Voltage Gain The voltage gains A v and G v of the loaded CG amplifier of Fig. 11(c) can be obtained in a number of ways. The most direct approach is to make use, once more, of the fact that i o = i i and express v 0 as v 0 =i 0 R L =i i R L. (45) The voltage v i, can be expressed in terms of i i as v i = i i R in. (46) Dividing Eq. (45) by Eq. (46) yields, for the voltage gain, A v. (47) Substituting for R in from Eq. (42) provides. (48) In a similar way, we can derive an expression for the overall voltage gain, G v = v o /vs ig v o = i o R L = i i R L v sig = i i (R s + R in ). (49) 25
Thus,. (50) in which we can substitute for R in from Eq. (42) to obtain. (51) Recalling that G vo = A vo, we can express G v as. (52) Output Resistance To complete our characterization of the CG amplifier, we find its output resistance. We recall that there are two different output resistances: R o, which is the output resistance when v i is set to zero, and R out which is the output resistance when v sig is set to zero. Both are illustrated in Fig. 12. Obviously R 0 can be obtained from the expression for R out by setting R s = 0. It is important to be clear on the application of R o and of R out. Since R 0 is the output resistance when the amplifier is fed with an ideal source v i it follows that it is the applicable output resistance for determining A v from A vo,. (53) On the other hand, R out is the output resistance when the amplifier is fed with v sig and its resistance R s ; so it is the applicable output resistance for determining G v from G vo,. (54) Returning to the circuit in Fig. 12(a), we see by inspection that R o = r o. (55) A verification of this result is achieved by substituting R o = r o in Eq. (53) and then observing that the resulting expression for A v is identical to that in Eq. (48), which we obtained from circuit analysis. 26
An expression for R out can be derived using the circuit in Fig. 12 (b) where a test voltage V x is applied at the output. Our aim is to find the current i x drawn from v x. Towards the FIGURE 12 (a) The output resistance R o is found by setting v i = 0. (b) The output resistance R out is obtained by setting v sig =0. Other end we note that the current through R s is equal to i x ; thus we can express the voltage v at the MOSFET source as v = i x R s. (56) Utilizing the analysis indicated on the circuit diagram in Fig. 12(b), we can write for v x v x = [i x + (g m + g mb )v]r o + v. (57) Equations (56) and (57) can be combined to eliminate v and obtain v x in terms of i x and hence R out = v x /i x. R out = r o +[1+(g m + g mb )r o ]R s. (58) We recognize the term multiplying R s as the open-circuit voltage gain A vo ; thus R out can be expressed in an alternative, more compact form as R out = r o + A vo R s. (59) 27
A verification of the formula for R out in Eq. (59) can be obtained by substituting it in Eq. (54). The result will be seen to be identical to the gain expression in Eq. (52), which we derive by circuit analysis. The expressions for R out in Eqs. (58) and (59) are very useful results that we will employ frequently further. These formulas give the output resistance not only of the CG amplifier but also of a CS amplifier with a resistance R s in the emitter. A first interpretation, immediately available from Eq. (59), is that the CG transistor increases the output resistance by adding to r 0 a component A vo R s. In many cases the latter component would dominate, and one can think of the CG MOSFET as multiplying the resistance R s in its source by A vo, which is approximately equal to g m r 0. Note that this action is the complement of what we saw earlier in regard to R in where the MOSFET acts to divide R L by A vo. This impedance transformation action of the CG MOSFET is illustrated in Fig. 13 and is a key to number of applications of the CG circuit. One such application involves the use of the CG amplifier as a current buffer. Fig. 14 shows an equivalent circuit that is suitable for such an application. It can be shown that the overall short-circuit current gain G is is given by. (60) Wkt, v o /v sig = G v = G vo R L / (R L +r o +A vo R s ) =>i o R L / i sig R s = G vo R L / (R L +r o +A vo R s ), => i o / i sig R s = G vo / (R L +r o +A vo R s ) => i o / i sig = G vo R s / (R L +r o +A vo R s ),When R L =0, => i o / i sig = G is = G vo R s / (r o +A vo R s ),[short circuit current gain] G vo R s / R out A vo R s / (r o +A vo R s ) 1 The near-unity current gain together with the low input resistance and high output resistance are all characteristics of a good current buffer.yet another interpretation of the formula for R out can be obtained by expressing Eq. (58) in the form R out = R s + [1 + (g m + g mb ) R s ] r o. (61) 28
FIGURE 13 The impedance transformation property of the CG configuration. FIGURE 14 Equivalent circuit of the CG amplifier illustrating its application as a current buffer, R in and R out are given in Fig. 13, and G is = A vo (R S /R out ) In this expression the second term often dominates, enabling the following approximation. (62) Thus placing a resistance R s in the source lead, results in multiplying the transistor output resistance r o by a factor (1+g m R s ). 29
High-Frequency Response Figure 15(a) shows the CG amplifier with the MOSFET internal capacitances C gs and C gd indicated. For generality, a capacitance C L is included at the output node to represent the input capacitance of a succeeding amplifier stage. Capacitance C L also includes the MOSFET capacitance C db. Note the C L appears in effect in parallel with C gd. Therefore, in the following discussion we will lump the two capacitances together. It is important to note that each of the three capacitances in the circuit of Fig. 15(a) has a grounded node. Hence none of the capacitances undergoes the Miller-multiplication effect seen in the CS stage. It follows that the CG circuit can be designed to have a much wider bandwidth than that of the CS circuit, especially when the resistance of the signal generator is large. FIGURE 15 (a) The common-gate amplifier with the transistor internal capacitances shown. A capacitance C L is also included, (b) Equivalent circuit for the case in which r o is neglected. Analysis of the circuit in Fig. 15(a) is greatly simplified if r o can be neglected. In such a case the input side is isolated from the output side, and the high-frequency equivalent 30
circuit takes the form shown in Fig. 15(b). We immediately observe that there are two poles: one at the input side with a frequency f P1. (63) and the other at the output side with a frequency f P2.. (64) The relative locations of the two poles will depend on the specific situation. However, f P2 is usually lower than f P1 ; thus f P2 can be dominant. The important point to note is that both f Pl and f p2 are usually much higher than the frequency of the dominant input pole in the CS stage. In situations when r o has to be taken into account (because R s and R L are large), the method of open-circuit time constants can be employed to obtain an estimate for the 3-dB frequency f H,Fig.16 shows the circuits for determining the resistances R gs and R gd seen by C gs and (C gd + C L ), respectively. By inspection we obtain. (65). (66). (67) 31
FIGURE 16 Circuits for determining R gs, and R gd EXAMPLE : Consider a common-gate amplifier specified as follows: W/L = 7.2 µm/0.36 µm, µ n C ox = 387µA/V 2, r o = 18 k, I D = 100 µa, g m = 1.25 ma/v, χ = 0.2, R s = 10 k, R L = 100 k, C gs = 20 ff, C gd = 5 ff, and C L = 0. Find A vo, R in, R out,. G v, G is, G i and f H. Solution 32
It can be noticed that this circuit performs well as a current buffer, raising the resistance level from R in = 4 k to R out = 300 k and having an overall short-circuit current gain of 0.94 A/A. Because of the high output resistance, the amplifier bandwidth is determined mainly by the capacitance at the output node. So, additional load capacitance can lower the bandwidth significantly. Exercise: a) For the CG amplifier considered in Example above, find the value of f H when a capacitance C L = 5 ff is connected at the output. Ans. 196 MHz b) Repeat the problem in above Example for the case R s = 1 k and R L = 10 k. Ans. A vo = 28 V/V; R in = 1 k ; R out = 46 k ; G v = 5 V/V; G is = 0.61 A/A; G i = 0.5 A/A; f H = 2.61 GHz The Common-Base Amplifier Analysis of the common-base amplifier resembles that of the common-gate circuit that we analysed previously, with one major difference: The BJT has a finite β, and its base conducts signal current, which gives rise to the resistance r π between base and emitter, looking into the base. Figure 17(a) shows the basic circuit for the active-loaded commonbase amplifier without any details of biasing. Note that resistance R L represents the combination FIGURE 17 (a) Active-loaded common-base amplifier, (b) Small-signal analysis performed directly on the circuit diagram with the BJT T model (c) Small-signal analysis with the output open-circuited. Of load resistance, if any, and the output resistance of the current source that realizes the active load I. 33
Figure 17(b) shows the small-signal analysis performed directly on the circuit with the T model of the BJT used implicitly. The analysis is very similar to that for the MOS case except that, as a result of the finite base current, v i /r π, the current i o is related to i i by i o = i i -v i /r π. (68) It can be shown that, neglecting r x, the input resistance at the emitter, R in is given by. (69) Wkt, i i = v i /r e +i ro (from the fig. above) i i = v i /r e +(v i -v o )/r o i i = v i /r e +v i /r o i o R L /r o i i =v i /r e +v i /r o (R L /r o )(i i v i /r π ) Remember: r π =(1+β)r e We observe that setting β = reduces this expression to that of the MOS case (Eq.39) except that here g mb = 0. Note that, for β =, α = 1, and r e = α/g m = 1 /g m. With a slight approximation, the expression in Eq. (69) can be written as. (70) Note that setting r o = yields R in = r e. Also, for R L = 0, R in = r e. The value of R in increases as R L is raised, reaching a maximum of (β + 1 )r e = r π for R L =, that is, with the amplifier operating open-circuited (see Fig. 17c). For R L /(β + 1) < r 0, Eq. (70) can be approximated as. (71) where A 0 is the intrinsic gain g m r o. This equation is very similar to Eq. (43) in the MOSFET case. The open-circuit voltage gain and input resistance can be easily found from the circuit in Fig. 17(c) as A vo = 1 + g m r 0 = l + A o. (72) which is identical to Eq. (41) for the MOSFET except for the absence of g mb. The input resistance with no load, R i, is R i = r π. (73) as we have already found out from Eq. (70). 34
As in the MOSFET case, the output resistance R o is given by R o = r o. (74) The output resistance including the source resistance R e can be found by analysis of the circuit in Fig. 18 to be wkt, i x = v/r e v=i x R e Where R' e = R e II r π R out = r o + (1+ g m r o ) R' e. (75) v x = v + (i x +g m v)r o v x = v(1 +g m r o ) + i x r o v x = i x R e (1 +g m r o ) + i x r o R out =v x /i x = R e (1 +g m r o ) + r o Note that the formula in Eq. (75) is very similar to that for the MOS case, namely Eq. (58). However, there are two differences: First, g mb is missing, and second, R' e =R e II r π FIGURE 18 Analysis of the CB circuit to determine R out. Observe that the current i x that enters the transistor must equal the sum of the two currents v/r π and v/r e that leave the transistor, that is, i x = v/r π + v/r e. Replaces R s. The reason r π appears in the BJT formula is the finite β of the BJT. The expression in Eq. (75) can also be written in terms of the open-circuit voltage gain A vo as R out = r o + A vo R' e. (76) 35
which is the BJT counterpart of the MOS expression in Eq. (59). Another useful form for R out can be obtained from (75), R out = R' e +(1+g m R' e )r 0. (77) which is the BJT counterpart of the MOS expression in Eq. (61). In Eq. (77) the second term is much larger than the first, resulting in the approximate expression R out (1 + g m R' e )r 0. (78) which corresponds to Eq. (62) for the MOS case. Equation (78) clearly shows that the inclusion of an emitter resistance R e increases the CB output resistance by a factor (1 + g m R' e ). Thus, as R e is increased from 0 to, the output resistance increases from r o to (1 +g m r π )r 0 = (1 + β)r 0 = βr 0. This upper limit on the value of R out dictated by the finite β of the BJT, has no counterpart in the MOS case and will have important implications for circuit design. We note that for R e < r π, Eq. (78) can be approximated by R out = (1 + g m R e )r o. (79) A useful summary of the formulas for R in and R out is provided in Fig. 19. The results above can be used to obtain the overall voltage gain G v as. (80). (81) 36
FIGURE 19 Input and output resistances of the CB amplifier. The high-frequency response of the common-base circuit can be evaluated in a manner similar to that used for the MOSFET. EXERCISE Consider the CB amplifier of Fig. 17(a) for the case I = 1 ma, β = 100, V A = 100 V, R L = 1 M and R e = 1 k. Find R in, A vo, R o, A v, R out and G v. Also find v o,if v sig is a 5-mV peak sine wave. Ans. 250 ; 4001 V/V; 100 k ; 3637 V/V; 2.97 M, 722 V/V; 3.61 V peak Note: The common-gate and common-base circuits have open-circuit voltage gains A vo almost equal to those of the common-source and common-emitter circuits. Their input resistance, however, is much smaller and their output resistance much larger than the corresponding values for the CS and CE amplifiers. These two properties, though not usually desirable in voltage amplifiers, make the CG and CB circuits suitable as current buffers. The absence of the Miller effect makes the high-frequency response of the CG and CB circuits far superior to that of the CS and CE amplifiers. 37
The most significant application of the CG and CB circuits is in a configuration known as the cascode amplifier, which we shall study next. THE CASCODE AMPLIFIER A common-gate (common-base) amplifier stage in cascade with a common source (common-emitter) amplifier stage, results in a very useful and versatile amplifier circuit known as the cascode configuration and has been in use in a wide variety of technologies for over three quarters of century. The basic idea behind the cascode amplifier is to combine the high input resistance and large transconductance achieved in a common-source (common-emitter) amplifier with the current-buffering property and the superior high-frequency response of the commongate (common-base) circuit. The cascode amplifier can be designed to obtain a wider bandwidth but equal dc gain as compared to the common-source (common-emitter) amplifier. Alternatively, it can be designed to increase the dc gain while leaving the gainbandwidth product unchanged. In many applications the cascade amplifier is thought of and treated as a single-stage amplifier though it is formed by cascading two amplifier stages. The MOS Cascode Figure 20(a) shows the MOS cascode amplifier. Here transistor Q 1 is connected in the common-source configuration and provides its output to the input terminal (i.e., source) of transistor Q 2. Transistor Q 2 has a constant dc voltage, V B1AS, applied to its gate. Thus the signal voltage at the gate of Q 2 is zero, and Q 2 is operating as a CG amplifier with a constant-current load, I. Obviously both Q 1 and Q 2 will be operating at DC drain currents equal to I. As in previous cases, feedback in the overall circuit that incorporates the cascode amplifier establishes an appropriate dc voltage at the gate of Q 1 so that its drain current is equal to I. Also, the value of V BIAS has to be chosen so that both Q 1 and Q 2 operate in the saturation region at all times. Small-Signal Analysis : In response to the input signal voltage v i the common-source transistor Q 1 conducts a current signal g m1 v i, in its drain terminal and feeds it to the source terminal of the common-gate transistor Q 2, called the cascode transistor. Transistor Q 2 passes the signal current g m1 v i on to its drain, where it is supplied to a load resistance R L (not shown in fig. 20) at a very high output resistance, R out. The cascode transistor Q 2 acts in effect as a buffer, presenting a low input resistance to the drain of Q 1 and providing a high resistance at the amplifier output. 38
Characteristic parameters: In Fig. 20(b) shows the cascode circuit prepared for smallsignal analysis and with a resistance R L shown at the output. R L is assumed to include the output resistance of current source I as well as an actual load resistance, if any. The diagram also indicates various input and output resistances obtained using the results of the analysis of the CS and CG amplifiers in previous sections. Note in particular that the CS transistor Q 1 provides the cascode amplifier with an infinite input resistance. Also, at the drain of Q 1 looking "downward, see the output resistance of the CS transistor Q 1, r o1. Looking "upward," we see the input resistance of the CG transistor Q 2, (82) (83) (84) FIGURE 20 (a) The MOS cascode amplifier. (b) The circuit prepared for small signal analysis with various input and output resistances indicated. (c) The cascode with the output open-circuited. 39
Figure 20 (b) also indicates that the output resistance of the cascode amplifier, R out, is given by R out = r o2 + A vo2 r o1 (85) This has been obtained using the formula in Eq. (59) and noting that the resistance R s in the source of the CG transistor Q 2 is the output resistance r o1 of Q 1. Substituting for A vo2 from Eq. (83) into Eq.(85) yields. R out = r o2 + [1+(g m2 + g mb2 ) r o2 ] r o1 (86) Approximate value can be written as, R out = (g m2 r o2 ) r o1 = A 0 r o1 (87) Thus the cascode transistor increases the level of output resistance by a factor equal to its intrinsic gain, from r o1 of the CS amplifier to A o r o1. From the cascode amplifier circuit in Fig. 20 (b), it is clear that when a signal source v sig with an internal resistance R sig is connected to the input, the infinite input resistance of the amplifier causes. Thus, v i = v sig G v =A v And the amplifier is unilateral; thus R o = R out The open circuit voltage gain A vo of the cascode amplifier can be easily determined from the circuit in Fig. 20(c), which shows the amplifier operating with the output open circuited. Since R in2 will be infinite, the gain of the CS stage Q 1 will be The signal v o1 will be amplified by the open circuit voltage gain A vo2 of the CG transistor Q 2 to obtain. v o = A vo2 v o1 40
Thus, A vo = -A 01 A vo2 -A 01 A 02 (88) And for the usual case of equal intrinsic gains, A vo becomes, A vo = -A 2 o = - (g m r o ) 2 (89) We conclude that cascading increases the magnitude of the open-circuit voltage gain from A o of the CS amplifier to A o 2. We are now in a position to derive an expression for the short circuit transconductance G m of the cascode amplifier. From the definitions we may write, A vo = -G m R o (90) Substituting for A vo from Eq. (88) and for R o = R out from Eq. (85) gives, for G m, (91) This confirms the value obtained earlier in the qualitative analysis. The operation of the cascode amplifier is now clear: In response to v i the CS transistor provides a drain current g m1 v i, which the CG transistor passes on to R L and, in the process, increases the output resistance by A o. It is the increase in R out to A 0 r o that increases the open-circuit voltage gain to (g m )(A o r 0 ) = A 2 o. Figure 21 provides a useful summary of the operation: Two output equivalent circuits are shown in Fig. 21(a) and (b), and an equivalent circuit for determining the voltage gain of the CS stage Q 1 is presented in Fig. 21(c). The voltage gain A v can be found from either of the two equivalent circuits in Fig. 21(a) and (b). From Fig. 21(a) we may write, (92) We see that if we are to realize the large gain of which the cascode is capable, resistance R L should be large. At the very least, R L should be of the order of A 0 r o. For 41
R L = A 0 r o, A v = -A 2 o/2 (93) The gain of the CS stage is important because its value determines the Miller effect in that stage. From the equivalent circuit in Fig. 21(c), neglecting g mb, (94) Figure 21 (a) & (b) Two equivalent circuits for the output of cascode amplifier. (c) Equivalent circuit for determining the voltage gain of the CS stage. 42
Thus we see that when R L is large and the cascode amplifier is realizing a substantial gain, a good part of the gain is obtained in the CS stage. This is not good news considering the Miller effect, as we shall see shortly. To keep the gain of the CS stage relatively low. R L has to be lowered. For instance, for R L = r o, Eq. (94) indicates that However, in this case the DC gain of the cascode is drastically reduced, as can be seen by substituting R L = r o in Eq. (92), (95) That is, the gain of the cascode becomes equal to that realized in a single CS stage. However, it does not mean that the cascode configuration (in this case) is not useful. Frequency Response of the MOS Cascode Figure 22 shows the cascode amplifier with all transistor internal capacitances indicated. Also included is a capacitance C L at the output node to represent the combination of C db2, the input capacitance of a succeeding amplifier stage (if any), and a load capacitance (if any). C db1 and C gs2 appear in parallel, and we shall combine them in the following analysis. Similarly, C L and C gd2 appear in parallel and will be combined. The easiest and, in fact, quite insightful approach to determining the 3-dB frequency f H is to use the open-circuit time-constants method. Capacitance C gs1 sees a resistance R sig. Capacitance C gd1 sees a resistance R gd1, which can be obtained by adapting the formula in Eq. (10) to give R gd1 = (1 + g m1 R d1 ) R sig + R d1 (96) where R d1, the total resistance at D 1 is given by Eq. (84). 43
FIGURE 22 The cascode circuit with the various transistor capacitances indicated. Capacitance (C db1 + C gs2 ) sees a resistance R d1. Capacitance (C L + C gd2 ) sees a resistance (R L II R out ). With the resistances determined, the effective time constant τ H can be computed as τ H = C gs1 R sig + C gd1 [1 + g m1 R d1 )R sig + R d1 ] + (C db1 + C gs2 ) R d1 + (C L + C gd2 ) (R L II R out ) (97) and the 3-dB frequency f H as To see what limits the high-frequency gain of the MOS cascode amplifier, we rewrite Eq. (97) in the form τ H = R sig [C gs1 + C gd1 (1 + g m1 R d1 )] + R d1 (C gd1 + C db1 + C gs2 ) + (R L II R out ) (C L + C gd2 ) (98) In the case of a large R sig, the first term can dominate, especially if the Miller multiplier (1 +g m1 R d1 ) is large. This in turn happens when the load resistance R L is large (of the order 44
of A 0 r o ), causing R in2 to be large and requiring the first stage, Q 1 to provide a large proportion of the gain. It follows that when R sig is large, to extend the bandwidth we have to lower R L to the order of r 0. This in turn lowers R in2 and hence R dl and renders the Miller effect insignificant. However, the dc gain of the cascode will then be A 0. Thus, while the dc gain will be the same as (or a little higher than) that achieved in a CS amplifier, the bandwidth will be greater. In the case when R sig is small, the Miller effect in Q 1, will not be of concern. A large value of R L (on the order of A 0 r o ) can then be used to realize the large dc gain possible with a cascode amplifier that is, a dc gain on the order of A 0 2. Equation (98) indicates that in this case the third term will usually be dominant. To pursue this point a little further, consider the case R sig = 0, and assume that the middle term is much smaller than the third term. It follows that τ H = (C L + C gd2 ) (R L IIR out ) (99) And the 3 db frequency becomes (100) Which is of the same form as the formula for the CS amplifier with R sig = 0. Here, however, (R L II R out ) is larger by a factor of about A 0 compared to R L in CS amplifier. Thus the f H of the cascode will be lower than that of the CS amplifier by the same factor A 0. Figure 23 shows a sketch of the frequency response of the cascode and of the corresponding common-source amplifier. We observe that in this case cascoding increases the dc gain by a factor A o while keeping the unity-gain frequency unchanged at (101) 45
FIGURE 23 Effect of cascoding on gain and bandwidth in the case R sig = 0. Cascoding can increase the dc gain by the factor A 0 while keeping the unity-gain frequency constant. Note that to achieve the high gain, the load resistance must be increased by the factor A O. This example illustrates the advantages of cascoding by comparing the performance of a cascode amplifier with that of a CS amplifier in two cases: a) The resistance of the signal source is significant, R sig = 10 k. b) R sig is negligibly small. Assume all MOSFETs have W/L of 7.2 µm/0.36 µm and are operating at I D = 100 µa, g m = 1.25 ma/v, χ = 0.2, r 0 = 20 k, C gs = 20 ff, C gd = 5fF,C db = 5 ff, and C L (excluding C db = 5 ff. For case (a), let R L = r 0 = 20 k for both amplifiers. For case (b), let R L = r 0 = 20 46
k for the CS amplifier and R L = R out for the cascode amplifier. For all cases, determine A v, f H and f t. 47
Thus cascoding increases the dc gain from 12.5 to 388 V/V. The unity-gain frequency (i.e., gain-bandwidth product), however, remains nearly constant. The BJT Cascode Figure 24(a) shows the BJT cascode amplifier. The circuit is very similar to the MOS cascode, and the small-signal analysis follows in a similar way, as shown in Fig. 24(b). The various input and output resistances have been shown. Unlike the MOSFET cascode, which has an infinite input resistance, the BJT cascode has an input resistance of r π1 (neglecting r x ). The formula for R in2 is the one we found in the analysis of the commonbase circuit. The output resistance R out =β 2 r o2 found 48
FIGURE 24 (a) The BJT cascode amplifier, (b) The circuit prepared for small-signal analysis with various input and output resistances indicated. Note that r x is neglected, (c) The cascode with the output open-circuited. by substituting R e2 = r ol in Eq. (79) and making the approximation that g m r o > β. Recall that βr o is the largest output resistance that a CB transistor can provide. The open-circuit voltage gain A vo and the no-load input resistance R i can be found from the circuit in Fig. 24(c), in which the output is open-circuited. Observe that R in2 = r π2 which is usually much smaller than r 01. As a result the total resistance between the collector of Q 1 and ground is approximately r π2 ; thus the voltage gain realized in the CE transistor Q 1 is g m1 r π2 = -β. Recalling that the open-circuit voltage gain of a CB amplifier is (l + g m r o ) = A o. We see that voltage gain A vo is A vo = -β A o. (102) Putting all of these results together we obtain for the BJT cascode amplifier the equivalent circuit shown in Fig. 25(a). We note that compared to the common-emitter amplifier, cascoding increases both the open-circuit voltage gain and the output resistance by a factor equal to the transistor β. This should be contrasted with the factor A 0 encountered in the MOS cascode. The equivalent circuit can be easily converted to the transconductance form shown in Fig.25(b). It shows that the short-circuit transconductance G m of the cascode amplifier is equal to the transconductance g m of the BJTs. This should have been expected since Q 1 provides a current g m1 v i to the emitter of the cascode transistor Q 2, which in turn passes the current on (assuming α 2 =1) to its collector and to the load resistance R L. In the process the cascode transistor raises the resistance level from r o at the collector of Q 1 to βr 0 at the collector of Q 2. This is the bynow-familiar current-buffering action of the common-base transistor. 49
The voltage gain of the CE transistor Q 1 can be determined from the equivalent circuit in fig-25(c). The resistance between the collector of Q 1 and ground is the parallel equivalent FIGURE : 25 (a) Equivalent circuit for the cascode amplifer in terms of the open circuit voltage gain A vo = - βa o. (b) Equivalent circuit in terms of the overall short circuit transconductance G m = g m. (c) Equivalent circuit for determining the gain of the CE stage Q 1. 50
FIGURE 26: Determining the frequency response of the BJT cascode amplifier. Note that in addition to the BJT capacitances C π and C µ the capacitance between the collector and the substrate C cs for each transistor are also included. of the output resistance of Q 1, r o, and the input resistance of the CB transistor, Q 2, namely R in2. Note that for R L < r o the latter reduces to r e, as expected. However, R in2 increases as R L is increased. Of particular interest is the value of R in2 obtained for R L =βr o, namely R in2 = r π /2. It follows that for this value of R L the CE stage has a voltage gain of -β/2. Finally, in Fig. 26 the circuit and the formulas for determining the high-frequency response of the bipolar cascade are given. The analysis is similar to that studied in the MOSFET case. A Cascode Current Source We know that to realize the high voltage gain of which the cascode amplifier is capable the load resistance R L must be at least of the order of A 0 r o, for the MOSFET cascode or βr o for the bipolar cascode. However, that R L includes the output resistance of the circuit which implements the current-source load I. This implies that the current-source must have output resistance that is at least A o r 0 for the MOS case (βr o for the BJT case). This means that the simple current-source circuits studied earlier cannot be considered, since their output resistances are equal to r 0. Fortunately, there is a conceptually simple and 51
FIGURE 27 A cascode current-source. effective solution namely, applying the cascoding principle to the current-source implementation. This is illustrated in Fig. 27, where Q 1 is the current-source transistor and Q 2 is the cascode transistor. V BlAS1, is a DC voltage that is chosen so that Q 1 provides the required value of I. V B1AS2 is chosen to keep Q 2 and Q 1, in saturation at all times. While the resistance looking into the drain of Q 1 is r ol, the cascode transistor Q 2 multiplies this resistance by (g m2 r o2 ) and provides an output resistance for the current source given approximately by R o = (g m2 r o2 )r o1. (103) Similar arrangement can be used in the bipolar case also. Double Cascoding The essence of the operation of the MOS cascode is that the CG cascode transistor Q 2 multiplies the resistance in its source, which is r 0 of the CS transistor Q 1, by its intrinsic gain A 02 to provide an output resistance A 02 r 01. It follows that we can increase the output resistance further by adding another level of cascoding, as shown in Fig. 28. Here another CG transistor Q 3 is added, and this results in increased output resistance 52
FIGURE 28 Double cascoding. by a factor A o3.thus the output resistance of this double-cascode amplifier is A 0 2 r o. An additional bias voltage has to be generated for the additional cascode transistor Q 3. A drawback of double cascoding is that an additional transistor is now stacked between the power supply rails. Furthermore, since we are now dealing with output resistances on the order of A 0 r o, the current source I will also need to be implemented using a double cascode which adds yet one more transistor to the stack. It is appropriate to recall that in modern CMOS process technologies V DD is only a bit more than 1V. Note that, since the largest output resistance possible in a bipolar cascode is βr 0, adding another level of cascoding does not provide any advantage. The Folded Cascode To avoid the problem of stacking a large number of transistors across a low-voltage power supply, one can use a PMOS transistor for the cascode device, as shown in Fig. 29. Here as before, the NMOS transistor Q 1 is operating in the CS configuration, but the CG stage is implemented using the PMOS transistor Q 2. An additional current-source I 2 is needed to bias Q 2 and provide it with its active load. Note that Q 1 is now operating at a bias current of (I 1 I 2 ). Finally, a DC voltage V BIAS is needed to provide an appropriate dc level for the gate of the cascode transistor Q 2. Its value has to be selected so that Q 2 and Q 1 operate in the saturation region. 53
The small-signal operation of the circuit in Fig. 29 is similar to that of the NMOS cascode. The difference here is that the signal current g m v i is folded down and made to flow into the source terminal of Q 2, which gives the circuit the name folded cascode. The folded cascode is a very popular building block in CMOS amplifiers. FIGURE 29 The folded cascode BiCMOS Cascodes The circuit designer can combine bipolar and MOS transistors in circuit configurations that take advantage of the unique features of each. As an example, Fig. 30 shows two possibilities for the BiCMOS implementation of the cascode amplifier. In the circuit of Fig. 30(a) a MOSFET is used for the input device, thus providing the cascode with an infinite input resistance. On the other hand, a bipolar transistor is used for the cascode device, thus providing a larger output resistance 54
FIGURE 30: BiCMOS cascodes than is possible with a MOSFET cascode. This is because β of the BJT is usually larger than A o of the MOSFET and because r o of the BJT is much larger than r 0 of modern submicron MOSFETs. Also, the bipolar CB transistor provides a lower input resistance R in2 than is usually obtained with a CG transistor, especially when R L is low. The result is a lower total resistance between the drain of Q 1 and ground and hence a reduced Miller effect in Q 1. The circuit in Fig. 30(b) utilizes a MOSFET to implement the second level of cascoding in a bipolar cascode amplifier. The need for a MOSFET stems from the fact that while the maximum possible output resistance obtained with a BJT is βr o, there is no such limit with the MOSFET, and indeed, Q 3 raises the output resistance by the factor A 03. 55
THE CS AND CE AMPLIFIERS WITH SOURCE (EMITTER) DEGENERATION Inserting a relatively small resistance (i.e. a small multiple of 1/g m ) in the source of a CS amplifier (the emitter of a common-emitter amplifier) introduces negative feedback into the amplifier stage. As a result this resistance provides the circuit designer with an additional parameter that can be effectively utilized to obtain certain desirable properties as a trade-off for the gain reduction that source (emitter) degeneration causes. The CS Amplifier with a Source Resistance Figure 31(a) shows an active-loaded CS amplifier with a source resistance R s. Note that a signal v bs will develop between body and source, and hence the body effect should be taken into account in the analysis. The circuit, prepared for small-signal analysis and with a resistance R L shown at the output, is presented in Fig. 31(b). To determine the output resistance R out, we reduce v i, to zero, which makes the circuit identical to that of a CG amplifier. Therefore we can obtain R out by using Eq. (58) as R out = r 0 + [l+(g m + g mb )r 0 ] R s (104) which for the usual situation (g m + g mb )r o > 1 reduces to R out r o [1+(g m + g mb )R s ] (105) The open-circuit voltage gain can be found from the circuit in Fig. 31(c). Noting that the current in R s must be zero, the voltage at the source, v s, will be zero and thus v gs = v i and v bs = 0, resulting in i = g m v gs 56
FIGURE 31 (a) A CS amplifier with a source-degeneration resistance R s (b) Circuit for small signal analysis. (c) Circuit with the output open to determine A vo. (d) Output equivalent circuit (e) Another output equivalent circuit in terms of G m. and Thus v o = -ir o = -g m r o v gs = -g m r o v i A vo = -g m r o = -A o (106) In other words, the resistance R s has no effect on A vo. Utilizing A vo =-A 0 and R out from Eq. (105) gives us the amplifier output equivalent circuit shown in Fig. 31(d). An alternative equivalent circuit in terms of the short-circuit transconductance G m is shown in Fig. 31(e), where G m can be found from 57
(107) The effect of R s is thus obvious: R s reduces the amplifier transconductance and increases its output resistance by the same factor: [ 1 + (g m + g mb )R s ]. The voltage gain A v can be found as (108) Thus, if R L is kept unchanged, A V will decrease, which is the price paid for the performance improvements obtained when R s is introduced. One such improvement is in the linearity of the amplifier. This comes about because only a fraction v gs of the input signal v i now appears between gate and source. Derivation of an expression for v gs /v i is significantly complicated by the inclusion of r 0. The derivation should be done with the MOSFET equivalentcircuit model explicitly used. The result is (109) which for r o > R L reduces to the familiar relationship (110) Thus the value of R s can be used to control the magnitude of v gs so as to obtain the desired linearity at the cost of gain reduction. Frequency Response Another advantage of source degeneration is the ability to broaden the amplifier bandwidth. Figure 32(a) shows the amplifier with the internal capacitances C gs and C gd indicated. A capacitance C L that includes the MOSFET capacitance C db is also shown at the output. The method of open-circuit time constants can be employed to obtain an estimate of the 3-dB frequency f H. We observe in Fig. 32(b) the circuit for determining R gd, which is the resistance seen by C gd, We observe that R gd can be determined by simply adapting the formula in Eq. (10) to the case with source degeneration as follows: R gd = R sig (1+ G m R L ) + R L (111) 58
where R L = R L II R out (112) The formula for R CL can be simply R CL = R L IIR out =R L (113) The formula for R gs is very difficult to derive, and the derivation should be performed with the hybrid-π model explicitly utilized. The result is (114) When R sig is relatively large, the frequency response will be dominated by the Miller multiplication of C gd. Another way for saying this is that C gd R gd will be the largest of the three open-circuit time constants that result in τ H. 59
FIGURE 32 (a) The CS amplifier circuit, with a source resistance R s, prepared for frequency response analysis, (b) Determining the resistance R gd seen by the capacitance C gd. τ H = C gs R gs + C gd R gd + C L R CL.. (115) τ H C gd R gd.. (116) and correspondingly to obtain f H as.. (117) Now, as R s is increased, the gain magnitude, A M = G m R L will decrease, causing 60
R gd to decrease (Eq.111), which in turn causes f H to increase (Eq.117). To highlight the trade-off between gain and bandwidth that R s affords the designer, let us simplify the expression for R gd in Eq. (111) by assuming that G m R L > 1, and G m R sig >1 R gd = G m R L R sig = A M R sig.. (118) which can be substituted in Eq. (117) to obtain.. (119) which very clearly shows the gain-bandwidth trade-off. The gain-bandwidth product remains constant at Gain-bandwidth product.. (120) In practice, however, the other capacitances will play a role in determining f H, and f t will decrease somewhat as R s is increased. The CE Amplifier with an Emitter Resistance Emitter degeneration is even more useful in the CE amplifier than source degeneration is in the CS amplifier. This is because emitter degeneration increases the input resistance of the CE amplifier. Figure 33 (a) shows an active-loaded CE amplifier with an emitter resistance R e usually in the range of 1 to 5 times r e. Figure 33(b) shows the circuit for determining the Figure 33 : an active-loaded CE amplifier with an emitter resistance 61
Input resistance R ln, which due to the presence of r o will depend on the value of R L. With the help of the analysis shown in Fig. 33(b), we can express the output voltage v 0 as.. (122) we can also express v o as.. (123) Equating these two expressions of v o yields an equation in v i and i, which can be rearranged to obtain.. (124).. (125) Usually R L is on the order of r 0 ; thus R L /(β + 1) < r 0. Also, R e < r o. Taking account of these two conditions enables us to simplify the expression for R in to.. (126) This expression indicates that the presence of r o reduces the effect of R e on increasing R in. This is because r o shunts away some of the current that would have flowed through R e. For example, for R L = r 0, R in = (β + 1)(r e + 0.5R e )... (127) To determine the open-circuit voltage gain A vo, we utilize the circuit shown in Fig. 33(c). Analysis of this circuit is straightforward and can be shown to yield A vo = -g m r 0.. (128) That is, the open-circuit voltage gain obtained with a relatively small R e (i.e., of the order of r e ) remains very close to the value without R e. The output resistance R o is identical to the value of R out that we derived for the CB circuit (Eq. 78), R o =r o (1+g m R e ).. (129) where R' e = R e // r π. Since R e is on the order of r e, R e is much smaller than r π and R' e = R e. Thus, 62
R 0 = r o (1+g m R e ).. (130) The expressions for R in, A vo,and R o in Eqs. (127), (128), and (130), respectively, can be used to determine the overall voltage gain for given values of source resistance and load resistance. Finally, we should mention that A vo and R o can be used to find the effective shortcircuit transconductance G m,of the emitter-degenerated CE amplifier as follows:.. (131).. (132) The high-frequency response of the CE amplifier with emitter degeneration can be found in a manner similar to that presented above for the CS amplifier. In summary, including a relatively small resistance R e (i.e.. a small multiple of r e ) in the emitter of the active-loaded CE amplifier reduces its effective transconductance by the factor ( 1 + g m R e ) and increases its output resistance by the same factor, thus leaving the opencircuit voltage gain approximately unchanged. The input resistance R in is increased by a factor that depends on R e and that is somewhat lower than ( 1 + g m R e ). Also, including R e reduces the severity of the Miller effect and correspondingly increases the amplifier bandwidth. Finally, an emitter-degeneration resistance R e increases the linearity of the amplifier. THE SOURCE AND EMITTER FOLLOWERS In the following discussion we consider their IC versions of source and emitter followers, with a special emphasis on their high-frequency response. The Source Follower Figure 34(a) shows an IC source follower biased by a constant-current source I, which is usually implemented using an NMOS current mirror. The source follower would generally be part of a larger circuit that determines the dc voltage at the transistor gate. Here, v i is the input signal appearing at the gate and R L represents the combination of a load resistance and the output resistance and the current-source I. The low-frequency small-signal model of the source follower is shown in Fig- 34(b)- Observe that r o appears in parallel with R L and thus can be combined with it. Also, the controlled current-source g mb v bs feeds its current into the source terminal, where the voltage is -v bs. Thus we can use the source-absorption theorem to replace the current source with a resistance 1 /g mb between the source and ground, this can then be combined with R L and r 0. 63
With these two simplifications, the equivalent circuit takes the form shown in Fig. 34(c), where.. (133) We now write the output voltage v 0 as v o = g m v gs R L v gs is given by, v gs = v i v o.. (134) FIGURE 34 (a) An IC source follower, (b) Small-signal equivalent-circuit model of the source follower. (c) A simplified version of the equivalent circuit (d) Determining the output resistance of the source follower. 64
Equations (133) and (134) can be combined to obtain the voltage gain.. (135) which, as expected, is less than unity. To obtain the open-circuit voltage gain, we set R L in Eq. (133) to, which reduces R' L to r o II (1 /g mb ). Substituting this value for R' L in Eq. (135) gives.. (136) which, for the usual case where (g m + g mb )r 0 > 1 simplifies to.. (137) Thus the highest value possible for the voltage gain of the source follower is limited to l/(l +χ), which is typically 0.8 V/V to 0.9 V/V. Finally, we can find the output resistance R o of the source follower either using the equivalent circuit of Fig. 34(c) or by inspection of the circuit in Fig. 34 (d) as.. (138) which can be approximated as R o = 1/[(1+χ)g m ].. (140) Similar to the discrete source follower, the IC source follower can be used as the output stage of a multistage amplifier to provide a low output resistance for driving lowimpedance loads. It is also used to shift the dc level of the signal by an amount equal to V GS. Frequency Response of the Source Follower A major advantage of the source follower is its excellent high-frequency response. This comes about because, as we shall now see, none of the internal capacitances suffers from the Miller effect. Figure 35(a) shows the high-frequency equivalent circuit of a source follower fed with a signal V sjg from a source having a resistance R sig. In addition to the MOSFET 65
capacitances C gs and C gd, a capacitance C L is included between the output node and ground to account for the source-to-body capacitance C sb as well as any actual load capacitance. The simplifications performed above on the low-frequency equivalent circuit can be applied to the high-frequency model of Fig. 35(a) to obtain the equivalent circuit in Fig. 35(b), where R L is given by Eq. (133). Although one can derive an expression for the transfer function of this circuit, the resulting expression will be too complicated to yield insight regarding the role that each of the three capacitances plays. Rather, we shall first determine the location of the transmission zeros and then use the method of open-circuit time constants to estimate the 3-dB frequency, f 3dB. Although there are three capacitances in the circuit of Fig. 35(b), the transfer function is of the second order. This is because the three capacitances form a continuous loop. To determine the location of the two transmission zeros, refer to the circuit in Fig. 35(b), and note that v 0 is zero at the frequency at which C L has a zero impedance and thus acts as a short circuit across the output, which is ω or s =. Also, v o will be zero at the value of s that causes the current into the impedance R L II C L to be zero. Since this current is (g m + sc gs )v gs -the transmission zero will be at s = s z, where.. (142) That is, the zero will be on the negative real-axis of the s-plane with a frequency.. (143) 66
FIGURE 35 Analysis of the high-frequency response of the source follower (a) Equivalent circuit (b) simplified equivalent circuit and (c) determining the resistance R gs seen by C gs Recalling that the MOSFET's ω T = g m /(C gs + C gd ) and that C gd < C gs, we see that ω z, will be very close to ω T f z = f T.. (144) Next, we turn our attention to the poles. Specifically, we will find the resistance seen by each of three capacitances C gd, C gs, and C L and then compute the time constant associated with each. With V sig set to zero and C gs and C L assumed to be open circuited, we find by inspection that the resistance R gd seen by C gd is given by R gd = R sig.. (145) Next, we consider the effect of C gs The resistance R gs seen by C gs can be determined by straightforward analysis of the circuit in Fig. 35(c) to obtain.. (146) We note that the factor (1 + g m R L ) in the denominator will result in reducing the effective resistance with which C gs interacts. In the absence of the two other capacitances, C gs together with R gs introduce a pole with frequency l/2πc gs R gs. 67
Finally, it is easy to see from the circuit in Fig. 35(b) that C L interacts with R L // R o that is. R CL = R L II R O.. (147) Usually, R 0 (Eq. 138) is low. Thus R CL will be low. and the effect of C L will be small. Nevertheless, all three time constants can be added to obtain τ H and hence f H,.. (148) The Emitter Follower Figure 36(a) shows an emitter follower suitable for IC fabrication. It is biased by a constant-current source, I. However, the circuit that sets the DC voltage at the base is not shown. The emitter follower is fed with a signal V sig from a source with resistance R sig. The resistance R L shown at the output, includes the output resistance of current source I as well as any actual load resistance. Analysis of the emitter follower of Fig. 36(a) will give low-frequency gain, A v = R L / (R L + r e ) (almost equal to 1).. (149) Input resistance, R in = (1+β)(R L +r e ).. (150) Output resistance, R out = r o (r π +R sig ) / [(r π +R sig ) + (1+β)r o ].. (151) Here r o is parallel combination of output resistances of current source transistor and amplifying transistor. The circuit can be used as voltage buffer because of unity gain, high input resistance and low output resistance. Figure 36(b) shows the high-frequency equivalent circuit. Lumping r o together with R L and r x together with R sig and making a slight change in the way the circuit is drawn results in the simplified equivalent circuit shown in Fig. 36(c). We will follow a procedure for the analysis of this circuit similar to that used above for the source follower. Specifically, to obtain the location of the transmission zero, note that V o will be zero at the frequency s z for which the current fed to R' L is zero:.. (152) 68
FIGURE : 36 (a) Emitter follower (b) High frequency equivalent circuit (c) Simplified equivalent circuit which is on the negative real-axis of the s-plane and has a frequency.. (154) This frequency is very close to the unity gain frequency ω T of the transistor. The other transmission zero is at s =. This is because at this frequency, C µ acts as a short circuit, making V π zero, and hence V o will be zero. Next, we determine the resistances seen by C µ and C π. For C µ, the resistance it sees, R µ, is the parallel equivalent of R sig and the input resistance looking into B ; that is,.. (155) Equation (155) indicates that R µ will be smaller than R sig and since c µ is usually very small, the time constant C µ R µ will be correspondingly small. The resistance R π seen by C π can be determined using an analysis similar to that employed for the determination of R gs in the MOSFET case. The result is 69
.. (156) We observe that the term R L /r e will usually make the denominator much greater than unity thus rendering R π rather low. Thus, the time constant C π R π will be small. The end result is that the 3-dB frequency f H of the emitter follower will usually be very high. f H = 1/[2π (C µ R µ + C π R π )].. (157) SOME USEFUL TRANSISTOR PAIRINGS The cascode configuration studied above combines CS and CG MOS transistors (CE and CB bipolar transistors) to great advantage. The key to the superior performance is that the transistor pairing is done in a way that maximizes the advantages and minimizes the shortcomings of each of the two individual configurations. In this section we study a number of other such transistor pairings. In each case the transistor pair can be thought of as a compound device; thus the resulting amplifier may be considered as a single stage. The CD-CS, CC-CE and CD-CE Configurations Figure 37(a) shows an amplifier formed by cascading a common-drain (source-follower) transistor Q 1 with a common-source transistor Q 2. As should be expected, the voltage of the circuit will be a little lower than that of the CS amplifier. The advantage of this circuit FIGURE 37 (a) CD-CS amplifier (b) CC-CE amplifier (c) CD-CE amplifier 70
configuration, however, lies in its bandwidth, which is much wider than that obtained in a CS amplifier. To see how this comes about, note that the CS transistor Q 2 will still exhibit a Miller s effect that results in a large input capacitance, C in2, between its gate and ground. However, the resistance that this capacitance interacts with will be much lower than R sig the buffering action of the source follower causes a relatively low resistance, approximately equal to a l/(g m1 + g mb1 ), to appear between the source of Q 1 and ground across C in2. The bipolar counterpart of the CD-CS circuit is shown in Fig. 37(b). Besides achieving a wider bandwidth than that obtained with a CE amplifier, the CC-CE configuration has an important additional advantage: The input resistance is increased by a factor equal to (β 1 + 1). Finally, we show in Fig. 37(c) the BiCMOS version of this circuit type. Observe that Q 1 provides the amplifier with an infinite input resistance. Also, note that Q 2 provides the amplifier with a high g m as compared to that obtained in the MOSFET circuit in Fig. 37(a) and hence high gain. EXAMPLE Consider a CC-CE amplifier such as that in Fig. 37(b) with the following specifications: I 1 = I 2 = 1mA and identical transistors with β = 100, f T = 400 MHz, and C µ = 2 pf. Let the amplifier be fed with a source V sig having a resistance R sig = 4 k, and assume a load resistance of 4 k. Find voltage gain A M, and estimate the 3-dB frequency, f H. Compare the results with those obtained with a CE amplifier operating under the same conditions. For simplicity, neglect r o and r x. Solution At an emitter bias current of 1 ma, Q 1, and Q 2 have 71
38(a) To determine f H we use the method of open-circuit time constants. Figure 38(b) shows the circuit with V sig set to zero and the four capacitances indicated. Capacitance C µ1 sees a resistance R µ1 72
FIGURE 38 Circuits for above Example: (a) The CC-CE circuit prepared for lowfrequency small singal analysis (b) the circuit at high frequencies, with V sig set to zero to enable determination of the open-ckt time constants and (c) a CE amplifier for comparison. To find the resistance R π1 seen by capacitance C π1, we refer to the analysis of the highfrequency response of the emitter follower Section. We may write as follows: Capacitance C π2 sees a resistance R π2, Capacitance C µ2 sees a resistance R µ2 To determine R µ2 we refer to the analysis of the frequency response of the CE amplifier Section to obtain 73
We now can determine τ H from We observe that C π1 and C π2 play a very minor role in determining the high-frequency response. As expected, C µ2, through the Miller effect plays the most significant role. Also, C µ1 which interacts directly with (R sig II R in ), also plays an important role. The 3-dB frequency f H can be found as follows: For comparison, we evaluate A M and f H of a CE amplifier operating under the same conditions. Refer to Fig. 38(c). The voltage gain A M is given by 74
Thus, including the buffering transistor Q 1 increases the gain, A M, from 61.5 V/V to 155 V/V a factor of 2.5 and increases the bandwidth from 303 khz to 4.2 MHz a factor of 13.9! The gainbandwidth product is increased from 18.63 MHz to 651 MHz a factor of 35! The Darlington Configuration Figure 39(a) shows a popular BJT circuit known as the Darlington configuration. It can be thought of as a variation of the CC-CE circuit with the collector of Q 1 connected to that of Q 2. Alternatively, the Darlington pair can be thought of as a composite transistor with β = β 1 β 2. It can therefore be used to implement a high-performance voltage follower, as illustrated in Fig. 39(b). Note that in this application the circuit can be considered as the cascade connection of two common-collector transistors (i.e., a CC-CC configuration). FIGURE 39 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration; and (c) the Darlington follower with a bias current I applied to Q 1 to ensure that its β remains high. 75
Since the transistor β depends on the dc bias current, it is possible that Q 1 will be operating at a very low β, rendering the β-multiplication effect of the Darlington pair rather ineffective. A simple solution to this problem is to provide a bias current for Q 1 as shown in Fig. (39c). The CC-CB and CD-CG Configurations Cascading an emitter follower with a common-base amplifier, as shown in Fig. 40(a) results in a circuit with a low-frequency gain approximately equal to that of the CB but with the problem of the low input resistance of the CB solved by the buffering action of the CC stage. Since neither the CC nor the CB amplifier suffers from the Miller effect, the CC-CB FIGURE 40 (a) A CC-CB amplifier (b) Another version of the CC-CB circuit with Q 2 implemented using a pnp transistor. (c) The MOSFET version of the circuit in (a). configuration has excellent high-frequency performance. Note that the biasing current sources shown in Fig. 40(a) ensure that each of Q 1 and Q 2 is operating at a bias current I. We are not showing, however, how the dc voltage at the base of Q 1 is set or the circuit that determines the dc voltage at the collector of Q 2. Both issues are usually looked after in the larger circuit of which the CC-CB amplifier is part. An interesting version of the CC-CB configuration is shown in Fig. 40(b). Here the CB stage is implemented with a pnp transistor. Although only one current source is now needed, observe that we also need to establish an appropriate voltage at the base of Q 2. This circuit is part of the internal circuit of the popular 741 op amp. The MOSFET version of the circuit in Fig. 40(a) is the CD-CG amplifier shown in Fig. 40(c). 76
We now briefly analyze the circuit in Fig. 40(a) to determine its gain A M and its highfrequency response. The analysis applies directly to the circuit in Fig. 40(b) and, with appropriate change of component and parameter names, to the MOSFET version in Fig. 40(c). For simplicity we shall neglect r x and r o of both transistors. The input resistance R in is given by R in = (β 1 + 1 )(r e1 + r e2 ). (158) which for r e1 = r e2 = r e and β 1 = β 2 = β 3 becomes R in = 2r π. (159) If a load resistance R L is connected at the output, the voltage gain V a /V i will be. (160) Now, if the amplifier is fed with a voltage signal V sig from a source with a resistance R sig, the overall voltage gain will be. (161) The high-frequency analysis is illustrated in Fig. 41(a). Here we have drawn the hybrid-π equivalent circuit for each of Q 1 and Q 2. Recalling that the two transistors are operating at equal bias currents, their corresponding model components will be equal (i.e. r π1 = r π2, c π1 = c π2 etc). With this in mind the reader should be able to see that V π1 = -V π2 and the horizontal line through the node labeled E in Fig. 41(a) can be deleted. Thus the circuit reduces to that in Fig. 41(b). This is a very attractive outcome because the circuit shows clearly the two poles that determine the high-frequency response: The pole at the input, with a frequency f p1 is. (162) and the pole at the output, with a frequency f P2, is. (163) 77
This result is also intuitively obvious: The input impedance at B 1 of the circuit in Fig. 41 consists of the series connection of r π1 and r π2 in parallel with the series connection of C π1 and C π2. Then there is C µ in parallel. At the output, we simply have R L in parallel with Cµ FIGURE 41 (a) Equivalent circuit for the amplifier in Fig. 40(a). (b) Simplified equivalent circuit Whether one of the two poles is dominant will depend on the relative values of R sig and R L. If the two poles are close to each other, then the 3-dB frequency f H can be determined either by exact analysis that is, finding the frequency at which the gain is down by 3 db or by using the approximate formula derived in unit2(last section),. (164) 78
CURRENT-MIRROR CIRCUITS WITH IMPROVED PERFORMANCE Current sources play an important role in the design of IC amplifiers: The constant-current source is used both in biasing and as active load. Simple forms of both MOS and bipolar current sources and, more generally, current mirrors are already studied. However, two performance parameters need to be addressed: the accuracy of the current transfer ratio of the mirror and the output resistance of the current source. We may recall that the accuracy of the current transfer ratio suffers particularly from the finite β of the BJT. The output resistance, which in the simple circuits is limited to r 0 of the MOSFET and the BJT, also reduces accuracy and, much more seriously, severely limits the gain available from cascode amplifiers. In this section we study MOS and bipolar current mirrors with more accurate current transfer ratios and higher output resistances. Cascode MOS Mirrors Figure 42 shows the basic cascode current mirror. Observe that in addition to the diodeconnected transistor Q 1, which forms the basic mirror Q 1 -Q 2, another diode-connected transistor, Q 4, is used to provide a suitable bias voltage for the gate of the cascode transistor Q 3 To determine the output resistance of the cascode mirror at the drain of Q 3, we set I REF to zero. Also, since Q 1 and Q 4 have a relatively small incremental resistance, each of approximately 1/g m, the incremental voltages across them will be small, and we can assume that the gates of Q 3 and Q 2 are both grounded. Thus the output resistance R o will be that of the CG transistor Q 3, which has a resistance r ol in its source. Equation (86) can be adapted to obtain R o =r o3 + [1+ (g m3 + g mb3 ) r o3 ]r o2 = g m3 r o3 r o2. (165) 79
Thus, as expected, cascoding raises the output resistance of the current source by the factor g m3 r o3 which is the intrinsic gain of the cascode transistor. FIGURE 42 A cascode MOS current mirror. A drawback of the cascode current mirror is that it consumes a relatively large portion of the steadily shrinking supply voltage V DD. While the simple MOS mirror operates properly with a voltage as low as V ov across its output transistor, the cascode circuit of Fig. 42 requires a minimum voltage of V t + 2V ov. This is because the gate of Q 3 is at 2V GS = 2 V t + 2V ov. Thus the minimum voltage required across the output of the cascode mirror is 1 V or so. This obviously limits the signal swing at the output of the mirror (i.e.. at the output of the amplifier that utilizes this current source as a load). A Bipolar Mirror with Base-Current Compensation Figure 43 shows a bipolar current mirror with a current transfer ratio that is much less dependent on β than that of the simple current mirror. The reduced dependence on β is obtained by including transistor Q 3, the emitter of which supplies the base currents of Q 1 and Q 2. The sum of the base currents is then divided by (β 3 + 1), resulting in a much smaller error current that has to be supplied by I REF. Detailed analysis is shown on the circuit diagram; it is based on the assumption mat Q 1 and Q 2 are matched and thus have equal collector currents, I c. A node equation at the node labeled x gives. (166) 80
Since I o = I c FIGURE 43 A current mirror with base-current compensation. the current transfer ratio of the mirror will be. (167) which means that the error due to finite β has been reduced from 2/β in the simple mirror to 2/β 2, a tremendous improvement. Unfortunately, however, the output resistance remains approximately equal to that of the simple mirror, namely r 0. If a reference current I REF is not available, we simply connect node x to the power supply V cc through a resistance R. The result is a reference current given by. (168) The Wilson Current Mirror A simple but clever modification of the basic bipolar mirror results in both reducing the β dependence and increasing the output resistance. The circuit, known as the Wilson mirror after its inventor, George Wilson, an IC design engineer working for Tektronix, is shown in Fig. 44(a). The analysis to determine the effect of finite β on the current transfer 81
FIGURE 44 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio: and (b) determining the output resistance. Note that the current i x that enters Q 3 must equal the sum of the currents that leave it, 2i. ratio is shown in Fig. 44(a), from which we can write. (169) This analysis assumes that Q 1, and Q 2 conduct equal collector currents. However, there is a slight problem with this assumption: The collector-to-emitter voltages of Q 1 and Q 2 are not equal, which introduces a current offset or a systematic error. The problem can be solved by adding a diode-connected transistor in series with the collector of Q 2, as is shown for the MOS version. Analysis to determine the output resistance of the Wilson mirror is illustrated in Fig. 44(b), from which we see that 82