D Series Power MOSFET PRODUCT SUMMARY (V) at T J max. 55 R DS(on) max. at 25 C () V GS = V.4 Q g max. (nc) 58 Q gs (nc) 8 Q gd (nc) 4 Configuration Single TO22AB D G G DS S NChannel MOSFET ORDERING INFORMATION Package Lead (Pb)free Lead (Pb)free and Halogenfree FEATURES Optimal Design Low Area specific OnResistance Low Input Capacitance (C iss ) Reduced Capacitive Switching Losses High Body Diode Ruggedness Avalanche Energy Rated (U IS ) Optimal Efficiency and Operation Low Cost Simple Gate Drive Circuitry Low FigureOfMerit (FOM): R on x Q g Fast Switching Material categorization: For definitions of compliance please see www.vishay.com/doc?9992 Note * Lead (Pb)containing terminations are not RoHScompliant. Exemptions may apply. APPLICATIONS Consumer Electronics Displays (LCD or Plasma TV Server and Telecom Power Supplies SMPS Industrial Welding, Induction Heating, Motor Drives Battery Chargers TO22AB E3 GE3 ABSOLUTE MAXIMUM RATINGS (T C = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT DrainSource Voltage 5 GateSource Voltage ± 3 V V GS GateSource Voltage AC (f > Hz) 3 Continuous Drain Current (T J = 5 C) V GS at V T C = 25 C 4 I D T C = C 9 A Pulsed Drain Current a I DM 38 Linear Derating Factor.6 W/ C Single Pulse Avalanche Energy b E AS 56 mj Maximum Power Dissipation P D 28 W Operating Junction and Storage Temperature Range T J, T stg 55 to 5 C DrainSource Voltage Slope T J = 25 C 24 dv/dt Reverse Diode dv/dt d.4 V/ns Soldering Recommendations (Peak Temperature) for s 3 c C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. V DD = 5 V, starting T J = 25 C, L = 2.3 mh, R g = 25, I AS = 7 A. c..6 mm from case. d. I SD I D, starting T J = 25 C. S2229Rev. A, 2May2 Document Number: 952
THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum JunctiontoAmbient R thja 62 C/W Maximum JunctiontoCase (Drain) R thjc.6 SPECIFICATIONS (T J = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static DrainSource Breakdown Voltage V GS = V, I D = 25 μa 5 V Temperature Coefficient /T J Reference to 25 C, I D = 25 μa.58 V/ C Gate Threshold Voltage (N) V GS(th) = V GS, I D = 25 μa 3. 5. V GateSource Leakage I GSS V GS = ± 3 V ± na = 5 V, V GS = V Zero Gate Voltage Drain Current I DSS = 4 V, V GS = V, T J = 25 C μa DrainSource OnState Resistance R DS(on) V GS = V I D = 7 A.32.4 Forward Transconductance a g fs = 5 V, I D = 7 A 5.2 S Dynamic Input Capacitance C iss VGS = V, 44 Output Capacitance C oss = V, Reverse Transfer Capacitance C rss f = MHz 2 Effective Output Capacitance, Energy pf Related a C o(er) 87 V GS = V, = V to 48 V Effective Output Capacitance, Time Related b C o(tr) 25 Total Gate Charge Q g 29 58 GateSource Charge Q gs V GS = V I D = 7 A, = 4 V 8 nc GateDrain Charge Q gd 4 TurnOn Delay Time t d(on) 6 32 Rise Time t r V DD = 4 V, I D = 7 A, 27 54 TurnOff Delay Time t d(off) V GS = V, R g = 9. 29 58 ns Fall Time t f 26 52 Gate Input Resistance R g f = MHz, open drain.7 DrainSource Body Diode Characteristics MOSFET symbol D Continuous SourceDrain Diode Current I S 4 showing the integral reverse G Pulsed Diode Forward Current I SM S p n junction diode 56 Diode Forward Voltage V SD T J = 25 C, I S = 7 A, V GS = V.2 V Reverse Recovery Time t rr 39 ns Reverse Recovery Charge Q rr T J = 25 C, I F = I S = 7 A, di/dt = A/μs, V R = 2 V 3. μc Reverse Recovery Current I RRM 8 A Notes a. C oss(er) is a fixed capacitance that gives the same energy as C oss while is rising from % to 8 % S. b. C oss(tr) is a fixed capacitance that gives the same charging time as C oss while is rising from % to 8 % S. A S2229Rev. A, 2May2 2 Document Number: 952
TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) I D, DraintoSource Current (A) 4 3 2 TOP 5 V 4 V 3 V 2 V V V 9. V 8. V 7. V 6. V T J = 25 C R DS(on), DraintoSource On Resistance (Normalized) 3 2.5 2.5.5 I D = 7 A V GS = V 5. V 5 5 2 25 3, DraintoSource Voltage (V) Fig. Typical Output Characteristics 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. 4 Normalized OnResistance vs. Temperature I D, DraintoSource Current (A) 3 24 8 2 6 TOP 5 V 4 V 3 V 2 V V V 9. V 8. V 7. V 6. V BOTYTOM 5. V T J = 5 C 5. V 5 5 2 25 3, DraintoSource Voltage (V) Fig. 2 Typical Output Characteristics Capacitance (pf) C oss C rss C iss, DraintoSource Voltage (V) Fig. 5 Typical Capacitance vs. DraintoSource Voltage V GS = V, f = MHz C iss = C gs C gd, C ds Shorted C rss = C gd C oss = C ds C gd 2 3 4 5 I D, DraintoSource Current (A) 4 3 2 T J = 5 C T J = 25 C V GS, GatetoSource Voltage (V) 24 2 6 2 8 4 = 4 V = 25 V = V 5 5 2 25 V GS, GatetoSource Voltage (V) Fig. 3 Typical Transfer Characteristics 2 3 4 5 Q g, Total Gate Charge (nc) Fig. 6 Typical Gate Charge vs. GatetoSource Voltage S2229Rev. A, 2May2 3 Document Number: 952
6 I SD, Reverse Drain Current (A) T J = 5 C T J = 25 C V GS = V..2.4.6.8.2.4.6 V SD, SourceDrain Voltage (V) Fig. 7 Typical SourceDrain Diode Forward Voltage I D, Drain Current (A) 2 8 4 25 5 75 25 5 T J, Case Temperature ( C) Fig. 9 Maximum Drain Current vs. Case Temperature 625 I D, Drain Current (A) Operation in this Area Limited by R DS(on) Limited by R DS(on) * I DM = Limited T C = 25 C ms T J = 5 C Single Pulse BVDSS Limited., DraintoSource Voltage (V) * V GS > minimum V GS at which R DS(on) is s Fig. 8 Maximum Safe Operating Area μs ms, DraintoSource Brakdown Voltage (V) 6 575 55 525 5 475 6 4 2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig. Temperature vs. DraintoSource Voltage Normalized Effective Transient Thermal Impedance. Duty Cycle =.5.2..5.2 Single Pulse..... Pulse Time (s) Fig. Normalized Thermal Transient Impedance, JunctiontoCase S2229Rev. A, 2May2 4 Document Number: 952
R D R G V GS D.U.T. V Q GS Q G Q GD V DD V Pulse width μs Duty factor. % Fig. 2 Switching Time Test Circuit V G Charge Fig. 6 Basic Gate Charge Waveform 9 % Current regulator Same type as D.U.T. 5 kω 2 V.2 μf.3 μf % V GS t d(on) t r t d(off) t f D.U.T. V DS V GS 3 ma Vary t p to obtain required I AS Fig. 3 Switching Time Waveforms L Fig. 7 Gate Charge Test Circuit I G I D Current sampling resistors R G I AS D.U.T. V DD V t p. Ω Fig. 4 Unclamped Inductive Test Circuit t p V DD I AS Fig. 5 Unclamped Inductive Waveforms S2229Rev. A, 2May2 5 Document Number: 952
Peak Diode Recovery dv/dt Test Circuit D.U.T. Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer R g dv/dt controlled by R g Driver same type as D.U.T. I SD controlled by duty factor D D.U.T. device under test V DD Driver gate drive P.W. Period D = P.W. Period V GS = V a D.U.T. l SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. waveform Diode recovery dv/dt V DD Reapplied voltage Inductor current Body diode forward drop Ripple 5 % I SD Note a. V GS = 5 V for logic level devices Fig. 8 For NChannel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?952. S2229Rev. A, 2May2 6 Document Number: 952
Package Information TO22AB D L H() Q L() E 2 3 M * b() Ø P A F MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 4.25 4.65.67.83 b.69..27.4 b().2.73.47.68 c.36.6.4.24 D 4.85 5.49.585.6 E.4.5.395.44 e 2.4 2.67.95.5 e() 4.88 5.28.92.28 F.4.4.45.55 H() 6.9 6.48.24.255 J() 2.4 2.92.95.5 L 3.35 4.2.526.552 L() 3.32 3.82.3.5 Ø P 3.54 3.94.39.55 Q 2.6 3..2.8 ECN: X228Rev. N, 8Oct2 DWG: 547 e b C Notes * M =.32 mm to.62 mm (dimension including protrusion) Heatsink hole for HVM Xi an and Mingxin actual photo e() J() Revison: 8Oct2 Document Number: 795
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