100V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand a high energy pulse in the avalanche and commutation modes. These devices are well suited for low voltage applications such as audio amplifier, high efficiency switching DC/DC converters, and DC motor control. Features January 2001 QFET TM 12.8A, 100V, R DS(on) = 0.18Ω @ = 10 V Low gate charge ( typical 12 nc) Low Crss ( typical 20 pf) Fast switching 100% avalanche tested Improved dv/dt capability 175 C maximum junction temperature rating D D! G S D 2 -PAK FQB Series G D S I 2 -PAK FQI Series G "! " "! "! S Absolute Maximum Ratings T C = 25 C unless otherwise noted Symbol Parameter Units S Drain-Source Voltage 100 V I D Drain Current - Continuous (T C = 25 C) 12.8 A - Continuous (T C = 100 C) 9.05 A I DM Drain Current - Pulsed (Note 1) 51.2 A S Gate-Source Voltage ± 25 V E AS Single Pulsed Avalanche Energy (Note 2) 95 mj I AR Avalanche Current (Note 1) 12.8 A E AR Repetitive Avalanche Energy (Note 1) 6.5 mj dv/dt Peak Diode Recovery dv/dt (Note 3) 6.0 V/ns P D Power Dissipation (T A = 25 C) * 3.75 W Power Dissipation (T C = 25 C) 65 W - Derate above 25 C 0.43 W/ C T J, T STG Operating and Storage Temperature Range -55 to +175 C T L Maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds 300 C Thermal Characteristics Symbol Parameter Typ Max Units R θjc Thermal Resistance, Junction-to-Case -- 2.31 C/W R θja Thermal Resistance, Junction-to-Ambient * -- 40 C/W R θja Thermal Resistance, Junction-to-Ambient -- 62.5 C/W * When mounted on the minimum pad size recommended (PCB Mount) 2000 Fairchild Semiconductor International Rev. A1, January 2001
Electrical Characteristics T C = 25 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BS Drain-Source Breakdown Voltage = 0 V, I D = 250 µa 100 -- -- V BS Breakdown Voltage Temperature / T J Coefficient I D = 250 µa, Referenced to 25 C -- 0.09 -- V/ C I DSS = 100 V, = 0 V -- -- 1 µa Zero Gate Voltage Drain Current = 80 V, T C = 150 C -- -- 10 µa I GSSF Gate-Body Leakage Current, Forward = 25 V, = 0 V -- -- 100 na I GSSR Gate-Body Leakage Current, Reverse = -25 V, = 0 V -- -- -100 na On Characteristics (th) Gate Threshold Voltage =, I D = 250 µa 2.0 -- 4.0 V R DS(on) Static Drain-Source On-Resistance = 10 V, I D = 6.4 A -- 0.142 0.18 Ω g FS Forward Transconductance = 40 V, I D = 6.4 A (Note 4) -- 6.8 -- S Dynamic Characteristics C iss Input Capacitance = 25 V, = 0 V, -- 345 450 pf C oss Output Capacitance f = 1.0 MHz -- 100 130 pf C rss Reverse Transfer Capacitance -- 20 25 pf Switching Characteristics t d(on) Turn-On Delay Time -- 5 20 ns V DD = 50 V, I D = 12.8 A, t r Turn-On Rise Time R G = 25 Ω -- 55 120 ns t d(off) Turn-Off Delay Time -- 20 50 ns t f Turn-Off Fall Time (Note 4, 5) -- 25 60 ns Q g Total Gate Charge = 80 V, I D = 12.8 A, -- 12 16 nc Q gs Gate-Source Charge = 10 V -- 2.5 -- nc Q gd Gate-Drain Charge (Note 4, 5) -- 5.1 -- nc Drain-Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain-Source Diode Forward Current -- -- 12.8 A I SM Maximum Pulsed Drain-Source Diode Forward Current -- -- 51.2 A V SD Drain-Source Diode Forward Voltage = 0 V, I S = 12.8 A -- -- 1.5 V t rr Reverse Recovery Time = 0 V, I S = 12.8 A, -- 72 -- ns Q rr Reverse Recovery Charge di F / dt = 100 A/µs (Note 4) -- 0.17 -- µc Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 0.87mH, I AS = 12.8A, V DD = 25V, R G = 25 Ω, Starting T J = 25 C 3. I SD 12.8A, di/dt 300A/µs, V DD BS, Starting T J = 25 C 4. Pulse Test : Pulse width 300µs, Duty cycle 2% 5. Essentially independent of operating temperature 2000 Fairchild Semiconductor International Rev. A1, January 2001
Typical Characteristics I D, Drain Current [A] 10 1 10 0 Top : 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V I D, Drain Current [A] 10 1 10 0 25 175-55 1. 250μs Pulse Test 2. T C = 25 1. = 40V 2. 250μs Pulse Test 10-1 10-1 10 0 10 1, Drain-Source Voltage [V] 10-1 2 4 6 8 10, Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 0.8 R DS(ON) [Ω ], Drain-Source On-Resistance 0.6 0.4 0.2 = 10V = 20V Note : T J = 25 0.0 0 10 20 30 40 I D, Drain Current [A] I DR, Reverse Drain Current [A] 10 1 10 0 175 25 1. = 0V 2. 250μs Pulse Test 10-1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V SD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 900 750 C iss = C gs + C gd (C ds = shorted) C oss = C ds + C gd C rss = C gd 12 10 = 50V = 80V Capacitance [pf] 600 450 300 150 C iss C oss C rss 1. = 0 V 2. f = 1 MHz, Gate-Source Voltage [V] 8 6 4 2 Note : I D = 12.8A 0 10-1 10 0 10 1, Drain-Source Voltage [V] 0 0 2 4 6 8 10 12 Q G, Total Gate Charge [nc] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics 2000 Fairchild Semiconductor International Rev. A1, January 2001
Typical Characteristics (Continued) BS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 0.9 0.8-100 -50 0 50 100 150 200 T J, Junction Temperature [ o C] 1. = 0 V 2. I D = 250 μa R DS(ON), (Normalized) Drain-Source On-Resistance 3.0 2.5 2.0 1.5 1.0 0.5 0.0-100 -50 0 50 100 150 200 T J, Junction Temperature [ o C] 1. = 10 V 2. I D = 6.4 A Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature I D, Drain Current [A] 10 2 10 1 10 0 Operation in This Area is Limited by R DS(on) 2. T J = 175 o C 3. Single Pulse 10-1 10 0 10 1 10 2, Drain-Source Voltage [V] DC 1. T C = 25 o C 10 ms 1 ms 100 µs I D, Drain Current [A] 15 12 9 6 3 0 25 50 75 100 125 150 175 T C, Case Temperature [ ] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature Z θ JC (t), Thermal Response 10 0 10-1 D=0.5 0.2 0.1 0.05 0.02 0.01 single pulse N otes : 1. Z θ JC (t) = 2.31 /W M ax. 2. D uty Factor, D =t 1 /t 2 3. T JM - T C = P DM * Z θ JC (t) P DM t 1 t 2 10-2 10-5 10-4 10-3 10-2 10-1 10 0 10 1 t 1, Square W ave Pulse Duration [sec] Figure 11. Transient Thermal Response Curve 2000 Fairchild Semiconductor International Rev. A1, January 2001
12V 200nF 50KΩ 300nF Gate Charge Test Circuit & Waveform Same Type as DUT 10V Q gs Q g Q gd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms R L 90% R G V DD 10V DUT 10% t d(on) t r t d(off) tf t on t off Unclamped Inductive Switching Test Circuit & Waveforms L 1 E AS = ---- 2 LI 2 AS BS -------------------- BS -V DD I D BS I AS R G V DD I D (t) 10V DUT V DD (t) t p t p Time 2000 Fairchild Semiconductor International Rev. A1, January 2001
Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + _ I SD L Driver R G Same Type as DUT V DD dv/dt controlled by RG I SD controlled by pulse period ( Driver ) Gate Pulse Width D = -------------------------- Gate Pulse Period 10V I FM, Body Diode Forward Current I SD ( DUT ) di/dt I RM Body Diode Reverse Current ( DUT ) Body Diode Recovery dv/dt V SD V DD Body Diode Forward Voltage Drop 2000 Fairchild Semiconductor International Rev. A1, January 2001
Package Dimensions (0.40) 9.90 ±0.20 D 2 PAK 4.50 ±0.20 1.30 +0.10 0.05 1.27 ±0.10 0.80 ±0.10 2.54 TYP 2.54 TYP 0.10 ±0.15 2.40 ±0.20 2.54 ±0.30 10.00 ±0.20 (8.00) (4.40) 10.00 ±0.20 15.30 ±0.30 (2XR0.45) 9.20 ±0.20 4.90 ±0.20 1.40 ±0.20 1.20 ±0.20 4.90 ±0.20 9.20 ±0.20 15.30 ±0.30 2.00 ±0.10 (0.75) 0 ~3 0.50 +0.10 0.05 (1.75) (7.20) 0.80 ±0.10 2000 Fairchild Semiconductor International Rev. A1, January 2001
Package Dimensions (Continued) (0.40) 9.90 ±0.20 I 2 PAK 4.50 ±0.20 1.30 +0.10 0.05 13.08 ±0.20 (0.94) (1.46) (45 ) 1.20 ±0.20 9.20 ±0.20 1.27 ±0.10 1.47 ±0.10 0.80 ±0.10 MAX 3.00 10.08 ±0.20 MAX13.40 2.54 TYP 2.54 TYP 0.50 +0.10 0.05 2.40 ±0.20 10.00 ±0.20 2000 Fairchild Semiconductor International Rev. A1, January 2001
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DOME E 2 CMOS EnSigna FACT FACT Quiet Series FAST FASTr GlobalOptoisolator GTO HiSeC ISOPLANAR MICROWIRE OPTOLOGIC OPTOPLANAR POP PowerTrench QFET QS QT Optoelectronics Quiet Series SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET TinyLogic UHC VCX DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. 2000 Fairchild Semiconductor International Rev. F1
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