Parallel DCMs APPLICATION NOTE AN:030. Introduction. Sample Circuit

APPLICATION NOTE AN:030 Parallel DCM Ugo Ghila Application Engineering Content Page Introduction 1 Sample Circuit 1 Output Voltage Regulation 2 Load Sharing 4 Startup 5 Special Application: Optimizing Current Sharing at High Temperature 6 Special Application: Non-equal Trim Level 6 Support Circuitry and PCB Layout 7 Concluion 9 Introduction The DC-DC Converter Module (DCM) operate on a high frequency, double-clamped zero voltage witching (DC-ZVS) topology, which provide a revolutionary increae in denity and efficiency compared to other complete DC-DC converter olution. The DCM encapulate iolation, regulation, thermal management, and fault monitoring in a ingle module. DCM are available in two different package: Converter houed in Package (ChiP) and Vicor Integrated Adapter (VIA) package. For more information on ChiP DCM capabilitie and option, pleae ee the application note "AN029: Single DCM a an Iolated, Regulated DC/DC Converter and the Vicor web page for DCM: www.vicorpower.com/dc-dc-converter-board-mount/dcm-dc-dc_converter. When an application call for more power than can be delivered by a ingle DCM, multiple DCM can be put in parallel. Thi application note dicue the parallel operation of ChiP DCM. Paralleling DCM i traightforward, ince the operation of each DCM in an array i nearly identical to that of a ingle DCM circuit (which i decribed in the DCM data heet and the application note AN029: Single DCM a an Iolated, Regulated DC/DC Converter). In a parallel circuit, each DCM operate on it own load line, baed on it hare of the load; in general, the effect of adding DCM in parallel i to remap that ame load line over a higher current range, with no derating. Current haring between DCM i automatically implemented. It i dependent on the individual DCM output etpoint and load line. Good load haring among DCM in an array i generally deired; however in mot cae, it not critical to accurately match the output etpoint, ince DCM are deigned to operate without damage even in the cae of a large haring imbalance. An example of maximum haring imbalance, between a DCM at full load and another DCM at minimum load i preented in thi document (ee ection: "Special Application: Non-equal Trim Level"). Depite not being required for operation, till it i better to optimize the current haring, becaue that reult in a more predictable aggregate load line and more equalized power diipation. Equalizing power haring acro all DCM alo mean that each DCM i operating at it lowet poible temperature, which reult in better efficiency. To achieve good current haring it i not neceary to have extremely accurate etpoint, ince the load line ha a bigger contribution to the output operating point v. load than a mall etpoint error; additionally, the DCM ha a built-in negative temperature coefficient (ee Output Voltage Regulation ection below) which help to further compenate for mall current haring imbalance. Sample Circuit An example of a circuit with four parallel DCM i hown in Figure 1. In thi circuit, the four DCM have different input voltage ource (all referenced to the ame IN). DCM have on-board protection for input overvoltage and overcurrent, o the fue F1-F4 hown in Figure 1 are only needed for application that mut pa afety approval, uch a CE Mark or UL60950. In that cae, note that each DCM need it own input fue. For more information on fue election and recommendation, ee the DCM data heet. Each DCM ha to ee at leat C OUT-MIN local to it output pin, before any output inductor (and therefore cloer to the DCM than to the junction of all DCM output). In array where all the DCM are alway tarted together, the array may have up to n* C OUT-MAX of total output capacitance (both local and bu capacitance). In array where DCM can be tarted individually, the total capacitance een by any DCM output (both local and bu capacitance) mut be equal or below the C OUT-MAX of a ingle DCM. See ection "Startup" and "Support Circuitry and PCB layout" for more information. AN:030 Page 1

For tability, to minimize ringing, and to provide optimal margin between the DCM rated input low line and it input undervoltage fault protection threhold (UVLO), the ource impedance of V IN mut be no more than half the combined effective input impedance of the DCM array. For example, for the DCM3623T50M17C2M00 at full output power (320W) and nominal efficiency (93%), the input power i 344W; at low line (16V) thi correpond to an equivalent input impedance of 0.744Ω (i.e. 162/344). For an array of four unit, the combined input impedance i 0.186Ω, and the ource impedance mut be no higher than 0.093Ω. If thi i not the cae, the input filter circuit mut compenate for the exceive impedance. A large electrolytic capacitor can be ued at each DCM' input: pecific information about filter deign for each DCM model i provided in it correponding data heet (ee Line Impedance, Input Slew rate and Input Stability Requirement in the dataheet). An additional ueful reource for filter deign i Vicor online filter deign tool, which can be found at the following link: http://app2.vicorpower.com/filterdeign/intifilter.do. For more information on component election, ee AN029: Single DCM a an Iolated, Regulated DC-DC Converter, and AN023: Filter Network Deign for VI Chip DC-DC Converter Module. Figure 1 Parallel DCM Circuit R TRIM DCM1 TR SW R1_1 EN FT V IN1 F1_1 L1_1 C1_1 +IN +OUT L2_1 CDCM_1 CLOAD Load -IN -OUT DCM2 TR EN R1_2 FT V IN2 F1_2 L1_2 C1_2 +IN +OUT L2_2 CDCM_2 -IN -OUT DCM4 TR EN R1_4 FT V IN4 F1_4 L1_4 C1_4 +IN +OUT L2_4 CDCM_4 R SERIES -IN -OUT R SHUNT Output Voltage Regulation A explained in the DCM data heet, the DCM provide a regulated output voltage around a load line that i 5.263% of the nominal voltage referenced to full load. Decreaing the load caue the output voltage to rie. Detail regarding DCM Load Line Slope and pecified value Specifying 5.263% at full load i the ame a pecifying the load line a having 5.0% of ome no-load voltage. For example, with a 24V nominal output DCM, V OUT_NO_LOAD = V OUT_FULL_LOAD (1 + 0.05263) V OUT_NO_LOAD = 24 (1 + 0.05263) = 25.26V In the other direction: V OUT_FULL_LOAD = V OUT_NO_LOAD (1-0.05) V OUT_FULL_LOAD = 25.26 (0.95) = 24V Since the marketed V OUT-NOM refer to the full load voltage, to keep the literature conitent, the 5.263% figure will be ued here. AN:030 Page 2

An example of an ideal V OUT v. I OUT plot for the DCM4623TD2H26F0T00 i hown in Figure 2, which i a modified verion of one of the DCM data heet figure (Figure 6 Ideal V OUT v. load current, at 25 C cae). Thi i an ideal plot becaue it doe not conider the contribution of light load booting, which i addreed eparately. Figure 2 Ideal V OUT v. I OUT Plot for DCM4623TD2H26F0T00 34 32 V OUT (V) 30 28 26 24 22 V OUT-LOAD = 1.26 V V OUT-LOAD = 1.26 V V OUT-LOAD = 1.26 V V OUT-LOAD = 1.26 V 20 V OUT-LOAD = 1.26 V 18 0 5 10 15 20 25 I OUT (A) Min Trim Low Trim High Trim Nom Trim Max Trim A hown in the figure, changing the trim value doen t affect the lope of the load line; the lope i till 5.263% of the nominal output voltage at full load, which for the model ued in thi example correpond to a V OUT-LOAD of 1.26V. The ame i true of change in temperature: voltage decreae with increaing temperature, but the lope of the output voltage tranfer function doen t change. (See Overall Output Voltage Tranfer Function in the DCM data heet.) If the equivalent erie reitance introduced by the DCM load line i needed, it can be calculated tarting from the load line equation given in the DCM dataheet, in the ection Nominal Output Voltage Load Line. For example, the load line equation for the DCM4623TD2H26F0X00 (with nominal trim) i: V OUT @ 25 = V OUT_FULL_LOAD + ΔV OUT-LOAD (1 - I OUT /I OUT_RATED ) Where: nv OUT_FULL_LOAD i the voltage at full load and nominal trim, nv OUT-LOAD i the rie of the ideal load line, ni OUT i the actual output current, and ni OUT_RATED i the rated output current in Amp (full load current). The equation above can be rewritten a: V OUT @ 25 = V OUT_FULL_LOAD + ΔV OUT-LOAD ΔV OUT-LOAD ( I OUT /I OUT_RATED ) Uing typical value: V OUT-LOAD = 1.26V V OUT_FULL_LOAD = 24.0V I OUT_RATED = 25.0A and combining term, V OUT @ 25 = 25.26 - (1.26/25.0) I OUT Where 25.26V i the ideal voltage at no load and nominal trim, which correpond to the 24.0V output at full load and nominal trim plu 1.26V for the load line. V OUT @ 25 = 25.26-0.0504 I OUT The equivalent erie reitance in Ohm introduced by the load line, V OUT-LOAD /I OUT (50.4mΩ in thi example), can be referred to a R INT_LOADLINE. AN:030 Page 3

Load Sharing The primary objective of paralleling DCM i to extend the loading capabilitie beyond that of a ingle DCM. See Figure 3 for an example. The figure how multiple DCM operating along the ame load line a a ingle DCM, but with the output current caled proportionally with the number of DCM in parallel. A implied in Figure 3, the failure of a ingle unit doen t necearily reult in the array being brought down, if the array i ized a N+1 redundant relative to the maximum load. A in other cae, haring i baed mainly on the load line and to a leer degree, the temperature coefficient, which i dicued next. Parallel unit with the ame output etpoint (i.e., ame trim value and ame temperature), ideally would have their load line perfectly overlap, and therefore their current haring would be perfect. In reality, there might be a mall difference in haring due to the output voltage etpoint accuracy, which could caue the real load line of each DCM to move lightly from the ideal etpoint. Thi would caue ome haring imbalance: that i, a unit with a lightly higher output voltage etpoint would contribute a little more to the output current than a unit with a lower output voltage etpoint. Inaccuracy in the etpoint repreent a mall contribution to the load line, o the reulting haring imbalance would be minor. Figure 3 Parallel DCM Behave Like a Single DCM with a Higher Output Current 34 32 3 Active DCM in Array 4 Active DCM in Array 34 32 V OUT (V) 30 28 ó 26 26 24.25 24.50 24 24 22 22 V OUT (V) 30 28 20 18 0 3 5 = 15 3 10 = 30 3 15 = 45 3 20 = 60 3 25 = 75 I OUT (A) Nom Trim 20 18 0 4 5 = 20 4 10 = 40 4 15 = 60 4 20 = 80 4 25 = 100 I OUT (A) Nom Trim The maximum etpoint accuracy pecified in the dataheet (%V OUT-ACCURACY, ±2% for mot model, -3% to +2% for ome pecial DCM) refer to the maximum variation of the etpoint over all poible operating condition (line, load, trim and temperature). The etpoint accuracy for nominal condition (nominal V IN, nominal trim, full load, 25 C) i ±0.5% V OUT_NOM (ee the minimum and maximum value for Output voltage etpoint in the dataheet Electrical Specification). Temperature ha a mall, beneficial effect on current haring. The DCM ha a negative voltagetemperature coefficient (ee Overall Output Voltage Tranfer Function in the data heet). If a unit i loaded more than other, it relative temperature tend to rie, which caue it output voltage to be reduced. Note that thi change in etpoint doe not affect the load line lope. Since the output voltage of the other parallel DCM match that of the loaded DCM, their output would follow their load line, increaing their hare of the load current and bringing the circuit back to equilibrium. DCM operate well in parallel, even if their trim etting are not all the ame. Unequal trim etting caue each DCM load line to tart at a different y-intercept (ee Figure 4); ince their output voltage are forced to be the ame value by the paralleled output connection, their current will be different when the circuit achieve balance. The voltage and current are maintained at thoe level uing the mechanim decribed above. From Figure 4, it can be een that etting the trim at different level between unit create a mimatch in current haring. AN:030 Page 4

Figure 4 Load Line of Parallel DCM Trimmed to Different Voltage Load Line DCM 3 DCM 1 DCM 2 Star ng VOUT, IOUT point VOUT (V) VOUT at equilibrium 20 30 40 50 60 70 80 % Rated Array I OUT Sharing improve at the upper limit of the output power range. Becaue of the finite accuracy of the output etpoint, the output voltage won t be identical (ee Figure 4) o a the output power increae, the DCM with the highet voltage will reach it maximum output current before the other. When that happen, it will operate a a contant current ource. (The DCM not in contant current will continue to regulate the output voltage). For either trim/haring cenario dicued above, the output ripple i typically reduced in a parallel DCM circuit compared to that of a ingle unit, becaue the DCM aren t ynchronized. That i, their witching period are not in phae, o the combined output of parallel DCM can behave like a ingle output with a higher effective witching frequency and lower ripple amplitude. In the bet cae, the witching period of N parallel DCM would be evenly taggered in time, o that the equivalent witching frequency would be N*f SW_STANDALONE. Since all DCM would contribute equally to maintaining the output voltage, the output ripple would be V OUT_RIPPLE_STANDALONE /N. In the wort cae cenario, all DCM would have the ame frequency and be in phae, uch that the equivalent witching frequency and total output ripple would be the ame a that of a ingle DCM. In a real-world ituation, the witching period are randomly ditributed, o the output ripple lie omewhere between the two extreme cae. Startup The tartup behavior of a DCM array depend on the type of load: reitive or contant current. For a reitive load, the load current increae a the DCM array output voltage rie. On tartup, DCM have a oft-tart ramp when operated alone; in an array, the DCM don t all turn on at the ame time, o there will be an additional component of the oft-tart ramp due to a ubet of DCM tarting before the other. Thi i mot notable when the DCM are tarted from the application of V IN, with a low input dv/dt. During the oft tart ramp, if the load current V OUT /R LOAD exceed the combined current limit (I OUT-LM ) of the active DCM, then thoe DCM go into current limit and the tartup ramp plateau to V OUT = R LOAD I OUT-LM (auming thi V OUT i above V OUT-UVP, the minimum current-limited V OUT, lited in the DCM dataheet). A additional DCM turn on and catch up to the firt group, they add current drive capability (that i, they increae the total current limit), and the output voltage increae to a higher level, given by the load reitance multiplied by the new total current limit. Thi continue until there are enough active DCM to provide the full load current at V OUT_NOM, allowing all DCM to exit from current-limited operation. With a contant current load, the load current remain the ame even if the DCM output voltage decreae. At tartup, a DCM ha a load current capability of I OUT-START, which i approximately 10% of the full load. If parallel DCM were tarted from the application of VIN and the load current exceeded the um of the current limit of the active DCM (I OUT-LM ), the active DCM would go into current limit, a in the cae for the reitive load. In thi cae, the DCM output voltage would drop, becaue the load current would be greater than the current limit, o the output voltage would collape. The higher the contant current etpoint of the load, the fater the DCM output voltage would collape. In ome extreme cenario, V OUT could collape when the firt DCM turned on, before additional DCM could tart driving the load. AN:030 Page 5

To prevent thi, the tartup delay between unit would have to be maller than the current limit delay; that i, the time from the firt to the lat DCM turning on would have to be horter than the time it would take the current limit of the firt DCM to kick in. Thi can be done by uing EN to tart the DCM. To ummarize, for contant current load, EN enure that the turn-on delay between DCM i maller than the current limit delay of one DCM. Special Application: Optimizing Current Sharing at High Temperature Optimizing the current haring between DCM equalize power diipation. While DCM till operate even when the load current i not balanced, equalizing power diipation lead to higher efficiency, ince generally peaking, efficiency i lightly reduced near the maximum operating temperature. There i an uncommon condition where good load haring acro an array i required for operation. Thi happen when the circuit operate at a temperature and power that are high enough to force the ue of the derating curve hown in Figure 25 of the data heet. In thee application, good current haring i important becaue a gro imbalance would increae the temperature of the overloaded part, which would decreae it maximum power. There are two cenario: nwhen operating at a temperature and power level that are far from the derating curve, a load imbalance caue a temperature difference, (which i partially compenated for by the temperature coefficient), but the maximum power doe not change. In thi cae, a loading imbalance doe not adverely affect the ytem. nwhen operating cloe to or at the derating curve, a load imbalance caue the temperature of the overloaded part to increae, which decreae the maximum power the unit can tolerate without triggering over-temperature protection (OTP). If the power being proceed by the unit i above the derated maximum power, the DCM in quetion will trigger OTP and hut down. The other unit have to compenate for the power drop caued by the unit hutting down, o their temperature increae, reducing their maximum output power that the remaining unit can tolerate without triggering OTP. Thi can lead to a domino effect that can potentially caue each DCM to trigger OTP and hut down one by one until the whole the ytem hut down. For thee application, good current haring i required. Special Application: Non-equal Trim Level Deliberately etting the programmed trim of DCM in an array to different level, (uch that ome unit reach their current limit long before other), could effectively be ued to extend the equivalent load line of the array over the entire array load rating. While thi i not a common application, it how how robut the DCM are, even under non-ideal condition. A an example, conider two unit in parallel, both with V OUT_NOM = 20V (at full load) and 10A maximum current each. A previouly explained, DCM have a built-in load line that i 5.263% of the nominal output voltage from full load to no load. For the unit in thi example, the load line would be 20*(0.05263) = 1.0526V (ee Figure 5). At nominal trim the DCM would how an output voltage of 20V at full load and 21.0526V at no load (excluding the poible contribution of light load booting, which i dicued eparately). For thee two DCM in parallel, with nominal trim, the contribution of the load line would go from 21.0526V at no load to 20V at full load (I MAX ). I MAX would be 20A, the um of the individual current. Thi example conider a implified ideal cenario where the current limit inception point i at 100% rated I OUT. In reality the current limit inception i variable baed on line and temperature condition; min, typ, and max value are provided in the DCM dataheet (Output current limit, page 5). If one unit, DCM1, i taken out of the parallel circuit (array) and it trim increaed to 21.0526V at full load, it load line would till be 1.0526V, but it would go from 21.0526V at full load to 22.1052V (21.0526V + 1.0526V) at no load (ee Figure 5). Putting thi DCM back into the original circuit, and increaing the load from the zero to the maximum, the nominally trimmed DCM (DCM2) would not contribute to driving the load until DCM1 reached an output voltage of 21.0526V. At that point, DCM1 would be at full load, while DCM2 would be at the highet etpoint of it load line (i.e. the point at the load line for which the unit output zero current). A the load i increaed, DCM1 would go in to current limit and DCM2 would tart driving the load, meaning that it would regulate the voltage baed on it own load line. With the load at 20A, DCM2 would alo be at full load and V OUT = 20V. The voltage from no load to the full load for the array would have gone from 22.1052V to 20V; the equivalent load line of the array would be almot 10% (i.e., almot double the load line of a ingle unit). AN:030 Page 6

Thi example i of little practical value, ince it negate many of the advantage of putting DCM in parallel, but it how that DCM would till function in a predictable manner even under thee extreme condition (a long a the cooling for the DCM atifie the limit in data heet Figure 25, maximum diipation veru cae temperature). Figure 5 Effect of Parallel DCM with Different Trim Set Point on Load Line 22.1052 V 21.0526 V DCM 1 DCM 2 21.0526 V 20 V 0A Output Current DCM 1 10A 0A Output Current DCM 2 10A DCM 1 & 2 22.1052 V 21.0526 V 20 V Current Limit DCM 1 Current Limit DCM 2 Output Current DCM 1 Output Current DCM 2 0A 10A 0A 10A 0A 10A 20A Output Current Array (DCM1 & DCM2) Current Limit Array (DCM1 & DCM2) I LOAD Support Circuitry and PCB Layout Matching the trace impedance of the DCM in an array in t critical in mot cae. From an output perpective, the DCM load line behave a a erie reitance which tend to trump any real erie reitive effect of the PCB, auming good deign practice are followed. Each DCM in an array hould have an output inductor placed after it local output capacitor. The inductor help uppre beat frequencie that can be generated with DCM interconnected output. In ome wort cae cenario, the circulating current among DCM output with no decoupling inductor can inadvertently trigger a fault protection mechanim. The inductor alo decouple each DCM and it local output capacitor from any bulk load capacitor a well a the local capacitor of other DCM in the array. Without the inductor, the total load capacitance would be limited to that which i within the C OUT-EXT range of a ingle DCM. A properly ized output inductor guarantee ufficient decoupling for the DCM to turn on within rated output capacitance even for the wort cae cenario of maximum turn on delay between the DCM in an array. Recommended output inductor value for each DCM model are provided in the DCM data heet under Array Operation. AN:030 Page 7

In addition, a explained in the DCM dataheet, an input decoupling network i needed to facilitate paralleling. Each DCM need a eparate input filter; additionally, for application that require common mode noie rejection on the input, a common mode choke hould be added to the input ide of each DCM. See Array Operation in the dataheet for recommended deign pecific component value for each DCM. The TR and the EN pin hould be equipped with low pa filter to avoid high frequency interference on the control ignal. Noie on TR might caue unwanted ocillation on the output voltage. Noie on EN might caue the DCM to turn off and on at unwanted time. When deigning a circuit to drive TR, it better not to load the pin with a capacitor, but to add a reitor (R2 in Figure 6) o that TR in t coupled to the capacitor directly, which could create a reonant tank between the capacitor, the lead inductance, and the internal bypa capacitor (which in t hown in Figure 6). The ame filter deign can be ued alo for EN (however R2 in thi cae i not required ince there i no internal reonant tank on EN). EN i a imple on/off input; each DCM ha a pull-up reitor R ENABLE-INT, which i approximately 10kΩ (for an array with N DCM in parallel, the internal pull-up reitor will be in parallel a well, lowering the equivalent pull-up reitance of TR an EN for the array to 10kΩ/N). The value of R1 and R2 need to be uch that the voltage on EN i le than the pecified minimum of V ENABLE DIS = 0.99V, keeping in mind that if one filter circuit i ued for all of the EN pin, the pull-up reitor of the DCM would be in parallel, o R1 and R2 would have to be choen accordingly. Calculating the reitor value for TR i a bit more complicated, ince the pin voltage i much more critical. The eaiet olution i to meaure the trim pin voltage VTR directly and et the value of V o that VTR i correct. If one filter i ued for all DCM in parallel, the value of R1 and R2 need to be choen for the parallel combination of pull-up reitor. Figure 6 Filter Circuit for EN or TR Pin DCM V CC V S R1 R2 EN or TR 10 k/n -IN The DCM powertrain witching noie frequency i ignificantly higher than the trim update frequency, o the filter doe not need to be finely tuned or very accurate. The trim bandwidth i around 30Hz, while primary ource of noie i the witching of the main powertrain, often cloe to 1MHz depending on the DCM model. A low pa filter with a cutoff frequency of le than 1kHz would introduce ufficient attenuation to help avoid any rik of interference from witching noie, with jut a imple 1t order filter network. FT pin can be directly bued (a previouly hown in Figure 1) becaue of the open-drain tructure. When the array i operating normally and no fault i preent, FT i pulled up to 3.3V and the aggregate pull-up reitance of FT i 499kΩ/N, o an external pull-down (R SHUNT of Figure 1) need to overcome that combined pull-up. The pull-down value hould be ized to allow the external fault detection ub-circuit to robutly reolve the normal operating mode tatu veru a faulted tate. A fault condition could affect all, or jut one DCM, o the total drive high current mut till be limited to the 4mA of a ingle DCM (the current limit i determined by the value of value of R SERIES previouly hown in Figure 1). AN:030 Page 8

Concluion Parallel DCM have many benefit: increaed current, redundancy, and increaed reliability - all with no derating. The theory of operation i primarily an extenion of the operation of a ingle unit, with ome additional conideration to be ure that current haring i optimized, o that the circuit achieve maximum efficiency. AN:030 Page 9

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