Features l Advanced Process Technology l Ultra Low On-Resistance l 75 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax Description Specifically designed for Industrial applications, this HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Industrial applications and a wide variety of other applications. G PD - 9775B IRLR3ZPbF IRLU3ZPbF HEXFET Power MOSFET D S D-Pak IRLR3ZPbF V DSS = V R DS(on) = 4mΩ I-Pak IRLU3ZPbF Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon Limited) 63 I D @ T C = C Continuous Drain Current, V GS @ V (Silicon Limited) 45 A I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package Limited) 42 I DM Pulsed Drain Current c 250 P D @T C = 25 C Power Dissipation 40 W Linear Derating Factor 0.95 W/ C V GS Gate-to-Source Voltage ±6 V E AS (Thermally limited) Single Pulse Avalanche Energyd mj E AS (Tested ) Single Pulse Avalanche Energy Tested Value h 40 I AR Avalanche Currentc See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy g mj T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Reflow Soldering Temperature, for seconds Mounting Torque, 6-32 or M3 screw Thermal Resistance 300 lbfyin (.Nym) Parameter Typ. Max. Units R θjc Junction-to-Case j.05 R θja Junction-to-Ambient (PCB mount) ij 40 C/W R θja Junction-to-Ambient j HEXFET is a registered trademark of International Rectifier. www.irf.com /30/09
IRLR/U3ZPbF Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units V (BR)DSS Drain-to-Source Breakdown Voltage V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient 0.077 V/ C R DS(on) Static Drain-to-Source On-Resistance 4 mω 2 6 V GS(th) Gate Threshold Voltage.0 2.5 V gfs Forward Transconductance 52 S I DSS Drain-to-Source Leakage Current 20 µa 250 I GSS Gate-to-Source Forward Leakage 200 na Gate-to-Source Reverse Leakage -200 Q g Total Gate Charge 34 48 Q gs Gate-to-Source Charge nc Q gd Gate-to-Drain ("Miller") Charge 5 t d(on) Turn-On Delay Time 24 t r Rise Time t d(off) Turn-Off Delay Time 33 ns t f Fall Time 48 Conditions V GS = 0V, I D = 250µA Reference to 25 C, I D = ma V GS = V, I D = 38A e V GS = 4.5V, I D = 32A e V DS = V GS, I D = µa V DS = 25V, I D = 38A V DS = V, V GS = 0V V DS = V, V GS = 0V, T J = 25 C V GS = 6V V GS = -6V I D = 38A V DS = 50V V GS = 4.5V e V DD = 50V I D = 38A R G = 3.7Ω V GS = 4.5V e L D Internal Drain Inductance 4.5 Between lead, D nh 6mm (0.25in.) G L S Internal Source Inductance 7.5 from package and center of die contact S C iss Input Capacitance 3980 V GS = 0V C oss Output Capacitance 3 V DS = 25V C rss Reverse Transfer Capacitance 30 pf ƒ =.0MHz C oss Output Capacitance 820 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 70 V GS = 0V, V DS = 80V, ƒ =.0MHz C oss eff. Effective Output Capacitance 320 V GS = 0V, V DS = 0V to 80V f Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current 63 MOSFET symbol D (Body Diode) A showing the I SM Pulsed Source Current 250 integral reverse G (Body Diode)Ãc p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 38A, V GS = 0V e t rr Reverse Recovery Time 34 5 ns T J = 25 C, I F = 38A, V DD = 50V Q rr Reverse Recovery Charge 42 63 nc di/dt = A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2 www.irf.com
I D, Drain-to-Source Current (Α) G fs, Forward Transconductance (S) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) IRLR/U3ZPbF 0 VGS TOP 5V V 8.0V 4.5V 3.5V 3.0V 2.7V BOTTOM 2.5V 0 VGS TOP 5V V 8.0V 4.5V 3.5V 3.0V 2.7V BOTTOM 2.5V 0. 2.5V 60µs PULSE WIDTH Tj = 25 C 0.0 0. 0 V DS, Drain-to-Source Voltage (V) 2.5V 60µs PULSE WIDTH Tj = 75 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 50 T J = 75 C 25 T J = 25 C 75 T J = 75 C T J = 25 C 50 0. V DS = 25V 60µs PULSE WIDTH 0 2 4 6 8 2 4 6 25 0 V DS = V 300µs PULSE WIDTH 0 25 50 75 V GS, Gate-to-Source Voltage (V) I D,Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3
I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRLR/U3ZPbF 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED 5.0 I D = 38A 00 C rss = C gd C oss = C ds C gd C iss 4.0 3.0 V DS = 80V V DS = 50V 0 C oss C rss 2.0.0 0.0 0 20 30 40 V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 0 OPERATION IN THIS AREA LIMITED BY R DS (on) T J = 75 C µsec T J = 25 C msec V GS = 0V 0. 0.0 0.2 0.4 0.6 0.8.0.2.4.6.8 V SD, Source-to-Drain Voltage (V) Tc = 25 C Tj = 75 C Single Pulse msec DC 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
I D, Drain Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) IRLR/U3ZPbF 70 60 Limited By Package 3.0 2.5 I D = 63A V GS = V 50 40 2.0 30 20.5.0 0 25 50 75 25 50 75 T C, Case Temperature ( C) 0.5-60 -40-20 0 20 40 60 80 20406080 T J, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Normalized On-Resistance vs. Temperature D = 0.50 Thermal Response ( Z thjc ) 0. 0.0 0.00 0.20 0. 0.05 0.02 0.0 SINGLE PULSE ( THERMAL RESPONSE ) R R 2 R R 2 τ J τ J τ τ τ 2 τ 2 Ci= τi/ri Ci i Ri E-006 E-005 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) τ C τ Ri ( C/W) τi (sec) 0.383 0.000267 0.667 0.00396 Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th) Gate threshold Voltage (V) E AS, Single Pulse Avalanche Energy (mj) IRLR/U3ZPbF R G V DS 20V V GS tp L D.U.T IAS 0.0Ω 5V DRIVER - V DD A 300 250 200 50 I D TOP 4.4A 6.5A BOTTOM 38A Fig 2a. Unclamped Inductive Test Circuit tp V (BR)DSS 50 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy vs. Drain Current V Q GS Q GD 3.0 V G 2.5 Charge Fig 3a. Basic Gate Charge Waveform L VCC DUT 0 K 2.0.5 I D = µa I D = 250µA.0 I D =.0mA I D =.0A 0.5 0.0-75 -50-25 0 25 50 75 25 50 75 200 T J, Temperature ( C ) Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage vs. Temperature 6 www.irf.com
E AR, Avalanche Energy (mj) Avalanche Current (A) IRLR/U3ZPbF Duty Cycle = Single Pulse 0.0 0.05 0. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 50 C and Tstart =25 C (Single Pulse) Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τ j = 25 C and Tstart = 50 C. 0..0E-06.0E-05.0E-04.0E-03.0E-02.0E-0 tav (sec) Fig 5. Typical Avalanche Current vs.pulsewidth 50 25 75 50 25 TOP Single Pulse BOTTOM % Duty Cycle I D = 38A 0 25 50 75 25 50 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2DT/ [.3 BV Z th ] vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRLR/U3ZPbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Pulse Width µs Duty Factor 0. % Fig 8a. Switching Time Test Circuit V DS 90% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8 www.irf.com
D-Pak (TO-252AA) Package Outline IRLR/U3ZPbF D-Pak (TO-252AA) Part Marking Information (;$03/( 7,6,6$,5)5 :,7$66(0%/< /27&2'( $66(0%/('2::,7($66(0%/</,($ RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'(,5)5 $ 3$5780%(5 '$7(&2'( <($5 :((. /,($ 25,7(5$7,2$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'(,5)5 3$5780%(5 '$7(&2'( 3 '(6,*$7(6/($')5(( 352'8&7237,2$/ <($5 :((. $ $66(0%/<6,7(&2'( Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRLR/U3ZPbF I-Pak (TO-25AA) Package Outline I-Pak (TO-25AA) Part Marking Information @Y6HQG@) UCDTDT6IDSAV! XDUC6TT@H7G` GPU8P9@$%&' 6TT@H7G@9PIXX (! DIUC@6TT@H7G`GDI@6 I r)qv h r iy yv rƒ v v v qvph r GrhqA rr DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPU8P9@,5)8 $ Q6SUIVH7@S 96U@8P9@ `@6S 2! X@@F ( GDI@6 25 DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G` GPU8P9@,5)8 Q6SUIVH7@S 96U@8P9@ Q29@TDBI6U@TG@69AS@@ QSP9V8UPQUDPI6G `@6S 2! X@@F ( 626TT@H7G`TDU@8P9@ Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com
IRLR/U3ZPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. 6 mm Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L = 0.6mH R G = 25Ω, I AS = 38A, V GS =V. Part not recommended for use above this value. ƒ Pulse width.0ms; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. This value determined from sample failure population. % tested to this value in production. When mounted on " square PCB (FR-4 or G- Material). ˆ R θ is measured at T J approximately 90 C. Data and specifications subject to change without notice. This product has been designed for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information./09 www.irf.com