PD -95487A Typical Applications l Industrial Motor Drive Benefits l Ultra Low On-Resistance l Dynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This Stripe Planar design of HEXFET Power MOSFETs utilizes the lastest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. G IRF67PbF HEXFET Power MOSFET D S TO-22AB V DSS = 75V R DS(on) =.75Ω I D = 42A Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 42 I D @ T C = C Continuous Drain Current, V GS @ V A I DM Pulsed Drain Current 57 P D @T C = 25 C Power Dissipation 38 W Linear Derating Factor 2.5 W/ C V GS Gate-to-Source Voltage ± 2 V E AS Single Pulse Avalanche Energy 25 mj I AR Avalanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy mj dv/dt Peak Diode Recovery dv/dt ƒ 5.2 V/ns T J Operating Junction and -55 to 75 T STG Storage Temperature Range C Soldering Temperature, for seconds 3 (.6mm from case ) Mounting Torque, 6-32 or M3 screw lbf in (.N m) Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.4 R θcs Case-to-Sink, Flat, Greased Surface.5 C/W R θja Junction-to-Ambient 62 www.irf.com 9/22/
IRF67PbF Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 75 V V GS = V, I D = 25µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient.86 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance.58.75 Ω V GS = V, I D = 85A V GS(th) Gate Threshold Voltage 2. 4. V V DS = V, I D = 25µA g fs Forward Transconductance 79 S V DS = 25V, I D = 85A I DSS Drain-to-Source Leakage Current 2 V µa DS = 75V, V GS = V 25 V DS = 6V, V GS = V, T J = 5 C I GSS Gate-to-Source Forward Leakage 2 V GS = 2V na Gate-to-Source Reverse Leakage -2 V GS = -2V Q g Total Gate Charge 2 32 I D = 85A Q gs Gate-to-Source Charge 45 68 nc V DS = 6V Q gd Gate-to-Drain ("Miller") Charge 73 V GS = V t d(on) Turn-On Delay Time 22 V DD = 38V t r Rise Time 3 I D = 85A ns t d(off) Turn-Off Delay Time 84 R G =.8Ω t f Fall Time 86 V GS = V Between lead, D L D Internal Drain Inductance 4.5 6mm (.25in.) nh G from package L S Internal Source Inductance 7.5 and center of die contact S C iss Input Capacitance 775 V GS = V C oss Output Capacitance 23 pf V DS = 25V C rss Reverse Transfer Capacitance 3 ƒ =.MHz, See Fig. 5 C oss Output Capacitance 577 V GS = V, V DS =.V, ƒ =.MHz C oss Output Capacitance 79 V GS = V, V DS = 6V, ƒ =.MHz C oss eff. Effective Output Capacitance 42 V GS = V, V DS = V to 6V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 42 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 57 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 85A, V GS = V t rr Reverse Recovery Time 3 2 ns T J = 25 C, I F = 85A Q rr Reverse RecoveryCharge 69 4 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Starting T J = 25 C, L =.2mH R G = 25Ω, I AS = 85A, V GS =V (See Figure 2). ƒ I SD 85A, di/dt 3A/µs, V DD V (BR)DSS, T J 75 C Pulse width 4µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. 2 www.irf.com
I D, Drain-to-Source Current (A) IRF67PbF VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 2µs PULSE WIDTH Tj = 25 C. V DS, Drain-to-Source Voltage (V) I D, Drain-to-Source Current (A) VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V 4.5V 2µs PULSE WIDTH T J = 75 C. V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) T J = 75 C T J = 25 C V DS= 25V 2µs PULSE WIDTH 4. 5. 6. 7. 8. 9.. V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3. I D = 42A 2.5 2..5..5 V GS = V. -6-4 -2 2 4 6 8 2 4 6 8 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) IRF67PbF 2 8 6 4 2 Ciss Coss Crss V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 2 6 2 8 4 I = D 85A V DS = 6V V DS = 37V V DS = 5V FOR TEST CIRCUIT SEE FIGURE 3 2 3 4 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) T J = 75 C T J = 25 C V GS = V..2.6..4.8 2.2 V SD,Source-to-Drain Voltage (V) Tc = 25 C Tj = 75 C Single Pulse OPERATION IN THIS AREA LIMITED BY R DS (on) µsec msec msec V DS, Drain-toSource Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
IRF67PbF 6 LIMITED BY PACKAGE V DS R D I D, Drain Current (A) 2 8 4 25 5 75 25 5 75 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 9% R G V GS V Pulse Width µs Duty Factor. % D.U.T. Fig a. Switching Time Test Circuit % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms - V DD Thermal Response (Z thjc ).. D =.5.2..5.2. SINGLE PULSE (THERMAL RESPONSE) Notes:. Duty factor D = t / t 2. 2. Peak T J = P DM x Z thjc TC..... t, Rectangular Pulse Duration (sec) PDM t t2 Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th) Gate threshold Voltage (V) IRF67PbF R G V DS 2V V GS tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T IAS.Ω V (BR)DSS 5V DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 3 25 2 5 5 TOP BOTTOM I D 35A 6A 85A 25 5 75 25 5 75 Starting T, Junction Temperature ( J C) I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy Vs. Drain Current V Q GS Q GD 5. V G 4. Current Regulator Same Type as D.U.T. Charge Fig 3a. Basic Gate Charge Waveform 3. I D = 25µA 2V.2µF 5KΩ.3µF 2. V GS D.U.T. V - DS. -75-5 -25 25 5 75 25 5 75 2 3mA T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage Vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRF67PbF Duty Cycle = Single Pulse..5. Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses.e-7.e-6.e-5.e-4.e-3.e-2.e- tav (sec) Fig 5. Typical Avalanche Current Vs.Pulsewidth 4 2 8 6 4 2 TOP Single Pulse BOTTOM % Duty Cycle I D = 85A 25 5 75 25 5 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-5 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2DT/ [.3 BV Z th ] Vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRF67PbF Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - V GS R G dv/dt controlled by R G I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Polarity of D.U.T for P-Channel Driver Gate Drive Period P.W. D = P.W. Period [ V GS =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Applied Voltage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Ripple 5% Forward Drop [ V DD ] [ ] I SD *** V GS = 5.V for Logic Level and 3V Drive Devices Fig 7. For N-channel HEXFET power MOSFETs 8 www.irf.com
IRF67PbF TO-22AB Package Outline Dimensions are shown in millimeters (inches) TO-22AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 789 ASSEMBLED ON WW 9, 997 IN THE ASSEMBLY LINE "C" Note: "P" inassembly line position indicates "Lead - Free" INTERNATIONAL RECTIFIER LOGO AS S E MB L Y LOT CODE PART NUMBER DATE CODE YEAR 7 = 997 WEEK 9 LINE C TO-22AB packages are not recommended for Surface Mount Application. Notes:. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) 252-75 TAC Fax: (3) 252-793 Visit us at www.irf.com for sales contact information. 9/2 www.irf.com 9