Low-voltage, High-precision Bandgap Current Reference Circuit

Low-voltage, High-precision Bandgap Current Reference Circuit Chong Wei Keat, Harikrishnan Ramiah and Jeevan Kanesan Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia ABSTRACT A low-voltage, low-power current-mode bandgap reference is designed and simulated in standard 0.13 µm CMOS technology on the Spectre platform. The proposed current-mode bandgap reference has a simulated temperature coefficient of 47.15 ppm/ C over the temperature range of -40 C to 140 C, with the corresponding current consumption of 42.06 µa complying with the specified temperature range. It could be operated down to 1.0 V of supply voltage headroom, while consuming 300 µw of power. Keywords: Bandgap reference, CTAT, Current-mode, Error amplifier, PTAT. 1. INTRODUCTION Bandgap reference circuit is one of the essential components in many circuits such as data converters, voltage regulators, flash memory circuits, and RF circuits interface [1,2]. The precision biasing and temperature stability of the reference voltage directly determine the accuracy of these applications [3]. Hence, a bandgap reference with little dependence on supply, temperature variations, and also process variation become increasingly important in current commercial products. The first bandgap voltage reference, proposed by Widlar [4] and followed by Kuijk [5], are the commonly adopted circuit design, due to its predictable reference voltage and low temperature dependence. The fundamental idea of bandgap voltage reference proposed by Widlar is to compensate the negative temperature coefficient (CTAT) of Base-Emitter voltage in BJT by adding a second voltage with positive temperature coefficient (PTAT). By cancelling off the CTAT voltage and PTAT voltage, a fixed DC voltage with low temperature sensitivity is generated. The continuous downscaling of the evolving deepsubmicron CMOS technologies proportionally scales the voltage headroom up to 1.2 V and below. The conventional bandgap reference is not suitable to be realized in these technologies since the conventional bandgap reference provides an output voltage almost equal to the silicon bandgap voltage ( 1.2 ev) [4]. Therefore, current-mode bandgap reference is designed as it can provide an output reference which is lower than silicon bandgap voltage. In this paper, the design and simulation results of a low-power current-mode bandgap reference circuit is presented and reviewed. The rest of the paper is organized as follow. In Section 2, the basic concepts of the bandgap reference are outlined. Section 3 details the proposed bandgap reference circuit with the integrated error amplifier. In Section 4, a simulation result of the bandgap reference and amplifier is presented. And, finally, the conclusion is drawn in Section 5. 2. CONVENTIONAL VOLTAGE REFERENCE CONCEPT The forward voltage of a pn-junction diode, as in the case of the emitter voltage of a bipolar transistor, exhibits a negative temperature coefficient. For a bipolar device, the saturation current I S is proportional to mktn 2 i, where m is the mobility of minority carriers, k is Boltzmann constant given by 1.3807 x 10-23 JK -1 and n i is the intrinsic minority carrier concentration of the silicon. The temperature dependence of these quantities 2 3 is represented as ni T exp Eg ( kt) and µ µ 0 T m, where, E g =1.12 ev is the bandgap energy of silicon and m = -3/2. Simplifying the analysis, and assuming that I C is held constant, the temperature coefficient of a baseemitter voltage is given as: V T ( ) V 4 + m V E q = T BE BE T g Equation (1) proves that the temperature coefficient of base-emitter voltage is dependent on the magnitude of V BE at the corresponding temperature. Note that the reference value generation will not be constant across the temperature variation if the positive temperature coefficient quantity is a constant instead. A positive temperature coefficient can be obtained if two bipolar transistors operate at an unequal current density (1) IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 NOV-DEC 2012 501

and the difference between their base-emitter voltages is directly proportional to the absolute temperature (PTAT), as shown in Figure 1. The two identical transistors, Q 1 and Q 2, with same saturation current (I S1= I S2 ) are biased at emitter current of ni and I, respectively, and their base currents are negligible, then V = V V BE BE 1 BE 2 Figure 1: Generation of PTAT voltage. = V T ni ln I V I ln I T S1 S2 (2) = V ( n) T ln 3. DESIGN WITH CURRENT-MODE 3.1 Current-mode Bandgap Reference Design The implementation of a conventional voltage bandgap reference is drowning to several design limitation. Due to the process scaling, supply voltage is one of the limiting factor as the headroom is limited to 1.2 V in 0.13 µm CMOS technology and the supply voltage expected to further scale down proportionally to the technology evolution in the sub-micron CMOS technology, thus favoring to the current-mode bandgap reference realization. Vertical p-n-p BJT is substituted by p-n junction diodes. The p-n diodes are preferably adopted in low-voltage design, with a penalty of increased incurred cost, large area consumption, and the need for accurate models of nonstandard devices [6]. In Figure 2, diode D 1 and D 2 are used to replace the BJT vertically as in the conventional bandgap reference design for low-voltage design. Transistors M 5, M 6, and M 7 act as the PMOS cascode in which they are implemented to isolate the bandgap reference from the noisy power supply [7], and thus improving the power supply rejection ratio (PSRR). Transistors M 3 and M 8 are stacked together to realize the totem pole bias configuration. Totem pole voltage source works like batteries, their values remain constant since there are no current leakages at the node while it can be used to define a series of bias voltage between the positive and the negative supply voltage. Therefore, it is configured to generate a constant voltage source for biasing of the cascode transistors M 5, M 6, and M 7. Voltage nodes V X and V Y are compensated to be equal by an error amplifier, which require a high gain error compensation to achieve this requirement. Since resistance R 1 is the same as R 2, I R1 is equal to I R2. Since the current in M 1 and M 2 are equal, I D1 is equal to I R3. Voltage drop across R 3 can be expressed as: V kt N q ln (3) R3 = ( ) Figure 2: Low-voltage current-mode bandgap reference with PMOS cascode. where, N is the ratio of the diode pair. The current in M2 is given by: I M 2 1 kt VX = N R ( ) ln q + (4) R 3 2 where, V X is the voltage drop of diode D 1. From equation (4), the first part of equation is PTAT expression, while second part is CTAT cancellation. By choosing an appropriate value for R 2, R 3, and N, the CTAT voltage will cancel off the PTAT voltage and a fixed DC voltage independent of temperature variation is generated. The current in M 4 is mirrored from M 2. As the resistor R 4 has low temperature coefficient, the voltage drop across it will generate V REF with low temperature sensitivity. V I R REF = REF 4 = 1 kt ( ) + V X ln N 4 R3 q R R (5) 2 502 IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 nov-dec 2012

3.2 Error Amplifier As offset compensation circuit, the amplifier will influence the overall system performance. The folded cascode amplifier is suitable for fast settling and wide band operational amplifier design. However, large numbers of external biasing circuit integration are needed in the amplifier circuit which will cause power overhead, additional parasitic components, which subjects the bias line to noise and cross talk due to high sensitivity of the bias. To maximize the performance, all the active devices in amplifier should be properly biased. Therefore, a self-bias folded cascode amplifier is integrated. This technique eliminates the need of external biasing circuitry by generating bias voltages from the internal nodes of the circuit. Figure 3 shows the self-biased folded cascode amplifier. Transistor M 4, M 5, M 12 and M 10, M 11, M 13 forms a set of current mirror with voltage level shifting. This configuration is known as the Rajput-Jamuar level shifted current mirror [8]. Transistor M 12 is biased in a moderate inversion region and it serves the purpose of fixing the drain voltage of M 4. Drain current of transistor M 4 fixes the value of V GS4 and thus the voltage at source terminal of M 12 is defined. Since drain current of transistor M 12 is known, V GS12 is also fixed. V = V V (6) DS4 GS4 GS12 This topology enables a low-voltage architecture. To achieve a high gain amplifier, gain boosting technique is adopted. Gain boosters are implemented at the altering biasing point of the transistor M 6, M 7, M 8, and M 9. Negative feedback loop drives the gate of M 7 till voltage V B and V A are the same value. Therefore, the variation of V OUT has less sensitivity on V B. The output impedance increases as: Rout = APgm ro ro ANgm ro r (7) 7 5 7 9 9 o11 An increase of the output resistance will improve the overall gain and the corresponding low frequency gain can be expressed as: AV = gm2rout = gm ( APgm ro ro ANgm ro ro ) 2 7 5 7 9 9 11 (8) where, A P is the gain of P-type gain booster A N is the gain of N-type gain booster Alternately, that the current mirror as described in Figure 3 comprising the transistor M 4, M 5, M 6, M 7, M 8, M 9, M 10, and M 11 serves as the output stage, collectively working as a summing circuit and provides biasing Figure 3: Self-biased folded cascade op-amp with gain boosters. for the constant current sources. The gate bias of the transistor M 3 forms a feedback path and there are no signal coming through because of the diode connected transistors M 12, M 13 and the two nodes at drain terminal of M 4, M 10 are attenuated. Hence, all the performances, except the transient response, are equivalent between the externally biased and self-biased architecture. As the amplifier is adopted as an offset cancellation architecture, the transient performance is not a concern of validation. Alternately, that the current mirror as described in Figure 3 comprising the transistor M4, M5, M6, M7, M8, M9, M10, and M11 serves as the output stage, collectively working as a summing circuit and provides biasing for the constant current sources. The gate bias of the transistor M3 forms a feedback path and there are no signal coming through because of the diodeconnected transistors M12, M13 and the two nodes at drain terminal of M4, M10 are attenuated. Hence, all the performances, except the transient response, are equivalent between the externally biased and self-biased architecture. As the amplifier is adopted as an offset cancellation architecture the transient performance is not a concern of validation. Figure 4a and b illustrate the N-type and P-type gain booster circuits, respectively. Transistor M 4 M 7 and M 8 M 11 assembles the n-type and p-type wide-swing cascode current mirrors, respectively. At the same IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 NOV-DEC 2012 503

(a) Figure 4: (a) N-type gain booster, (b) P-type gain booster. (b) time, the transistors are complementarily self-biased in a negative feedback-loop mode. The operating point of the self-biased amplifier has low sensitivity with the process and temperature variations, as the biasing point in this topology is dependent on the size ratio of the stacked transistors. Only two power rails, VDD and GND, are needed and all the external biasing circuits can be removed in this self-biased topology. Thus, the power consumption can be significantly reduced. The small signal output resistance, R out, looking into drain terminal of M 7 and M 9, can be expressed as: Rout = gm ro ro gm ro r (9) 7 5 7 9 9 o11 The dc gain of the gain booster is given by: Figure 5: Simulated current reference vs Temperature with different process variation. AV = gm2rout = gm ( gm ro ro gm ro ro ) 2 7 5 7 9 9 11 (10) 4. SIMULATION RESULTS The precision biasing circuit in Figure 2 is simulated in 0.13 µm standard CMOS process on the Cadence Spectre platform. The output PTAT and CTAT currents are adjusted to a lower range resulting in the reduction of the total power consumption in the bandgap reference circuit. PTAT current is obtained from resistor R 3 while CTAT current is obtained from resistor R 2. The I REF is observed over a temperature span of -40 C to 140 C with respect to process variation and is reported in Figure 5. The simulated output current reference is 42.06 µa at 27 C in typical process. The desired output reference voltage can be obtained by adjusting the resistance value of R 4. The variation of the simulated output current is 0.357 µa over the temperature range of -40 C to 140 C. The average temperature coefficient is calculated to Figure 6: PSRR of bandgap reference with cascade transistor. be 47.15 ppm/ C. The total power consumption of the current-mode bandgap reference is 300 µw. The variation of PSRR is described in Figure 6. Due to the integration of PMOS cascoding topology, greater PSRR 504 IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 nov-dec 2012

Table 1: Simulated performance summary Performance Value Supply voltage (V) 1.2 DC gain of error amplifier (db) 102.78 Output current reference (µa) 42.06 PSRR (a) 1 Hz 82.53 (b) 1 MHz 49.12 Phase margin (degree) 87.8 Temperature coefficient (ppm/ C) 47.15 Power consumption (µw) 299.38 Technology (µm) 0.13 Figure 7: Simulated current reference vs supply voltage variation. 5. CONCLUSION A low-power, high PSRR current-mode bandgap reference is designed and simulated in 0.13 μm standard CMOS technology. The bandgap reference circuit integrates offset cancellation operational amplifier at the PTAT input and is measured over a wide temperature range of -40 C to 140 C. An output current reference of 42.06 µa is generated and the temperature coefficient is simulated to be 47.15 ppm/ C. High PSRR is achieved by integrating PMOS cascoding topology to isolate the circuit from noisy power supply. The PSRR is simulated to be 82.53 db at low frequency and 49.122 db at 1 MHz. The circuit consumes 300 µw and operates down to a minimum power supply voltage of 1.0 V. REFERENCES Figure 8: Simulated gain for proposed folded cascode op-amp. of 80 db at low frequency and around 50 db at 1 MHz of offset is achieved. The simulated reference current with the 20% headroom variation at 27 C is reported in Figure 7. Considering the tolerances affecting the devices, the proposed current-mode bandgap reference consumes a minimum supply headroom of 1.0 V. Reference to the proposed amplifier illustrated in Figure 3, the corresponding gain is plotted in Figure 8. The DC gain of the proposed amplifier should be high enough (102.78 db) to ensure the voltage at nodes X and Y are equal in the offset cancellation. The simulated phase margin of proposed current-mode bandgap reference is 87.8 which ensures the stability of operation. The simulated performances of the proposed circuit are summarized in Table 1. 1. G Yu and X Zou, A high precision CMOS current-mode band-gap voltage reference in IEEE International Conference on Solid- State and Integrated Circuit Technology, Shanghai, pp. 1736-8, Oct. 2006. 2. GA Rincon-Mora, and PE Allen, A 1.1-V current-mode and piecewiselinear curvature-corrected bandgap reference, IEEE J. Solid-State Circuits, Vol. 33, pp. 1551-4, Oct. 1998. 3. B Song and PR Gray, A precision curvature-compensated CMOS bandgap reference, IEEE J. Solid-State Circuits, Vol. 18, pp. 634-43, Dec. 1983. 4. RJ Widlar, New developments in IC voltage regulators, IEEE J. Solid- State Circuits, Vol. 6, pp. 2-7, Feb. 1971. 5. KE Kuijk, A precision reference voltage source, IEEE J. Solid-State Circuits, Vol. 8, pp. 222-6, June. 1973. 6. A Boni, Op-amps and startup circuits for CMOS bandgap references with near 1-V supply, IEEE J. Solid-State Circuits, Vol. 37, pp. 1339-43, Oct. 2002. 7. C Lee, K McClellan and J Choma Jr, A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter, IEEE J. Solid-State Circuits, Vol. 36, pp. 1453-63, Oct. 2001 8. SS Rajput and SS Jamuar, Advanced current mirrors for low voltage analog designs in IEEE International Conference on Semiconductor Electronics, Kuala Lumpur, pp. 258-63, Dec. 2004, IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 NOV-DEC 2012 505

AUTHORS Chong Wei Keat received the B.S. degree in electronic engineering from University Malaysia Perlis, Malaysia, in 2008. Currently he is working towards the M.S degree in the University of Malaya, Kuala Lumpur, Malaysia. His current research interest includes analogue and Radio Frequency Integrated Circuit Design. E-mail: wkchong2008@gmail.com Harikrishnan Ramiah received the B.E., M.S. and Ph.D. degrees in electrical and electronics engineering, majoring in analogue and digital IC design from University Science Malaysia, Penang, Malaysia, in 2000, 2003 and 2009, respectively. In the year 2003, he was with SiresLabs Sdn. Bhd, CyberJaya, Malaysia, working on audio pre-amplifier for MEMs ASIC application and the design of 10Gbps optical transceiver solution. In year 2002 he was with Intel Technology Sdn. Bhd., Penang, Malaysia performing high frequency signal integrity analysis for high speed digital data transmission and developing Matlab spread sheet for Eye diagram generation, to evaluate signal response for FCBGA and FCMMAP packages. Currently, he is a Senior Lecturer in the Department of Electrical Engineering, University Malaya. Dr. Harikrishnan was the recipient of Intel Fellowship Grant Award, from 2000 to 2006. His research work has resulted in several technical publications. His main research interest includes Analogue Integrated Circuit Design, RFIC Design and VLSI system design. E-mail: hrkhari@um.edu.my Jeevan Kanesan received B.S. degree in electrical & electronics engineering from University Technology Malaysia, Johor, Malaysia, in 1999, and M.S. degree and Ph.D. degree in mechanical engineering from University Science Malaysia, Penang, Malaysia in 2003 and 2006 respectively. From 2000 to 2001, he has worked as equipment engineer at Carsem Semiconductor, Ipoh, Malaysia and IC Design engineer in the thermo-mechanical department, Intel Technology Sdn. Bhd., Penang, Malaysia from 2006 to 2008. He has been with University Malaya, Malaysia as a Senior Lecturer in the electrical engineering department since 2008. His research work has so far generated 20 technical publications. His research interests include CAD of VLSI circuits and design and analysis of algorithms. E-mail: jievan@um.edu.my DOI: 10.4103/0377-2063.106760; Paper No JR 3_12; Copyright 2012 by the IETE 506 IETE JOURNAL OF RESEARCH VOL 58 ISSUE 6 nov-dec 2012