A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals Bongjin Kim, Somnath Kundu, Seokkyun Ko and Chris H. Kim University of Minnesota, Minneapolis kimx2447@umn.edu
Agenda Motivation Conventional vs. proposed VCO-based ADC Multi-phase & Noise-shaping BF Quantizer Test chip configuration Measurement results Conclusion 2
Direct Sub-mV Signal Acquisition [µv~mv] LNA VGA [V] Conv. ADC N-bit [µv~mv] BF- ADC N-bit Conventional This Work Conventional - Signal pre-conditioning amplifiers (LNA/VGA) - Conventional ADC for rail-to-rail input range 0 This work (Beat Frequency (BF) ADC) - Direct A-to-D conversion w/o signal amplification 3
Conv. vs. Proposed VCO-Based ADC [mv] V IN CK S CK IN Counter Reset Conventional (VCO + Counter) D OUT (= f IN /f S ) CK IN CK S D OUT 64 64 63 0-1 bit resolution Counter Reset f REF f IN *f BF [mv] CK BF BF clock (f BF =f REF -f IN ) *f BF = f REF - f IN > 0 (Ref. VCO Bias > Input VCO Bias) V IN CK IN CK REF BF Counter D OUT (= f IN /f BF ) CK REF CK IN CK S CK BF CK S Proposed (VCO + BF-Counter) D OUT 64 31 15 Multi-bit (6-7bit) resolution Conventional : Linear freq. detection using VCO Proposed : High-resolution BF detection based [1] [1] B. Kim et al., IEEE Custom Integrated Circuits Conference 2013 4
Noise-Shaping Beat Freq. Quant. VCO reset f IN / (f REF -f IN ) = 3.33 CK REF CK REF V IN V IN CK IN CK IN CK BF CK BF CNT BF CNT BF D OUT 3 3 3 D OUT 3 3 4 3 Quant. Error +0.33 +0.33 +0.33 Quant. Error +0.33 +0.33-0.66 Prior work [1]: Nyquist rate This work: Noise-shaping Noise-shaping improves BF detection resolution 5
Multi-Phase Beat Freq. Quantization (Example of a 7-phase ring oscillator) ph0 ph0 ph1 ph2 ph3 ph4 ph5 ph6 ph0 Unused phases ph0 ph1 ph2 ph3 ph4 ph5 ph6 CK REF CK IN CK REF CK IN CK BF CK BF (Single-phase resolution) Prior work [1] (Multi-phase resolution) This work N-phase improves BF detection resolution N-times 6
Output Output Linear BF-ADC with Multi-Phase (Raw BF-ADC output) [1mV] Input (1) BF ADC [3-4 ENOB] *BF Decoder BF DEC* (2) Prior Work [1]: 1-phase Input (1) x (2) (Decoded: Linear) [6-7 ENOB] [1mV] BF ADC No DEC This Work: 31-phase (Pseudo-linear) [6-7 ENOB] Does not require BF-decoding with the improved resolution from multi-phase 7
DNL [LSB] INL [LSB] BF-ADC Output Linearity of Multi-Phase BF-ADC 8 6 [0bit @ 1mV] 1mV +4.95bit w/ 31-phase [4.95bit @ 1mV] 31 from phase #0~#30 4 Pseudo-linear region 2 1step=0bit 0 0 5 Input Voltage [mv] 1-Phase BF Quantizer (#0) 0 0 1 Input Voltage [mv] 31-Phase BF Quantizer 1 0-1 [-0.38, +0.62] [-0.02, +0.02] 0 21 42 63 Output Code 10 0-10 [0, +7.82] 1-phase BF Quant. 31-phase BF Quant. 0 21 42 63 Output Code [0, +0.32] Simulated linearity: DNL MAX /INL MAX =0.02/0.32 [LSB] 8
Comparison with Prior Arts Quantization Scheme Freq. Detection Sensitivity* (@ 100 counts) Noise-Shaping Multi-Phase BF Code Utilization Conventional VCO-based Linear Counting Low (1%) - Previous BF-ADC [1] Beat Freq. Counting High (0.01%) Wide (Nonlinear) This work Beat Freq. Counting High (0.01%) Yes No Yes Yes No Yes Narrow (Pseudo-linear) BF Decoding - Required Not Required *Freq. step required for a count change of one 9
VCO-Based ADC w/ BF-Quantizer V IN+ 31-phase Ring-Oscillator CLK INP CLK REF Counter BF Quantizer #0 BF Quantizer #1 BF Quantizer #2 BF Quantizer #30 RST Reset READ Short Pulse Generator CLK S NBFP CLK INP0 CLK REF0 N BFP0 N BFP30 Σ CLK S D OUTP CLK INN RST Short Pulse Generator Reset Counter READ CLK S NBFN CLK INN0 N BFN30 N BFN0 Σ CLK S D OUTN V IN- 31-phase Ring-Oscillator A pair of 31-phase ring oscillator for +/- inputs 31x banks (each consists of +/- BF quantizers) 10
Measured Code vs. Ramp Input N AVG +32 Output Code N AVG 1-phase BF Quant. 31-phase BF Quant. N AVG -32 0 40 80 120 160 ADC sample number Noise-shaping is clearly shown in the results 31-phase result shows 31x wider output range 11
Magnitude [dbfs] Measured FFT Result w/ 1mV Input 0-20 [1.85kHz, 1mV sine input, 10kHz BW] 1-phase BF Quant. 31-phase BF Quant. -40-60 -80-100 10 3 Frequency [Hz] 10 4 10 5 SNDR = 43dB (i.e. ENOB=6.85) / SFDR = 56.7dB 12
SNDR [db] Measured SNDR vs. Input Amplitude 50 40 [1.85kHz sine input, 10kHz BW] 1-phase BF Quant. 31-phase BF Quant. 30 20 10 43dB @ 1mV 33dB @ 1mV 0-105 -95-85 -75-65 -55 Input Amplitude [dbfs] SNDR @ 1mV = 43dB @ 31-phase, 33dB @ 1-phase 13
430µm Chip Micrograph 600µm 31-phase Pos. ROSC 31-phase Ref. ROSC 31-phase Neg. ROSC Multi-phase Routing & Decap. Positive BF Quantizers (31x) Negative BF Quantizers (31x) Adder Adder Test Circuitry 14
Performance Comparison VLSI'07 VLSI'11 [1] This CICC'13 work Process 0.13µm 90nm 65nm 65nm Supply 1.2V N/A 1.2V 1.2V Sample Rate 950MHz 640MHz 4.17kHz 300kHz Input BW 20MHz 8MHz 2kHz 10kHz SNDR 1mV * 12dB 3dB 35dB 43dB ENOB 1mV * 1.70 0.21 5.52 6.85 SFDR[dB] N/A 71.4 41.9 56.7 IN 0dB [dbfs]** -70-63 -89-105 Power Area[mm 2 ] 38mW 0.185 4.3mW 0.10 0.92µW 0.013 36µW 0.258 * Peak SNDR/ENOB for a 1mV input amplitude. ** Input amplitude at SNDR = 0dB (dbfs @ full-scale = 1V) 15
Conclusion A VCO-based ADC featuring beat-freq. quantizer is designed using 65nm CMOS for a direct A-to- D conversion of sub-mv input signal Multi-phase and 1 st order noise-shaping property improves ADC resolution without the use of beat frequency decoding 43dB SNDR (6.85 ENOB) has been achieved for a 1mVppd input signal 16