Wafer Admission Control for Clustered Photolithography Tools Kyungsu Park Department of Industrial and System Engineering KAIST, Daejeon, 305-70 Republic of Korea Abstract In semiconductor wafer manufacturing, clustered photolithography scanners frequently use pre-scan or post-scan wafer buffers to ensure that the scanner is seldom starved of wafers or blocked from further production. While such practice is essential to maximize the throughput of this costly tool, stateof-the-art methods for determining when to use the buffer are overly cautious. As a consequence, each wafer s residency time in the tool may be significantly larger than necessary and the time a lot spends inside the cluster is increased. Since satisfaction of time windows and reduction in wafer residency time in a tool will arguably improve yield and reduced lot process time will increase manufacturing deployment opportunities, we strive to minimize residency time while maintaining maximum throughput. To achieve our goal, we develop wafer admission control algorithms considering setups and transient operation. The output of the algorithm is suggested wafer entry times to the tool and is intended to be used by the wafer handling robot as a guideline. We simulate several representative systems to verify the performance of the approach. For a typical system, it is shown that, while maintaining throughput, the wafer residency time, the lot process time and the wafer buffer occupancy are reduced by 54%, 3% and 67%, respectively. The lot deployment opportunity in the same case is increased by 4%. As a consequence, there are fewer wafers for the wafer handling robots to serve and the tool may be designed with fewer buffer slots. The concept and algorithm will thus improve clustered photolithography performance in numerous ways. I. INTRODUCTION The purpose of the pre-scan wafer buffer in clustered photolithography tools is to provide the scanner with a ready supply of wafers in the event of setup delays in the pre-scan track. A supply of wafers in the buffer ensures minimal loss of scanner throughput. However, wafers often languish needlessly and for a significant duration of time in the prescan buffer. This is because typical wafer admission policies (implemented by a wafer handling robot) do not carefully admit wafers as needed for setup protection. Rather, they admit wafers in an opportunistic manner as the wafer, robot and first process are jointly available. The consequences of unnecessarily early wafer admission are twofold. First, lots are admitted into the tool earlier than necessary, preventing them from being deployed to another tool should one become available. The result is increased sector cycle time and so called deployment capacity loss ([]). Second, and perhaps more importantly, early wafer admission, and the resulting high buffer levels, causes an increase in the James R. Morrison Department of Industrial and System Engineering KAIST, Daejeon, 305-70 Republic of Korea duration of time each wafer spends in the tool. This may result in a loss of yield. In semiconductor manufacturing, it is generally believed that lots with long cycle times incur higher contamination levels resulting in yield loss. In [2], it was shown that a reduction in waiting times at key production stages provides an improvement in manufacturing yield in semiconductor wafer manufacturing. In the studies of [3-5], they assumed that the duration of time the wafer spends in fabrication leads to a reduction in yield. There is thus ample evidence and conjecture that wafer cycle times are correlated with yield. Our goal is to develop and evaluate wafer admission algorithms that guarantee no loss of throughput while minimizing the wafer residency time (the average duration each wafer is in the tool). Since we can easily achieve our goal by fixing the wafer admission interval at the bottleneck output interval when the buffer is full and the tool is in steady state operation, our policies are most relevant in transient operation. That is, our algorithm will be effective when switching from one class of lot to another or before the buffer reaches its target level. Such transient behavior is particularly relevant for high mix manufacturing and is anticipated in the impending era of 450mm diameter wafers ([6]). To our knowledge, only a single effort described below has addressed this issue. However, work on related concepts such as deployment loss, parallelism (extended duration of time in a tool) and transient modeling of clustered photolithography tools may be found in [], [7], and [8-9], respectively. Since transient analysis and the control of systems with wafer handling robots are intractable problems ([0]), we abstract to a flow line model of the tool. The resulting wafer admission policy will be directly applicable to the robot controller as a guideline for wafer pickup time at the tool entrance. In [], a guideline for wafer admission was developed. They considered scheduled failures during the processing of lots using a serialized flow line model with only a single class of wafers. Here, we study flow line models with redundant and setups between lot changes. As we incorporate practical features such as multiple classes of wafers and the reticle alignment process at the scanner, our model is more practically applicable and extends the results of []. We conduct simulation studies on models of clustered photolithography tools to verify the algorithm s performance. In our studies we consider different train sizes (the average number of lots of the same class processed sequentially)
systems and loading. The results indicate, for example, that we can reduce the wafer residency time, the lot process time and the wafer buffer occupancy by 54%, 3% and 67%, respectively, when the train level is 3 and the loading level is 90% of the maximum throughput of the tool. The paper is organized as follows. In Section II, we describe clustered photolithography tools and flow line models. The equations for wafer behavior and the algorithms are presented in Section III. In Section IV, numerical experiments are discussed. Concluding remarks are presented in Section V. II. SYSTEM DESCRIPTION A. Clustered Photolithography Tools Photolithography tools play an important role in semiconductor wafer manufacturing process. Such a tool consists of a pre-scan track, a photolithography scanner and a post-scan track. As the scanner is very expensive it is typically the bottleneck process of the clustered photolithography tool. The track tools consist of numerous processes and each process may be conducted by several to guarantee a sufficient throughput. The pre-scan track prepares each wafer for the scanner by coating the wafer with photosensitive chemicals and conducting baking and cooling operations. The photolithography scanner exposes wafers to desired light patterns. The post-scan track develops the wafer. There may be wafer buffers between the track tools and scanner and several wafer handling robots within the clustered tool. Fig. depicts a clustered photolithography tool with one pre-scan tool consisting of 3 processes, one pre-scan buffer with six wafer capacity, one photolithography scanner, one post-scan tool consisting of 3 processes and one wafer handling robot. Fig.. A clustered photolithography tool. Wafers randomly arrive to the system in batches called lots and are served in a first come first served (FCFS) manner. There are K classes of wafers, each has different process times. When changing lot class, a setup of the track tool and a reticle alignment process may be required. A track setup only can begin once all of its are empty. The reticle alignment process is conducted for the first wafer when lot class changes. B. Flow Line Models For tractability, we abstract the clustered photolithography tool to a flow line. That is, we do not model robot actions. Such an abstraction is sufficient for our purposes as we seek to develop recommendations for wafer admission that the wafer handling robot may consider in its deliberations. A flow line model consists of a sequence of M processes, P,, P M, which wafers must receive in order. There are R m for process P m. Each module can hold at most one wafer. An arriving wafer waits at the infinite queue and enters service when one of the for process P is available. Once a wafer enters the module for process P m, it advances to next process P m+ if the wafer completes process m and at least one module for process P m+ is available. When a wafer completes process P M, it exits the system. Such a flow line model is depicted in Fig. 2. Wafers Arrive R 2 R Infinite queue P 2 P...... P P2 Fig. 2. A flow line with redundant. III. OPTIMIZATION MODELS WITH SETUPS R M P M... P M Wafers Exit Photolithography tools may require setups between lots and a reticle alignment process for the first wafer of each lot when lot class changes. In this section, we develop flow line models for the wafer behavior and optimization algorithms that minimize wafer residency time subject to maximum throughput. The algorithm decides when wafers should enter the tool; we call this wafer admission control. We extend the algorithms of [] to a redundant flow line models with a focus on practical features such as multiple classes of lots, reticle (re)alignment and setups between lots. A. Flow Line Models with Redundant Modules and Setup We use X m (i, w) to denote the time instant when wafer w of lot i enters into process P m. Let τ k m denote the deterministic process time for a wafer of class k at process m. Let C m (i, w) denote the completion time of a wafer w of lot i at process P m (not including time spent queueing for the next process), so that C m (i, w) = X m (i, w) + τ k m. Process P m has R m redundant. Let a(i) denote the arrival time of lot i and c(i) denote the class of lot i. When changing from one class of lot to another two kinds of setups are conducted; track setups and reticle alignment. Track setups require that all devoted to processes prior to and including some process P p be empty before the setup begins. For clustered photolithography tools, process P p is generally the last process of the pre-scan track. Once all before and including process P p are vacant, the setup may commence. These then remain empty for the deterministic duration of the setup τ setup (the duration can be a function of the lot classes). Assume that we know the class of the succeeding lots before it arrives. Reticle alignment is conducted at process P s (P s is the scan process), where s > p, and is done for the first wafer of the lot when lot class changes. It has deterministic duration, τ align. Lot i consists of W i wafers. Since the setup can start once the last wafer of the preceding lot enters process P p+,
X (i, ) = max{a(i), X P+ (i-, W i- )}+ τ setup if c(i) c(i-), () X (i, ) = max{a(i), X 2 (i, W i- -R +)} if c(i) = c(i-), (2) X m (i, w) = max{ X m- (i, w) + τ c(i) m-, X m+ (i, w-r m )} for i and m, (3) X s+ (i, ) = max{x s (i, ) + τ c(i) s+τ align, X s+2 (i, W i- -R s+ +)},(4) X M (i, w) = max{ X M- (i, w) + τ c(i) M-, X M (i, w-r M ) +τ c(i) M},(5) for w > 0 and i =,, L (L is the number of lots considered). Above a negative wafer index indicates a wafer of the previous lot, that is, X m (i, w) = X m (i-, W i- -w+) for w < 0. Initial conditions are X P+ (0, W 0 ) = - for w < 0 and X m (i, w) = - for i < 0. With these equations, we can calculate the completion time of wafer w of lot i from a tool as C M (i,w) = X M (i, w) +τ c(i) M. (6) Equations () and (2) assume that each wafer enters the tool as soon as possible. That is, wafers enter the tool when a wafer and the first process are jointly available. This policy is called opportunistic wafer entry, provides the earliest exit time for each wafer, and results in maximum throughput. Note that buffers can be considered as a process with zero service time. B. Optimization Models We next discuss how to obtain the maximum throughput and reduce the wafer residency time. This process is the same as in [] at the high level. However, since we are using the extended equations ()-(6), the detailed calculations are different. We include the steps of the high level procedure here for completeness. In the opportunistic wafer entry policy, wafers enter a tool earlier than necessary; thus causes two negative consequences. First, lots enter a tool earlier than necessary and cannot be deployed to another tool if one becomes available. This causes deployment capacity loss and increased sector cycle time. Second, unnecessarily early wafer admission forces more wafers into the tool than are needed for maximum throughput. Thus, there are unnecessary delays inside the tool and high buffer levels. Consequently, there is more wafer handling robot movement, and the residency time of each wafer is increased and may have higher variation. However, we can reduce the negative effects of the opportunistic wafer admission policy while preserving the maximum throughput of that policy with wafer admission control. We next provide an algorithm that computes the latest wafer entry time for each wafer that still guarantees maximum throughput. The algorithm consists of two steps. Step: Determine the earliest exit time for each wafer. With given anticipated lot arrival times, reticle alignment times and setup durations, calculate the earliest exit time for each wafer by using the opportunistic wafer admission policy. The solution of () to (6) gives the earliest possible exit times for each wafer. Denote those times as C* M (i,w) for i =,, L and w =,, W i. Step2: Compute the latest admission time for each wafer that will still guarantee the earliest wafer exit time. In this step, we consider the wafer admission times as decision variables and restrict the exit time for each wafer to that of Step. To obtain the latest admission time for each wafer, use the objective function Max W w= X ( w). The optimal solution obtained with this objective function provides the minimum average residency time (see []). The optimization problem is as follow: Max W w= X ( w) Subject to equations (3), (4), (5), X (i, ) max { a(i), X P+ (i-, W i ) }+ τ setup if c(i) c(i-), X (i, ) max { a(i), X 2 (i, W i- -R +) } if c(i) = c(i-), C M (i, w) = C* M (i, w), for i =,, L and w =,, W i. The optimal solution provides the recommended admission time for each wafer which is the latest release time into the tool to guarantee maximum throughput. IV. NUMERICAL EXPERIMENTS We conduct a numerical study of several different systems to evaluate the effectiveness of our algorithm. The systems we study are based on [9]. The process time data for each class and the number of parallel for each process are given in the appendix of Section VI. All systems have deterministic process times, random setup time and random reticle alignment time and allow redundant. The setup times and reticle alignment time are uniformly distributed over [20, 300] seconds and [240, 420] seconds, respectively. There are 5 pre-scan processes, 2 or 24 buffer, one bottleneck (scan) module and 5 post-scan processes. System and 3 have a buffer with 24 wafer slots and System 2 has a 2 wafer buffer. Setups on the track occur when changing lot type and the st wafer of every lot prompts delay for a reticle alignment at the scanner. The setup index P is 5 (that is, processes P,, P 5 must be vacant before a setup can begin). There are 3 classes of lots (K = 3) and we consider three different average train sizes (T =.5, 3, 6). Each lot consists of 24 wafers (W = 24) and we use a Poisson arrival process with ten different system loading levels. We first study the Just-in-Time (JIT) maximum throughput case, and subsequently consider loading levels ρ = 0., 0.2,..., 0.9, (the JIT case is the ρ = case). Assume that we already know the class of the succeeding lots before it arrives. We conducted 0 replications for each case. Each replication consists of,800 lots and averages are calculated based on the last,500 lots. The results for Systems and 2 are very similar to that of System 3; we provide only the results for System 3.
A. Cycle Time and Throughput Time Fig. 4. Average buffer level for System 3. Fig. 3. Cycle time and throughput time for System 3. The cycle time and throughput time of System 3 are depicted in Fig. 3. Cycle time is the duration of time that a lot is inside the tool; the cycle time of lot i is CT(i) = C M (i,w i ) - X (i, ). Throughput time is defined as TT(i) = min{ CT(i), C M (i,w i ) - C M (i-,w i- )}. The average of the throughput time is the inverse of the measured tool throughput. The graph shows that our algorithm (Alg.) provides much less cycle time with same throughput time as compared to the opportunistic wafer admission (Opp.). In the case of T = 3 and ρ = 0.9, (typical values for a real environment), the cycle time of the algorithm is 3.35% smaller than that of the opportunistic admission policy. Fig. 4 depicts the pre-scan buffer levels for each case. Buffer level is defined as the average number of wafers occupying the buffer. When wafers are admitted into the tool as necessary, buffer use is reduced. Consequently, wafers spend less time in the buffer and the mean wafer residency time (the average duration each wafer is in the tool) and lot cycle time are reduced. A reduction in buffer use also allows are to design the tool with less buffer space. Less buffer size may improve space efficiency. In the system with T = 3 and ρ = 0.9, our algorithm reduced the average buffer level by 66.57%. C. Wafer Residency Time B. Pre-scan Buffer Occupancy
F. Performance Characterization of the Algorithms Fig. 5. Wafer residency time for System 3. As mentioned before, reduced wafer residency time may improve yield. It is the specific purpose of our algorithm to reduce residency time. Fig. 5 shows that our algorithm works well for that purpose. In the system with T = 3 and ρ = 0.9, it reduces the wafer residency time by 53.90%. D. Deployment Opportunity Fig. 6. Deployment opportunity for System 3. When a lot is seized by a tool as late as possible, it has greater chance to be deployed at another accessible and empty tool. Our algorithm increases this chance. Simulation results of the deployment opportunity improvement are depicted in Fig. 6. The opportunity time is measured by a(i) X (i, ), that is, queuing time of a lot before the lot enters a tool. The y axis of the graph represents the improvement of opportunity times of our algorithm compared to opportunistic wafer entry. That is, increment in average opportunity time by applying our algorithm divided by that of opportunistic wafer entry. In the system with T = 3 and ρ = 0.9, our algorithm obtains a 3.62% increase in deployment opportunity time compared to opportunistic wafer entry. E. Algorithm Performance with Train Level Based on the previous results, when the train level is higher, our algorithm provides more improved results in tool performances such as cycle time of lot, buffer level, wafer residency time and deployment opportunity. It is due to that high train level means fewer changes of lot class resulting in fewer setups. Consequently, pre-scan buffers do not need to be filled with wafers to preserve throughput. Fig. 7. Performances of the algorithms for System 3 (T = 3, ρ = 0.9). Fig. 7 depicts the results of several admission policies in System 3 with T = 3 and ρ = 0.9. The throughput is calculated as the inverse of the average throughput time. Opportunistic wafer entry provides maximum throughput with large residency time. Our algorithm reduces the residency time while preserving the maximum throughput. The bottleneck interval policy admits wafer at constant interval equal to the bottleneck process time after the entry of the first wafer of a new class of lot. That policy offers minimum residency time when the bottleneck process is a single module. In this characterization, a policy with high throughput (greater y-axis value) and low residency time (smaller x-axis value) is desired. The algorithm presented here performs quite well. V. CONCLUDING REMARKS Process time of a lot, wafer residency time and, arguably, yield can all be improved by wafer admission control. In this paper, we have introduced a wafer admission control algorithm that minimizes wafer residency time while achieving maximum throughput. It will provide lower buffer levels and improved deployment opportunity by recommending wafer admission times that can be used by a wafer transfer robot controller. Numerical experiments support the effectiveness of the algorithm. The algorithm allows practical consideration of clustered photolithography tools including pre-scan setup and reticle alignment process. Future work will be to incorporate robot movements inside the tools into the wafer admission control algorithm. It would also be of interest to develop a lower level robot controller to obey the guidelines of the algorithm. ACKNOWLEDGMENT This work was supported in part by the Korea Research Foundation (KRF) Grant N0090250 and N000263.
VI. APPENDIX: EXPERIMENTAL DATA TABLE I PROCESS TIME DATA FOR SYSTEM System Class 2 3 number of τ k 98 00 92 2 τ k 2 35 38 29 3 τ k 3 32 37 39 τ k 4 04 90 96 2 τ k 5 38 36 34 Note τ k 6 0 0 0 24 Buffer τ k 7 65 60 55 Scanner τ k 8 26 29 23 τ k 9 47 29 38 3 τ k 0 90 80 70 2 τ k 28 33 34 τ k 2 93 90 99 3 TABLE II PROCESS TIME DATA FOR SYSTEM 2 System 2 Class 2 3 number of τ k 98 00 92 2 τ k 2 35 38 29 3 τ k 3 32 37 39 τ k 4 04 90 96 2 τ k 5 38 36 34 Note τ k 6 0 0 0 2 Buffer τ k 7 65 60 55 Scanner τ k 8 26 29 23 τ k 9 47 29 38 3 τ k 0 90 80 70 2 τ k 28 33 34 τ k 2 93 90 99 3 International Semiconductor Manufacturing Symposium, pp. 267-270, 200. [3] Krishna Srinivasan, Raka Sandell, and Steven Brown, Correlation between yield and waiting time: A quantitative study, IEEE/CPMT International Electronics Manufacturing Technology Symposium, pp. 65-69, 995. [4] Lawrence M. Wein, On the relationship between yield and cycle time in semiconductor wafer fabrication, IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No.2, pp. 56-58, 992. [5] Doron Meyersdorf and Taho Yang, Cycle time reduction for semiconductor wafer fabrication facilities, IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pp. 48-423, 997. [6] D. Pillai, The future of semiconductor manufacturing: Factory integration breakthrough opportunities, IEEE Robotics and Automation Magazine, vol.3, no. 4, pp. 6 24, 2006. [7] J. R. Morrison and D. P. Martin, Performance evaluation of photolithography cluster tools: Queueing and throughput models, OR Spectrum, vol., no. 4, pp. 375-389, 2007. [8] T. L Perkinson, P. K. McLarty, R. S. Gyurcsik and Ralph K. Cavin III, Single-wafer cluster tool performance: An analysis of throughput, IEEE Transactions on Semiconductor Manufacturing, Vol. 7, No. 3, pp. 369-373, 994. [9] James R. Morrison, Deterministic flow lines with applications, IEEE Transactions on Automation Science and Engineering, Vol. 7, No. 2, pp. 228-239, April 200. [0] Milind W. Dawande, H. Neil Geismar and Suresh P. Sethi, Throughput optimization in robotic cells, Springer, 2007 [] Kyungsu Park and James R. Morrison, Control of wafer release in muti cluster tools, to appear in the Proceedings of the 200 IEEE International Conference on Control and Automation, June 200. TABLE III PROCESS TIME DATA FOR SYSTEM 3 System 3 Class 2 3 number of τ k 92 70 52 2 τ k 2 26 84 3 τ k 3 33 48 7 τ k 4 65 86 46 2 τ k 5 47 32 9 Note τ k 6 0 0 0 24 Buffer τ k 7 00 75 50 Scanner τ k 8 29 6 4 τ k 9 4 8 3 τ k 0 50 70 60 2 τ k 23 26 29 τ k 2 96 87 69 3 REFERENCES [] Marcoux, P. McClintock, M. Martin, D. Woods, R., Determining capacity loss from operational and technical deployment practices in a semiconductor manufacturing line, Proceedings of the 999 IEEE International Semiconductor Manufacturing Symposium, pp. 3-5, 999. [2] Wen-Chi Chang, Max Yu, Ray Wu, Claire Chen, Joey Chen, C. Y. Hsieh, and C. K. Wang, Yield improvement through cycle time and process fluctuation analyses, Proceedings of the 200 IEEE