March 5, 2007 Spansion S29GL512N11TAI02 512 Mbit MirrorBit TM Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Transistors and Poly 3.7 Isolation 3.8 Wells and Substrate 4 Flash Cell Analysis 4.1 MirrorBit TM Architcture 4.2 Flash Cell in Plan-View 4.3 Cross-Section Analysis (Parallel to Bit Line) 4.4 Cross-Sectional Analysis (Parallel to Word Line)
Structural Analysis 5 Materials Analysis 5.1 TEM-EDS Analysis of the Dielectrics 5.2 TEM-EDS Analysis of the Metal 1 5.3 TEM-EDS Transistor and Contacts 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Top Package Photograph 2.1.2 Bottom Package Photograph 2.1.3 Bottom Package Marking 2.1.4 Package Pin-Out 2.1.5 Plan-View Package X-Ray 2.1.6 Package Cross-Section 2.1.7 Die Photograph 2.1.8 Die Markings 2.1.9 Annotated Die Photograph at Polycide 2.2.1 Die Corner 1 2.2.2 Die Corner 2 2.2.3 Die Corner 3 2.2.4 Die Corner 4 2.2.5 Minimum Pitch Bond Pads 3 Process Analysis 3.1.1 General View of S29GL512N11TAI02 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad 3.2.2 Right End Bond Pad 3.3.1 Passivation 3.3.2 IMD 2 3.3.3 IMD 1 3.3.4 TEM Pre-Metal Dielectric 3.4.1 Minimum Pitch Metal 3 3.4.2 TEM Metal 3 Cap Layer 3.4.3 TEM Metal 3 TiN Barrier and Ti Adhesion Layers 3.4.4 Minimum Pitch Metal 2 3.4.5 TEM Minimum Pitch Metal 2 3.4.6 Minimum Pitch Metal 1 3.4.7 TEM Metal 1 TiN Cap Layer 3.4.8 TEM Metal 1 TiN Barrier and Ti Adhesion Layers 3.5.1 Minimum Pitch Via 2s
Overview 1-2 3.5.2 Minimum Pitch Via 1s 3.5.3 Minimum Pitch Bit Line Contacts to Diffusion 3.5.4 TEM Bit Line Contact 3.5.5 TEM Peripheral Contact Silicide 3.5.6 Contact to Polycide 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 Minimum Gate Length Peripheral PMOS Transistor 3.6.3 TEM Peripheral NMOS Transistor 3.6.4 TEM Peripheral Gate Edge 3.6.5 TEM Peripheral Gate Oxide Thickness 3.6.6 TEM Flash Cell Gate Dielectric 3.6.7 Minimum Pitch Polycide 3.7.1 Polycide Over Field Oxide 3.7.2 Minimum Width STI 3.8.1 Peripheral N-Well 3.8.2 SCM Embedded P-Well 3.8.3 SRP Shallow Peripheral N-Well 3.8.4 SCM Peripheral and Array P-Wells 4 Flash Cell Analysis 4.1.1 MirrorBit TM Flash Array 4.1.2 Flash Array in Perspective and Cross-Sectional Views 4.2.1 Metal 3 4.2.2 Metal 2 4.2.3 Metal 1 Bit Lines 4.2.4 Polycide Word Lines 4.2.5 SCM Bit Line Diffusions 4.3.1 Flash Cell in Cross-Section 4.3.2 Word Lines Over N + Bit Line Diffusion 4.3.3 Bit Line Contact and Bit Line Diffusion 4.3.4 TEM Bit Line Contact and Word Lines 4.3.5 TEM Polycide Word Line 4.3.6 TEM ONO Gate Dielectric 4.3.7 TEM Lattice Image of ONO Gate Dielectric 4.3.8 TEM Bit Line Contact 4.4.1 Word Line and Bit Line Diffusions 4.4.2 Bit Line Contacts
Overview 1-3 5 Materials Analysis 5.1.1 TEM-EDS Spectra of Silicon Nitride and Oxide Passivation 5.1.2 TEM-EDS Spectra of IMD 2 Layers 5.1.3 TEM-EDS Spectra of IMD 1 Layers 5.1.4 Metal 1 Seed and ARC Layers 5.1.5 TEM-EDS Spectra of PMD Layers 5.2.1 TEM-EDS Metal 1 TiN Cap Layers 5.2.2 TEM-EDS Metal 1 TiN/Ti Barrier and Adhesion Layers 5.3.1 TEM-EDS ONO Gate Dielectric 5.3.2 TEM-EDS Titanium Silicided Source/Drain Diffusion 5.3.3 TEM-EDS Silicon Nitride Sidewall Spacer 1.2 List of Tables 1.5.1 Device Summary 1.6.1 Process Summary 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 4.3.1 Flash Cell Dimensions
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