HCPL, HCPL, HCPL, HCPL7, HCPL8, HCPL9 High Speed- MBit/s Logic Gate Optocouplers Single Channel: HCPL, HCPL, HCPL Dual Channel: HCPL7, HCPL8, HCPL9 Features Compact SO8 package Very high speed- MBit/s Superior CMR Logic gate output Strobable output (single channel devices) Wired OR-open collector U.L. recognized (File # E97) IEC77-5- approved (VDE option) HCPL, HCPL, HCPL only Applications Ground loop elimination LSTTL to TTL, LSTTL or 5-volt CMOS Line receiver, data transmission Data multiplexing Switching power supplies Pulse transformer replacement Computer-peripheral interface Description August The HCPLXX optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output (single channel devices). The devices are housed in a compact small-outline package. This output features an open collector, thereby permitting wired OR outputs. The HCPL, HCPL and HCPL output consists of bipolar transistors on a bipolar process while the HCPL7, HCPL8, and HCPL9 output consists of bipolar transistors on a CMOS process for reduced power consumption. The coupled parameters are guaranteed over the temperature range of - C to +85 C. An internal noise shield provides superior common mode rejection. Package Dimensions. (.). (.) SEATING PLANE Pin. (5.).8 (.).9 (.8). (.). (.). (.5). (.).8 (.). (.5). (.8). (.8).5 (.7) TYP Lead Coplanarity :. (.) MAX Note: All dimensions are in inches (millimeters). (.9). (5.9) HCPLXX Rev...9
N/C Single-channel circuit drawing (HCPL, HCPL and HCPL) Truth Table (Positive Logic) + V F _ N/C 5 GND Input Enable Output H H L L H H H L H L L H H* NC* L* L* NC* H* 8 7 V CC V E V O + V F V F + 5 GND Dual-channel circuit drawing (HCPL7, HCPL8 and HCPL9) 8 7 V CC V V *Dual channel devices or single channel devices with pin 7 not connected. A.µF bypass capacitor must be connected between pins 8 and 5. (See note ) HCPLXX Rev...9
Absolute Maximum Ratings (No derating required up to 85 C) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Value Units T STG Storage Temperature - to +5 C T OPR Operating Temperature - to +85 C EMITTER I F DC/Average Forward Input Current (each channel) Single Channel 5 ma Dual Channel V E Enable Input Voltage Single Channel 5.5 V Not to exceed VCC by more than 5mV V R Reverse Input Voltage (each channel) 5. V P I Power Dissipation Single Channel 5 mw Dual Channel DETECTOR V CC Supply Voltage 7. V ( minute max) I O Output Current (each channel) Single Channel 5 ma Dual Channel 5 V O Output Voltage (each channel) 7. V P O Collector Output Power Dissipation Single Channel 85 mw Dual Channel 85 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units I FL Input Current, Low Level 5 µa I FH Input Current, High Level *. 5 ma V CC Supply Voltage, Output.5 5.5 V V EL Enable Voltage, Low Level Single Channel only.8 V V EH Enable Voltage, High Level Single Channel only. V CC V T A Operating Temperature - +85 C N Fan Out (TTL load) Single Channel 8 TTL Loads Dual Channel 5 R L Output Pull-up K Ω *.ma is a guard banded value which allows for at least % CTR degradation. Initial input current threshold value is 5.mA or less HCPLXX Rev...9
Electrical Characteristics (T A = - C to +85 C unless otherwise specified.) Individual Component Characteristics Symbol Parameter Test Conditions Min. Typ.* Max. Unit EMITTER V F Input Forward Voltage I F = ma.8 V T A = 5 C.75 B VR Input Reverse Breakdown Voltage I R = µa 5. V ΔVF/ΔTA Input Diode Temperature Coefficient I F = ma -.5 mv/ C DETECTOR I CCH High Level Supply Current I F = ma, V E =.5 V V CC = 5.5V Single Channel ma Dual Channel 5 I CCL Low Level Supply Current I F = ma, V E =.5 V Single Channel ma V CC = 5.5V Dual Channel I EL Low Level Enable Current V CC = 5.5V, V E =.5V Single Channel -. ma I EH High Level Enable Current V CC = 5.5V, V E =.V Single Channel -. ma V EH High Level Enable Voltage V CC = 5.5V, I F = ma Single Channel. V V EL Low Level Enable Voltage V CC = 5.5V, I F = ma () Single Channel.8 V Switching Characteristics (T A = - C to +85 C, V CC = 5 V, I F = 7.5 ma unless otherwise specified.) Symbol AC Characteristics Test Conditions Device Min. Typ. Max. Unit T PLH Propagation Delay Time to Output High Level R L = 5Ω, C L = 5pF () T A = 5 C All 75 ns (Fig. ) T PHL Propagation Delay Time R L = 5Ω, C L = 5pF () T A = 5 C All 5 75 ns to Output Low Level (Fig. ) T PHL -T PLH Pulse Width Distortion R L = 5Ω, C L = 5pF (Fig. ) All 5 ns t r Output Rise Time (-9%) R L = 5Ω, C L = 5pF (5) (Fig. ) Single Ch 5 ns Dual Ch 7 t f Output Fall Time (9-%) R L = 5Ω, C L = 5pF () (Fig. ) Single Ch ns Dual Ch 5 t ELH t EHL CM H CM L Enable Propagation Delay Time to Output High Level Enable Propagation Delay Time to Output Low Level Common Mode Transient Immunity (at Output High Level) Common Mode Transient Immunity (at Output Low Level) I F = 7.5mA, V EH =.5V, R L = 5Ω, C L = 5pF (7) (Fig. ) I F = 7.5mA, V EH =.5V, R L = 5Ω, C L = 5 pf (8) (Fig. ) R L = 5Ω, T A =5 C, I F = ma, V OH (Min.) =. V (9) (Fig., ) R L = 5Ω, T A =5 C, I F = 7.5mA, V OL (Max.) =.8 V () (Fig., ) HCPL HCPL HCPL HCPL HCPL HCPL ns ns V CM = V HCPL 5, V/µs HCPL7 V CM = 5V HCPL, HCPL8 V CM =,V HCPL 5, HCPL9 5, V CM = V HCPL 5, V/µs HCPL7 V CM = 5V HCPL, HCPL8 V CM =,V HCPL 5, HCPL9 5, HCPLXX Rev...9
Transfer Characteristics (T A = - C to +85 C unless otherwise specified.) Symbol DC Characteristics Test Conditions Min. Typ.* Max. Unit µa. V I OH High Level Output Current V CC = 5.5V, V O = 5.5 V, I F = 5µA, V E =.V () V OL Low Level Output Voltage V CC = 5.5V, I F = 5mA, V E =.V, I OL = ma () I FT Input Threshold Current V CC = 5.5V, V O =.V, V E =.V, I OL = ma 5 ma Isolation Characteristics (T A = - C to +85 C unless otherwise specified.) Symbol Characteristics Test Conditions Min. Typ.* Max. Unit I I-O Input-Output Insulation Leakage Current *All typical values are at V CC = 5 V, T A = 5 C Relative humidity = 5%, T A = 5 C, t = 5s, V I-O = VDC () V ISO Withstand Insulation Test Voltage R H < 5%, T A = 5 C, I I-O µa, t = min. ().* µa 75 V RMS R I-O Resistance (Input to Output) V I-O = 5V () Ω C I-O Capacitance (Input to Output) f = MHz (). pf Notes:. The V CC supply to each optoisolator must be bypassed by a.µf capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V CC and GND pins of each device.. Enable Input No pull up resistor required as the device has an internal pull up resistor.. t PLH Propagation delay is measured from the.75ma level on the HIGH to LOW transition of the input current pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse.. t PHL Propagation delay is measured from the.75ma level on the LOW to HIGH transition of the input current pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 5. t r Rise time is measured from the 9% to the % levels on the LOW to HIGH transition of the output pulse.. t f Fall time is measured from the % to the 9% levels on the HIGH to LOW transition of the output pulse. 7. t ELH Enable input propagation delay is measured from the.5v level on the HIGH to LOW transition of the input voltage pulse to the.5v level on the LOW to HIGH transition of the output voltage pulse. 8. t EHL Enable input propagation delay is measured from the.5v level on the LOW to HIGH transition of the input voltage pulse to the.5v level on the HIGH to LOW transition of the output voltage pulse. 9. CM H The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., V OUT >.V). Measured in volts per microsecond (V/µs).. CM L The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., V OUT <.8V). Measured in volts per microsecond (V/µs).. Device considered a two-terminal device: Pins,, and shorted together, and Pins 5,, 7 and 8 shorted together. HCPLXX Rev...9 5
Typical Performance Curves (HCPL, HCPL and HCPL only) IF FORWARD CURRENT (ma) ITH INPUT THRESHOLD CURRENT (ma) Fig. Forward Current vs. Input Forward Voltage....9......5..7 5 T A = 7 C T A = 5 C T A = 85 C V F FORWARD VOLTAGE (V) Fig. Input Threshold Current vs. Temperature V CC = 5V V O =.V R L = 5Ω R L = KΩ T A TEMPERATURE ( C) T A = - C T A = C Vo OUTPUT VOLTAGE (V) IOH HIGH LEVEL OUTPUT CURRENT (μa) 5 Fig. Output Voltage vs. Forward Current R L = kω R L = 5Ω 5 I F FORWARD INPUT CURRENT (ma) Fig. High Level Output Current vs. Temperature 8 T A TEMPERATURE ( C) T A = 5 C V CC = 5V V O = V CC = 5.5V V E = V I F = 5μA HCPLXX Rev...9
Typical Performance Curves (HCPL, HCPL and HCPL only) VOL LOW LEVEL OUTPUT VOLTAGE (V) TP PROPAGATION DELAY (ns).8.7..5.... Fig. 5 Low Level Output Voltage vs. Temperature. T A TEMPERATURE ( C) 9 8 7 5 V = 5.5V CC V E = V I F = 5mA I O = ma I O =.ma I O =.8mA I O = 9.mA Fig. 7 Propagation Delay vs. Temperature V = 5V CC I F = 7.5mA t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω IOL LOW LEVEL OUTPUT CURRENT (ma) TP PROPAGATION DELAY (ns) Fig. Low Level Output Current vs. Temperature 55 5 5 5 5 V = 5V CC V E = V V OL =.V I F = -5mA I F = 5mA T A TEMPERATURE ( C) Fig. 8 Propagation Delay vs. Pulse Input Current 9 8 7 5 V = 5V CC T A = 5 C t PLH R L = kω t PLH R L = 5Ω t PHL RL = 5Ω & kω T A TEMPERATURE ( C) 5 7 9 5 I F PULSE INPUT CURRENT (ma) HCPLXX Rev...9 7
Typical Performance Curves (HCPL, HCPL and HCPL only) PWD PULSE WIDTH DISTORTION (ns) Fig. 9 Typical Enable Propagation Delay vs. Temparature te ENABLE PROPAGATION DELAY (ns) 9 8 7 5 V = 5V CC V EH = V V EL = V I F = 7.5mA t ELH R L = kω t ELH R L = 5Ω t EHL RL = 5Ω & kω Fig. Typical Rise and Fall Time vs. Temperature T A TEMPERATURE ( C) T A TEMPERATURE ( C) Fig. Typical Pulse Width Distortion vs. Temperature 5 V = 5V CC I F = 7.5mA tf FALL TIME (ns) 8 V = 5V CC I F = 7.5mA t r R L = kω t r R L = 5Ω t f R L = 5Ω & kω 5 R L = kω 5 5 R L = 5Ω T A TEMPERATURE ( C) HCPLXX Rev...9 8
Typical Performance Curves (HCPL7, HCPL8 and HCPL9 only) IF FORWARD CURRENT (ma) IOH HIGH LEVEL OUTPUT CURRENT (na) Fig. Input Forward Current vs. Forward Voltage....8 8 T A = 85 C T A = C T A = - C T A = C T A = 5 C.9......5..7 V F FORWARD VOLTAGE (V) Fig. High Level Output Current vs. Ambient Temperature V O = V CC = 5.5V V E = V (Single Channel Only) I F = 5 μa ITH INPUT THRESHOLD CURRENT (ma) IOL LOW LEVEL OUTPUT CURRENT (ma) Fig. Input Threshold Current vs. Ambient Temperature.5..5..5 V CC = 5.5V V O =.V R L = kω R L = 5Ω R L = kω. 5 5 5 T A AMBIENT TEMPERATURE ( C) Fig. 5 Low Level Output Current vs. Ambient Temperature V = 5.5V CC V E = V (Single Channel Only) V OL =.V I F = 5 5mA T A AMBIENT TEMPERATURE ( C) T A AMBIENT TEMPERATURE ( C) VOL LOW LEVEL OUTPUT VOLTAGE (V)..5.... Fig. Low Level Output Voltage vs. Ambient Temperature V = 5.5V CC V E = V (Single Channel Only) I F = 5mA I O =.ma I O =.8mA I O = 9.mA I O = ma PWD PULSE WIDTH DISTORTION (ns) 7 5 Fig. 7 Pulse Width Distortion vs. Ambient Temperature V = 5V CC I F = 7.5mA RL = kω RL = kω RL = 5Ω. T A AMBIENT TEMPERATURE ( C) T A AMBIENT TEMPERATURE ( C) HCPLXX Rev...9 9
Typical Performance Curves (HCPL7, HCPL8 and HCPL9 only) TP PROPAGATION DELAY (ns) 8 V = 5V CC I F = 7.5mA Fig. 8 Propagation Delay vs. Ambient Temperature t PLH RL = kω t PHL RL = 5Ω, kω, kω t PLH RL = kω t PLH RL = 5Ω T A AMBIENT TEMPERATURE ( C) tr RISE TIME (ns) 5 5 5 5 V = 5V CC I F = 7.5mA Fig. 9 Rise and Fall Times vs. Ambient Temperature t r RL = kω t f RL = 5Ω, kω, kω t r RL = kω t r RL = 5Ω T A AMBIENT TEMPERATURE ( C) 7 5 tf FALL TIME (ns) HCPLXX Rev...9
Pulse Gen. t f = t r = 5 ns Z O = 5 Ω Input Monitor (I F) 7Ω +5V Pulse Gen. Z O = 5 Ω t f = t r = 5 ns Dual Channel I F V CC 8 V CC 8 Input.μf 7 R L Monitoring Bypass Node 7 Output (V O) C L R M GND 5 5 GND Test Circuit for HCPL, HCPL and HCPL Pulse Generator tr = 5ns Z O= 5Ω 7.5 ma V CC 8 7 Input Monitor (V E).μf bypass Test Circuit for HCPL7, HCPL8 and HCPL9 R L +5V Output (V O) Input (V ) E tehl Output (V O) Input (I F) t PHL Output (V O) Output (V ) O Fig. Test Circuit and Waveforms for t PLH, t PHL, t r and t f. R L +5 V.μF Bypass Output V O Monitoring Node C L* telh tf. V.5 V.5 V 9% % t PLH tr I F = 7.5 ma I =.75 ma F.5 V C L GND 5 Fig. Test Circuit t EHL and t ELH. HCPLXX Rev...9
VCM V 5V VO V FF A B I F Peak V CC GND V CM Pulse Gen Switching Pos. (A), I = F V O (Min) V O (Max) 8 7 5.μf bypass Test Circuit for HCPL, HCPL, and HCPL 5Ω +5V Output (V O) CM H VO.5 V Switching Pos. (B), I = 7.5 ma F CM L Fig. Test Circuit Common Mode Transient Immunity (HCPL, HCPL and HCPL) HCPLXX Rev...9
VCM V Peak.V VO I F V FF B A Switching Pos. (A), I = F V O (Min) Dual Channel V CC 8 7 GND 5 V CM + Pulse Generator Z O = 5 Ω R L.μF Bypass Test Circuit for HCPL7, HCPL8 and HCPL9 +.V Output V O Monitoring Node CM H V O (Max) VO.5 V Switching Pos. (B), I = 7.5 ma F CM L Fig. Test Circuit Common Mode Transient Immunity (HCPL7, HCPL8 and HCPL9) HCPLXX Rev...9
8-Pin Small Outline.75 (.99).55 (.9). (.). (.5).5 (.7) HCPLXX Rev...9
Ordering Information Option Order Entry Identifier Description No Suffix HCPL Shipped in tubes (5 units per tube) V* HCPLV IEC77-5- approval R HCPLR Tape and Reel (5 units per reel) RV* HCPLRV IEC77-5- approval, Tape and Reel (5 units per reel) *Available for HCPL, HCPL, HCPL only. Marking Information V 5 Definitions Fairchild logo Device number VDE mark indicates IEC77-5- approval (Note: Only appears on parts ordered with VDE option See order entry table) One digit year code, e.g., 5 Two digit work week ranging from to 5 Assembly package code X YY S HCPLXX Rev...9 5
Carrier Tape Specifications 8. ±..5 ±.. ±.5. MAX. ±. 8. ±.. MAX. ±. User Direction of Feed Ø.5 MIN.75 ±. 5.5 ±.5. ±. 5. ±. Ø.5 ±./- HCPLXX Rev...9
Reflow Profile Temperature ( C) 8 8 TP TL Tsmax Tsmin Max. Ramp-up Rate = C/S Max. Ramp-down Rate = C/S Preheat Area Time 5 C to Peak Time (seconds) Profile Freature Pb-Free Assembly Profile Temperature Min. (Tsmin) 5 C Temperature Max. (Tsmax) C ts tl tp Time (t S ) from (Tsmin to Tsmax) Ramp-up Rate (t L to t P ) seconds C/second max. Liquidous Temperature (T L ) 7 C Time (t L ) Maintained Above (T L ) Peak Body Package Temperature Time (t P ) within 5 C of C Ramp-down Rate (T P to T L ) Time 5 C to Peak Temperature 5 seconds C + C / 5 C seconds C/second max. 8 minutes max. HCPLXX Rev...9 7
Fairchild Semiconductor Corporation HCPLXX Rev...9 www.fairchildsemi.com 8