CHAPTER 1 CHAPTER Conventional delta-sigma modulators 1.0 This Chapter presents the traditional first- and second-order DSM. The main sources for non-ideal operation are described together with some commonly used techniques to improve the performance. All the theory in this Chapter is collected from references [1,5,6,7,8,9]. 1.1 The first order DSM Quantization of amplitude and sampling in time are at the hart of all ADCs. The transfer function of an ADC or quantizer is nonlinear (Fig. 1.1), and in order to achieve a simple mathematical description of the modulator, we may treat the quantization error as a random variable. For most busy input signals we may consider this random variable to be uncorrelated with the input signal and to have a constant probability density function (pdf) over the interval ± /2 where is the quantization level spacing. In many cases, reported experiments have confirmed these properties, but there are two important instances where they may not apply; when the input is constant, and when it changes regularly by a multiple or submultiples of, as can happen in feedback circuits. As a constant pdf random output quantization levels quantization error thresholds input Fig. 1.1 The input-output relationship of a quantizer variable, the root mean square value (RMS) of the quantization error e n [- /2, /2 will be e 2 1 rms 2 = -- e 2 de = 2 2 -----, (1.1) 12 and we will assume that the spectral density is constant for all frequencies. 5
Chapter 1 Conventional delta-sigma modulators f s a) in _ ( )dt ADC out DAC e n b) x n _ z -1 quantizer y n Fig. 1.2 a) The first-order DSM principle. b) Linearized mathematical model In Fig. 1.2a, the first-order DSM principle is illustrated. The input to the circuit is fed to the quantizer via an integrator, and the quantized output is then fed back and subtracted from the input. The feedback forces the average value of the quantized output to track the average input. Any differences between them accumulates in the integrator and corrects itself. Unless otherwise specified, the quantizer gain, defined as the level spacing divided by the threshold spacing, will be unity for all quantizers described in this thesis. In Fig. 1.2b a commonly used simplified model of the DSM is shown. The circuit is linearized by representing the quantizer by the additive noise source e n, and the integrator is represented as an analog discrete-time accumulator. By considering the ideal behavior, the DAC may be disregarded. From the figure we see that the modulator output may be expressed y n = x n 1 ( e n e n 1 ), (1.2) i.e the signal passes unchanged except a unit delay while the quantization error is differentiated. Due to the differentiation, low frequency quantization noise components will be attenuated. The spectral density of the output quantization noise given by may be expressed as e o n = e n e n 1, (1.3) Nf () = 2e rms 2 f sin s π-- f f s. (1.4) In Fig. 1.5a the theoretical output noise spectral density is shown for an example where =1 and the sampling frequency is 2MHz. As we see, the quantization noise is shifted up in frequency. For the maximum signal frequency f max, the total in-band noise power is given by integrating Eq. (1.4) over the frequency range 0 - f max. For f s >>f max the resulting in-band noise power will, by using Eq. (1.1), be 2f max f s n 2 2 π o 2 3 =. (1.5) 36 In Fig. 1.5b n o is plotted as a function of f max for =1 and f s =2MHz. As we see, the in-band noise power is significantly reduced for low signal bandwidths. The improvement in resolution over ordi- 6
1.2 Errors and noise sources in the first-order DSM nary oversampling do however require that the DSM output is decimated by a sharp digital low-pass filter. From Eq. (1.5), the SQNR of the modulator will be 2f max SQNR 20 SR --------- o, (1.6) 2 2 10 2 π 2 3 = log log 36 f s where RS o is the output signal range which by the use of a unity gain quantizer will be equal to the input signal range. From Eq. (1.6) we have that each doubling of the oversampling ratio (OSR) increases the SQNR by 9dB. An alternative way to increase the SQNR is by decreasing the quantization spacing, or increasing the input signal range. By doing so, we have to increase the number of quantization thresholds, and the result is a SQNR gain of 6dB for each doubling of the number of effective quantization thresholds which in turn doubles the output word-length of the modulator. 1.2 Errors and noise sources in the first-order DSM So far, we have treated the quantization error as uncorrelated with the input signal. In a practical modulator, this assumption will not always be sufficient. In addition, the Σ modulator is an analog device where the effect of inaccurate operation must be considered. In the following sections, the main limiting error and noise sources will be presented. Pattern noise For DC or slowly varying inputs, the output will bounce between two levels, keeping its mean equal to the input. The output sequence may be repetitive and the frequency of this sequence will be determined by the input DC level. When the repetition frequency lies in the signal band, the modulation is noisy, but when it does not, the modulation is quiet. Fig. 1.3a (scanned from reference [1]) shows how the in-band noise power depends on the value of the DC input for a DSM with quantization levels =±1 and a low OSR. Fig. 1.3b (scanned from reference [5]) shows the corresponding noise for a high OSR, and =0,1. There are peeks of noise adjacent to integer divisions of the space between levels, elsewhere the noise is small. This structure of the quantization error is called pattern noise, and it will appear as spurious tones/peaks in the modulator output spectrum. The larger peeks in Fig. 1.3 can far exceed the expected noise level calculated from Eq. (1.5), and the following properties of pattern noise are noteworthy: The height and width of each peak are inversely proportional to the OSR. The height and width are also inversely proportional to the denominator of the fraction that describe the position of the peak within the quantization interval relative to the level spacing. About half the total power is in the end peaks, one-sixteenth in the center peak. The pattern noise may however be randomized by injecting a signal with frequency well above the signal band at the input. This signal, also called a dither signal smears out the output power spectrum, and as a consequence, it reduces the energy of the noise peeks/tones. For one-bit first-order -Σ conversion, the pattern noise problem may be significant as the in-band pattern noise power may be large compared to the signal power. If not the full output signal range is used, the output signal range may however be biased and located well away from the main noise peaks to reduce this problem. 7
Chapter 1 Conventional delta-sigma modulators a) in-band noise power (db) DC input level b) in-band noise power (db) Fig. 1.3 DC input level Simulated output in-band noise v.s input signal DC value. Arrows indicates the theoretical in-band noise levels calculated by Eq. (1.5). a) Low OSR. b) High OSR DAC output levels The main problem for multi-bit DSM operation is inaccurate DAC output levels. From Fig. 1.2a we notice that all errors introduced in the feedback path will add directly to the signal. In addition, since y n is close to x n in a multi-bit DSM, the correlation between the input and the DAC error will be large. Thus the DAC error will usually have a large baseband energy content and will generate harmonic distortion. The DAC output levels must therefore be positioned with an accuracy better than the overall SQNR which for high resolution conversion normally will require external components and/or trimming. This will however raise the cost of the system considerably. The fact that the DAC output settling time must be very low (less than 1/f s ), eliminates the use of most ordinary high resolution DAC architectures. For single-bit DSM operation only two DAC output levels are required, and any misplacement is equivalent to a bias the modulator input signal. The only requirement will therefore be properly placed DAC output levels to accommodate the input signal range. ADC thresholds The quantizer in the multi-bit DSM usually takes the form of a flash ADC. Misplaced ADC thresholds may be regarded as a non-linearity of its gain, but due to the high gain feedback, such errors have little effect on the baseband properties of the modulator. Misplacing the thresholds by as much as a quarter of their spacing is usually tolerable. For single-bit DSM operation, the only requirement on the single threshold placement is to prevent overloading in the integrator. ADC overloading The signal oscillations internal in the integrator uses up some of the dynamic range of the circuit, and if the ADC is not to overload, the input signal range (SR i ) must not exceed the maximum and 8
1.3 The second-order DSM minimum ADC output levels. If a large input causes the ADC to overload, the modulator noise will increase rapidly. Simulations shows that the excess noise introduced into larger signals appears as odd-order harmonic distortion of sine waves. The excess noise will decrease with increased OSR but increases with the frequency of the applied sine wave. Integrator errors In the integrator, there are several noise sources, but small errors introduced by the integrator will generally due to the high gain feedback have little impact on the overall modulator performance. For most applications a 10% change of integrator gain will be tolerable. Integrator leakage decreasing the integrator DC gain to at least the OSR will neither be a problem. The integrator slew rate will however be a limiting factor for high sampling frequency operation. Most DSM integrators are implemented by the use of switched capacitor (SC) techniques, and linear capacitors and a non-overlapping two-phase clock are therefore required. To reduce the effect of power supply noise, charge injection and clock feedtrough, a fully differential architecture are normally used. The SC technique is very little sensitive to clock jitter, but to achieve a low kt/c level, there will be a minimum limit on the capacitor values. For high SNR operation the minimum value may typically be in the 10pF range. Due to this constraint, there will be a trade-off between high speed operation combined with a low kt/c level, and low power consumption. It should be mentioned that in a DSM, the main power consumer will normally be the integrator, but in a complete Σ converter, the decimator power consumption will dominate. Implementation constraints As previously stated, by using SC techniques in the DSM, linear capacitances are required, and the SC-DSM can generally not be implemented in the least expensive standard digital CMOS process since an extra poly-layer will be required. In addition, as an voltage-mode device, the SC-DSM is not well-suited for low power supply operation. With 3.3V likely to become the future industrial standard, process parameters such as threshold voltage will be chosen to optimize digital performance and so voltage domain behavior will suffer as a consequence. To overcome this limitations, switched current (SI) techniques have been proposed (reference [6]), but so far no high-resolution SI-DSMs have been reported due to several implementation difficulties associated with this new technique. 1.3 The second-order DSM x n - z -1 - z -1 e n quantizer y n Fig. 1.4 A linearized illustration of the traditional double-loop DSM. A efficient way to increase the SQNR of a DSM is to increase the order of the low-pass filter in the feedback loop. By doing so, the quantization error will also be significantly less correlated with the input signal, and problems due to pattern noise will be small. The most straight-forward second-order architecture is the double-loop modulator is shown in Fig. 1.4. As in Fig. 1.2b the integrators are represented as discrete-time accumulators, and the DAC in the feedback loop is disregarded. 9
Chapter 1 Conventional delta-sigma modulators From the figure we notice that the output may be expressed as y i = x i 1 ( e i 2e i 1 e i 2 ). (1.7) i.e. the signal passes unchanged except form a unit delay, but the quantization error is double differentiated. The spectral density of the output quantization noise given by may be expressed as e o n = e n 2e n 1 e n 2, (1.8) Nf () = e rms 2 f s 2 π-- f sin 2. (1.9) In Fig. 1.5a, an example illustrating the output noise spectral density for =1 and f s =2MHz is shown. Compared to the first-order spectrum, the quantization noise is shifted even more up in frequency and f s 50 100 0 0 50 0 Output spectral density (W/Hz) (db) 150 200 I II In band power (W) (db) 100 150 200 I II 250 250 300 10 0 10 1 10 2 10 3 10 4 10 5 10 6 Frequency (Hz) 300 10 0 10 1 10 2 10 3 10 4 10 5 10 6 Max signal frequency (Hz) a) b) Fig. 1.5 a) Quantization noise spectral density plot. b) In band quantization noise power. a/b) 0: unshaped quantization noise, I: first-order DSM output, II: second-order DSM output. f s =2MHz, =1 out of the signal band. For f s >>f max the resulting in-band noise power may, by using Eq. (1.1), be expressed as 2f max f s n 2 2 π o 4 5 =. (1.10) 60 In Fig. 1.5b, n o is plotted as a function of f max for =1 and f s =2MHz. As we see, compared to the first-order modulator, the in-band noise power is significantly reduced for low signal bandwidths. The SQNR of the modulator will be SQNR 20 SR --------- o, (1.11) 2 2 10 2 π 4 2f max 5 = log log 60 f s and by doubling the OSR, the SQNR will increase by 15dB. As in the first-order DSM, the SQNR may also be increased by 6dB by doubling SR o or halving, which normally will require multi-bit quantization. 10
1.4 Errors and noise sources in the second-order DSM By simulating the ideal first- and second-order DSM given by Fig. 1.2b and Fig. 1.4 in the high-level language Simula [7], we may study the behavior of the perfect first- and second-order DSM. In Fig. 1.6, the FFT analysis of the respective first- and second-order output sequences are shown for a single sinusoidal input signal at a frequency of 100Hz. For both DSMs, a commonly used one-bit quantizer is applied, and for the first-order DSM, the input signal range is therefore limited to [ /2, /2]. For the second-order DSM the input signal range is limited to [- /4, /4] due to effects described next. As we see from the plots, the output power is shifted up in frequency according to the 0 0 20 20 40 Normalized amplitude (db) 40 60 80 Normalized amplitude (db) 60 80 100 120 140 100 160 120 10 1 10 2 10 3 10 4 10 5 10 6 Frequency (Hz) Fig. 1.6 180 10 1 10 2 10 3 10 4 10 5 10 6 Frequency (Hz) a) b) FFT analysis of ideal DSM output sequences. f s =2MHz, =1. Both plots are normalized to let 0dB represent max input signal amplitude. a) First-order DSM b) Second-order DSM theory. For the first-order DSM spectrum we notice some low and medium frequency pattern noise. It is hard to explain the flat part of the spectrum for the highest frequencies in the second-order plot. 1.4 Errors and noise sources in the second-order DSM As in the first order DSM, the second-order DSM is an analog device, and in a practical application we have to consider the non-ideal behavior. In the following sections the main error and noise sources are presented. Pattern noise The inner feedback loop will add the quantization error to the integral of the input. The net impact from the quantization error on the signal will therefore be a mixture of the quantization error and its derivative. The result is a significantly lower correlation between the input signal, and the quantization error, and for most applications, pattern noise will be of no concern. As we see from the example in Fig. 1.6b, the power spectrum is quite smooth for low and medium frequencies. DAC output levels As in the first-order modulator, errors introduced by inaccurate DAC output levels will add directly to the signal, and the DAC accuracy requirement will be almost the same as in the first-order modulator. Due to the inner loop, DAC introduced errors will be somewhat less correlated with the input signal, and harmonic distortion will be slightly improved. ADC thresholds Due to the high gain feedback, errors introduced by misplaced ADC thresholds will have little impact on the baseband properties of the modulator. The ADC level accuracy requirements will be 11
Chapter 1 Conventional delta-sigma modulators almost the same as for the first-order modulator. ADC overloading In the double-loop modulator, the signal oscillations in the second integrator will be considerably more complex and have a larger amplitude than in the first-order DSM. Due to this oscillations, ADC overloading must be carefully considered, and the input signal range must be properly restricted to reduce this effect. By using a single-bit quantizer in the double-loop DSM, the modulator will, in principle, be overloaded for all input signal except those with zero amplitude. The noise introduced by ADC overloading will have the same structure as in the first-order DSM, and appear as odd-order harmonics distortions of sine waves. By looking at Fig. 1.6b, we notice the noise peak at 3 100Hz which is the result of modest ADC overloading for the single sinusoidal input signal with amplitude /4. Integrator errors The second-order modulator contains two separate integrators which determine their respective loop gains. The outer loop determine the low-frequency properties of the modulator, while the inner loop serves to stabilize the modulator and determine the high-frequency properties. Matching their gains to ±5% is usually satisfactory for high resolution operation. The second-order modulator is not as stable as the first-order, and a 30% increase in loop gain and /or additional delay in the loop may cause instability. Leakage in the integrators is somewhat more serious than for the first-order DSM, as it may cause the output to settle into regular patterns. This oscillations is most noticeable for slowly varying input signals in the center of the dynamic range. When the modulator starts oscillating it will be less sensitive to input variations, and a dead zone occur. It is shown that for the width of the dead zone to be less than twice the quantization noise RMS value, it will be required that the DC gain H 0 of the integrators must be ( OSR) 5 4. (1.12) As in the first-order DSM there will be a trade-off between high-speed operation combined with a low kt/c level and low power consumption. Due to the double feedback, noise introduced by the inner-loop integrator will however be first-order shaped. In the second-order DSM the slew rate of the integrators will be even more critical for high speed operation as they operates in series. Implementation constraints Same as for the first-order DSM. H 0 1.5 Improved architectures In order to overcome some of the above listed problems in the traditional DSM, several alternative architectures have been proposed. In the following, two alternative architectures improving the resolution, and stability of the DSM is presented. Cascaded modulators To increase the dynamic range, and decrease the probability of overloading and instability in the double-loop second-order DSM, the cascaded or MASH [8] architecture have been presented. The second-order MASH DSM may be described as a first-order DSM where the quantization error is feed to another first-order DSM which output is digitally differentiated, and added to the original output (Fig. 1.7). 12
1.5 Improved architectures If the two stages are perfectly matched, the quantization error produced by the first stage will be canceled by the second-stage, and the net quantization error will be the double differentiated error from the second-stage quantizer. Although we may use single-bit quantizers in both stages, the output will be two bit, and the input signal range may be increased to ± /2 without any risk of overloading _ z -1 z -1 _ -e n _ εn -2ε n-1 ε n-2 ε n -e n-1 e n-2 x n _ z -1 z -1 x n-2 e n-1 -e n-2 x n-1 ε n -2ε n-1 ε n-2 e n Fig. 1.7 A linearized illustration of the second-order MASH DSM the ADCs. Half the output signal range is however reserved for excess oscillations so the effective output signal range itself will not be increased, and Eq. (1.11) may still be used to calculate the SQNR. The problem with the MASH architecture is the need for accurate component matching between the two stages. Output level mismatches between the two DACs will make the two loop gains diverge, and the first-order quantization noise will leak through the second-stage. To completely cancel the first-order quantization noise it will be required that the tranferfunction of the first-stage integrator matches the tranferfunction of the ideal digital differentiator in the second-stage. It can therefore be proven that the baseband noise properties will mainly depend on the accuracy of the first-stage integrator, and the design of this block may be difficult. It is shown that particularly the phase error of the first integrator can increase the noise dramatically. The resulting decrease in SQNR is particularly great when the oversampling ratio exceeds 100. The required op-amp gain is about 10 times higher than for a single stage configuration. Most significant bit feedback Multi-bit operation combined with simple DA conversion may be achieved by letting the DAC input only be the most significant bit of the multi-bit ADC output. The SQNR will then be the same as for a conventional multi-bit DSM although a single-bit DAC is used. Since the large part of the signal given by the rest of the ADC output bits is not processed by the loop filter, an external digital filter must follow as illustrated in Fig. 1.10a. In the figure, the loop filter is represented by the general tranferfunction I(z), and the digital filter transfer function must then be equal to the inverse filter transfer function. To verify the correct operation we may look at the linearized and Z-transformed representation illustrated in Fig. 1.10b. The coarse quantized signal U(z) will then be given by Uz () = Iz ()Xz E 1 () z ---, (1.13) 1 Iz () where E 1 (z) represents the coarse quantization error. The finer quantized and digitally filtered signal V(z) may be written as Xz () E Vz () 1 () z E ----- m () z = -, (1.14) 1 Iz () Iz () 13
Chapter 1 Conventional delta-sigma modulators a) X(z) - I(z) m-bit ADC 1-bit DAC m-bit msb 1/I(z) Y(z) E m (z) 1/I(z) b) X(z) - I(z) E 1 (z) U(z) V(z) Y(z) Fig. 1.10 a) A multi-bit DSM with single-bit feedback. b) Linearized mathematical equivalent where E m (z) is the finer quantization error. From this, the overall output will be E Yz () Uz () Vz () Xz () m () z = = -. (1.15) Iz () As we see, the net quantization error will be the finer quantization error produced by the multi-bit quantizer, and an increase in SQNR of 6dB for each extra ADC output bit will follow. Noise introduced by misplaced ADC levels will due to the high-pass filter 1/I(z) have little impact on the baseband properties of the modulator. If a higher-order loop-filter is used, the stability of the modulator will however not be improved since the feedback is single-bit. In reference [9], this problem is solved, but the resulting modulator architecture is somewhat large and complex. Due to the high speed requirement, a flash type ADC will normally be preferred. 14