Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input NAND gates. They perform the Boolean function Y = A B or Y = A + B in positive logic. The SNHC00 is characterized for operation over the full military temperature range of C to 12 C. The SN7HC00 is characterized for operation from 0 C to C. SNHC00... J OR W PACKAGE SN7HC00... D, N, OR PW PACKAGE (TOP VIEW) GND 1 2 7 1 1 12 11 10 9 V CC Y B A Y SNHC00... FK PACKAGE (TOP VIEW) V CC FUTION TABLE (each gate) INPUTS OUTPUT A B Y H H L L X H 2 1 20 19 1 7 17 1 1 1 91011121 Y B X L H GND Y A logic symbol 1 2 A B 9 10 12 1 & 11 Y Y No internal connection This symbol is in accordance with ANSI/IEEE Std 91-19 and IEC Publication 17-12. Pin numbers shown are for the D, J, N, PW, and W packages. logic diagram (positive logic) A B Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Insuments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Insuments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Insuments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS 72 1
absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC.......................................................... 0. V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note 1).................................... ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note 1)................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±2 ma Continuous current through V CC or GND................................................... ±0 ma Package thermal impedance, θ JA (see Note 2): D package.................................. 127 C/W N package................................... 7 C/W PW package................................ 170 C/W Storage temperature range, T stg................................................... C to 10 C Sesses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are sess ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 1, except for through-hole packages, which use a ace length of zero. recommended operating conditions SNHC00 SN7HC00 MIN NOM MAX MIN NOM MAX Supply voltage 2 2 V = 2 V 1. 1. VIH High-level input voltage =. V.1.1 V = V.2.2 = 2 V 0 0. 0 0. VIL Low-level input voltage =. V 0 1. 0 1. V = V 0 1. 0 1. VI Input voltage 0 0 V VO Output voltage 0 0 V = 2 V 0 1000 0 1000 tt Input ansition (rise and fall) time =. V 0 00 0 00 ns = V 0 00 0 00 TA Operating free-air temperature 12 0 C 2 POST OFFICE BOX 0 DALLAS, TEXAS 72
elecical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 2 C SNHC00 SN7HC00 MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 1.99 1.9 1.9 IOH = 20 µa. V..99.. VOH VI = VIH or VIL V.9.999.9.9 V IOH = ma. V.9..7. IOH =.2 ma V...2. 2 V 0.002 0.1 0.1 0.1 IOL = 20 µa. V 0.001 0.1 0.1 0.1 VOL VI = VIH or VIL V 0.001 0.1 0.1 0.1 V IOL = ma. V 0.17 0.2 0. 0. IOL =.2 ma V 0.1 0.2 0. 0. II VI = or 0 V ±0.1 ±100 ±1000 ±1000 na ICC VI = or 0, IO = 0 V 2 0 20 µa Ci 2 V to V 10 10 10 pf switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 2 C SNHC00 SN7HC00 MIN TYP MAX MIN MAX MIN MAX 2 V 90 1 11 tpd A or B Y. V 9 1 27 2 ns V 1 2 20 2 V 7 110 9 tt Y. V 1 22 19 ns V 1 19 1 operating characteristics, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance per gate No load 20 pf POST OFFICE BOX 0 DALLAS, TEXAS 72
PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 0 pf (see Note A) Input tplh tphl 0 V LOAD CIRCUIT In-Phase Output 90% 90% VOH VOL Input 90% 90% 0 V Out-of-Phase Output tphl 90% tplh VOH 90% VOL VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbiarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, = ns, = ns. C. The outputs are measured one at a time with one input ansition per measurement. D. tplh and tphl are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 72
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