4 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 3, NO., ARCH 5 Efficient Slew-Rate Enhanced Operational Transconductance Amplifier Xiao-Peng Wan, Fei-Xiang Zhang, Shao-Wei Zhen, Ya-Juan He, and Ping Luo Abstract Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product (GBW), slew rate (SR), and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier (OTA) with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a.5 μm complementary metal oxide semiconductor (COS) process. The simulation results show that the SR is 4.54 V/μs, increased by 8.5 times than that of the conventional design, while the current dissipation is only 87.3%. Index Terms Efficient, gain-bandwidth product, operational transconductance amplifier, slew rate.. Introduction It is well known that the amplifier is the fundamental module in most analog and mixed circuits. And the operational transcondutance amplifier (OTA) [] is one of the most widely used, which is usually used to drive a capacitive load or a pass transistor in a low dropout anuscript received ay 4, 4; revised August 8, 4. This work was supported in part by the National Natural Science Foundation of China under Grant No. 6747 and the National Key Laboratory of Analog Integrated Circuit under Grant No. 94c9534c948. X.-P. Wan and F.-X. Zhang are with the School of icroelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 654, China (e-mail: wxp36@63.com; fx.zhang@foxmail.com). S.-W. Zhen is with the School of icroelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 654, China (Corresponding author e-mail: swzhen@uestc.edu.cn). Y.-J. He and P. Luo are with the School of icroelectronics and Solid-State Electronics, University of Electronic Science and Technology of China, Chengdu 654, China (e-mail: yajuan.he@gmail.com; pingl@uestc.edu.cn). Digital Object Identifier:.3969/j.issn.674-86X.5..4 regulator (LDR). But due to the limitation of tail current, the driving capability of conventional OTA is weak. And improving the slew rate (SR) is inevitably at the cost of more static power consumption. Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with high gain-bandwidth product (GBW), SR, and at the same time very low static power dissipation is growing. Slew rate enhancement (SRE) techniques have been developed in recent years to solve the problem. Different techniques have been suggested. For example, the dynamic biasing technique [] [4] was used to enhance the SR by increasing the bias current of the input differential pair when the differential-mode input voltage was large. Another differential pair was added to sense the input voltage. In [5] [8], auxiliary branches carried the extra current required by charging/discharging the load during slewing and the core operational amplifier (op amp) would remain unaffected. Both the main amplifier and SRE op amp sensed the same input signal. The SRE amplifier then needed to detect the slewing condition and inject an extra current to the output node. In [9] and [], the class-ab input stage was used to produce a larger dynamic output current compared with a common differential input pair. In this paper, a SR enhancement structure is proposed, which transforms a conventional OTA into an efficient one without the static power dissipation or input capacitance increase. To increase the SR, a sensing resistor in series with the diode connecting the metal oxide semiconductor (OS) transistors of the current mirror is applied. Unlike the diode configured OS transistor of which the voltage drop is in proportion to the square root of current, it is a linear relationship between the voltage across the resistor and the current through it. Therefore, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage by the single-transistor amplifier in the current mirror. The proposed structure, which will be shown below, leads to the essential SR and GBW improvements. The paper is organized as follows. Section briefly describes the performance of the conventional OTA and the limitation. The proposed SRE technique with the details of its circuit implementation is brought in Section 3. Section 4 presents the simulation results. The paper is concluded in Section 5.
WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier 5. Conventional OTA The conventional OTA is shown in Fig.. The p-channel differential input stage comprised of 3L and 3R converts the input voltage into currents. irrors consisting of L, L and R, R mirror the currents to the output stage. The current generated by the mirror of L and L is then mirrored to the output port via the mirror formed by 4L and 4R. The mirror gain factor, K, indicates the current gain in the mirrors formed by L, L and R, R with the following relations: K = I I = β β = W L W L () where subscripts and indicate that the parameters are corresponding to L or R and L or R, respectively. And β=μc ox W/L, where μ is the electron mobility and C ox is the unit-area capacitance of gate oxide, and W/L is the aspect ratio of the OS transistor. flowing through each branch from the power supply to the ground, which is given by P = V I + K (5) static dd bias where V dd is the power supply voltage. It is obvious that increasing the mirror gain factor K will enhance the SR and GBW at the cost of increasing the static power dissipation. Hence, a trade-off between the driving capability and static power dissipation in the conventional OTA design is required. 3. Proposed SRE OTA As shown in Fig., the common current mirrors in the conventional OTA are modified by adding two resistors and a bias current sink to each one. This structure reinforces the SR, which will be hereinafter referred to as the SR enhanced structure or SRE mirror. 4L 4R I bias 4L 4R V N 3L 3R V P V out V N 3L I bias 3R I V P = I L 4 L V out L L R R R L R L R R R R Fig.. Conventional OTA. The conventional OTA is differentiated from other amplifiers by the fact that its only high impedance node is located at the output terminal. The conventional OTA does not employ an output buffer and is, therefore, only capable of driving capacitive loads. The voltage gain of the OTA is given by V A = Kg r r () m3 o o4 where g m3 is the transconductance of the differential pair; r o and r o4 are the small signal output resistance of R and 4R, respectively; indicates that r o and r o4 are in parallel. The GBW is given as GBW = Kg C = K β I C (3) m3 load 3 bias load where C load is the load capacitance and I bias is the bias current of the differential pair. Then the SR can be expressed as SR = KI C. (4) bias It can be seen that for a certain bias current, the GBW and SR increase linearly with the scaling factor K of the current mirror. The static power dissipation P static is the sum of the product of the power supply voltage with the currents load L I bias, L L R I bias, R R Fig.. Proposed SRE operational transconductance amplifier. In a common current mirror, the output current depends linearly on the input current simply because the non-linearity of the amplifying OS transistor L is compensated by the non-linearity of the diode-connected OS transistor L. In order to take advantages of the non-linearity of the amplifying OS transistor L to generate more output current, the non-linearity of the diode-connected OS transistor must be broken. Take the SRE enhanced mirror for example. The resistor R L in series with the diode-connected OS transistor L is applied to sense input current and convert it into a voltage including a term linearly depending on the input current. And the output current will include a term containing the square of input current because of the square law characteristic of the amplifying OS transistor L. The current sink I bias,l provides a constant bias current to R L and produces a voltage drop across it. Eventually, the static voltage drop across R L can be canceled out by the voltage drop across R L with an appropriate bias current, whereas the dynamic performance will not be affected. Then, we will analyze the characteristic of the SRE OTA quantitatively. The gate voltage of L is the sum of the voltage across R L and the drain-to-source voltage of
6 L minus the voltage across R L, and can be given as V = I + V + I R I R (6) gs,l L βl th, N L L bias,l L where I L is the current generated from the differential pair minus the bias current I bias,l. And then, the single-transistor amplifier L converts the gate voltage into a current which is in a square law relationship with the voltage and is given as I I I R I R L = βl[ L βl + L L bias,l L ] = K( I I ) + 3L bias,l β KI ( I )[ I R I ( R + R )] + L 3L bias,l 3L L bias,l L L β +. (7) L[ I3LRL Ibias,L ( RL RL )] JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 3, NO., ARCH 5 and exceeds the output current of the common mirror when the input current is over a certain value. And the quiescent operating point has not been affected. oreover, increasing β L and β L simultaneously, the output current also increases more quickly with the input current, of which the effect is similar to increasing R L. Decreasing the value of m/n, the quiescent operating point will be moved upwards, and the output current of SRE mirror exceeds that of the common mirror more easily with the increasing of input current, vice versa. SRE mirror R L =R L =5kΩ SRE mirror R L =R L =5kΩ SRE mirror R L =R L =kω Common mirror R L R L I bias L L I bias, L Fig. 3. Bias circuit schematic for SRE mirror. As shown in Fig. 3, the bias current of R L, which is I bias,l, is realized by mirroring the tail current. It can be seen that I bias,l =(m/n)i bias, where m/n</. As mentioned before, the bias current of R L is properly chosen to set the voltage drop across R L to be the same as that across R L at the static stage. So, R L =(n/m )R L /. Substitute it into (7), the result is I = K[ I I ( m n)] + L 3L bias β KI [ I ( mn)]( I I ) R + L 3L bias 3L bias L β. (8) L[( I3L Ibias ) RL ] As a result, the relationship between the quiescent current of L and L is I L,static = K[I 3L I bias (m/n)]=ki L, just like the common current mirror. But the value of the quiescent output current is [(n m)/n]i bias, which is less than the common mirror. And by adjusting the value of m/n, the quiescent operating point can be adjusted. Assuming R L =R L, m/n=/4, and β L =β L, Fig. 4 shows the normalized current transmission characteristic of the SRE mirror with different sensing resistances versus the common mirror. It can be seen the quiescent output current of SRE mirror is half of that of the common mirror. And when R L =R L =, the SRE mirror is similar to the common mirror, so the curve of I L versus I 3L is linear. When R L =R L, the output current increases non-linearly with the input current just as predicted qualitatively before. And the larger R L is, the more significant (I 3L I bias /) term in (8) is. Therefore, the output current increases more quickly with the input current, Fig. 4. Normalized current transmission characteristic of the SRE mirror with different sensing resistances vs. the common mirror (m/n=/4, β L =β L ). As the positive input voltage V p is much larger than the negative input voltage V n, the tail current of the differential pair flows entirely through the transistor 3L. Then (8) can be rewritten as ( ) β I = n m n KI + R I + L,max bias L L bias 8 n m nβ R K I (9) 3 L L bias which is the maximum output current of SRE mirror and also the maximum charging current of the SRE OTA. So the SR can be given as (( n m) n) KI β R I SR = bias + L L bias 8 + 3 ( ) β n m n R K I C L L bias load. () Obviously, the SR of the SER OTA can be much larger than the conventional one with the same bias current, as long as the values of R L and β L are large enough and m/n is small (the quiescent operating point moves upwards). Additionally, when the bias current is improved, the SR increases more quickly because of the I term while the bias conventional one increases linearly with I bias. Then, the static power dissipation of SRE OTA can be expressed as Pstatic = VddIbias + K + mk n. () As can be seen, when m=/k, the static power dissipation is the same as the conventional one s for any value of n.
WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier 7 When m>/k, the static power dissipation is less than the conventional one s. By increasing m and decreasing n, where n should be larger than m, P static decreases. When m approaches to infinity and n to m, P static will become the minimum value V dd I bias (+K/). When m</k, the static power dissipation is larger than conventional one s. Increasing n could decrease the dissipation as much as possible, and the limitation is V dd I bias (+K). The SR enhanced structure also changes the small signal voltage gain and GBW. The voltage gain is easy to be deduced from small signal analysis and given by V ( L ml ) m3l ( or o4r ) A = K + R g g r r. () The dominated pole is at the output terminal and given as P d =/[(r or r o4r )C L ], where r or and r o4r are the small signal output resistance of R and 4R, respectively. Eventually, GBW is given by GBW = K + R g g C. (3) L ml m3l load It is obvious that voltage gain and GBW are boosted as well in the SR enhanced structure. But the added resistors, R L and R L, make the internal pole move towards the low-frequency. This degrades the AC small-signal performance. Fig. 5 depicts the AC small-signal model of the part from the drain of 3L to the gate of L in Fig.. The translation function can be given as Vgs,L ( + gml )( + sc gml ) = I3L gml + As+ Bs ( + gml ) (4) gml + ( RL + RL ) Cs where A = C + C + g R + R C ml L L B = R + R CC L L C = Cgs,L + Cdb,L C = C. gs,l the value of R L +R L is very large, this pole will make the GBW and phase margin (P) deteriorate. To avoid the deterioration, a compensation resistor is used in series with the load capacitor C load to generate a zero /R C C load to cancel the pole out. The resistance of R c can be given as R = R + R C C. (5) C L L load 4. Simulation Results A proposed SRE OTA and a conventional OTA are designed with a power supply voltage of 5 V in a.5 μm COS process to compare their performance. Fig. 6 shows the curves of the unit gain frequency (UGF) and SR versus the resistance of R L (R L =R L =R R =R R ), and Fig. 7 shows the parameters versus the bias current. From Fig. 6, it can be seen that the SR of SRE OTA increases with the increase of the resistance as analyzed before. The UGF also increases with the increase of the resistance at first, but tends to be saturated and even decreases when the resistance continues increasing. This can be explained as follows. When the resistance increases, the GBW increases whereas the non-dominant pole, which is the internal pole, moves towards the low-frequency. At first because the resistance is not so large, the internal pole is still at the high-frequency far beyond GBW, which does not affect the UGF. Therefore, the UGF increases with GBW. But when the resistance continues increasing, the internal pole moves towards GBW and even becomes lower than it. So, the effect of the internal pole becomes more significant and makes the UGF be saturated and even decreases. UGF (Hz).6.4...8 Conventional OTA UGF Proposed SRE OTA UGF Conventional OTA SR Proposed SRE OTA SR. 7.5 5..5 Slew rate (V/µs) Slew rate (V/μs) I 3 L.6. V gs, L R L C C R L g L Fig. 5. Small signal analysis of the internal poles and zeros. It can be seen that this new structure produces two poles and one zero. When the sum of R L and R L are much larger than /g ml, the pole /[(R L +R L )C ] becomes the most significant one. The high-frequency pole and the zero are very close, which cancels each other s effect out. So, the structure actually produces one pole /(R L +R L )C. If -4 4 8 6 4 Resistance of R L =R L =R R =R R (ko) Resistance of R L =R L =R R =R R (kω) Fig. 6 UGF and SR vs. different resistances R L =R L =R R =R R (I bias =5.3 μa, R C =, C load = pf, m=, n=4). From Fig. 7, we can see that the SR of the SRE OTA increases much more quickly with the increase of the bias current than the conventional OTA, because it increases non-linearly with the bias current as analyzed in (), whereas the SR of conventional OTA increases linearly with the bias current. The UGF of SRE OTA also increases more quickly than the conventional one. The reason is that
8 the transconductance g m of the OS transistor increases with the bias current as is well-known, and g ml and g m3l both contribute to the increasing of the GBW of the SRE OTA whereas only g m3l contributes to the increasing of the conventional one according to (3) and (3). 4 8 6 4 4 8 6 4 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 3, NO., ARCH 5 5 5 5 Slew rate (V/μs) Table : Simulation results comparison (I bias =5.3 μa, R L =R L =R R =R R =5 kω, R c =7 kω, C L = pf, m=, and n=4) Parameter indicators Proposed SRE OTA Conventional OTA DC Gain (db) 66.9 47.8 UGF (khz) 73 74 aximum charging/discharging 45.4/ 4.5 5.5/ 5. current (μa) Average SR (V/μs) 4.35.54 Settling time (μs).9 7.4 Static power dissipation (μw) 48 55 FO (Hz pf/ma) 35 39 FO 8.53.3 FO3 4.74.5 Fig. 7. GBW and SR with different bias currents (R L =R L =R R =R R =5 kω, R C =7 kω, C load = pf, m=, and n=4). The AC small-signal characteristic is shown in Fig. 8. It can be seen that the low-frequency gain and UGF of the SRE OTA are both higher than those of the conventional one, agreeing with the small signal analysis in Section 3. The output settling time simulation results are shown in Fig. 9. The output of the SRE OTA settles much faster than the conventional OTA. Voltage gain (db) Phase (deg) 8 6 4 - -4-6 -8-5 - Conventional OTA SRE OTA -5 Conventional OTA SRE OTA - 3 4 5 6 7 Frequency (Hz) Fig. 8. Frequency response of the SRE OTA and conventional OTA (I bias =5.3 μa, R L =R L =R R =R R =5 kω, R C =7 kω, C load = pf, m=, and n=4). 5 4 3 5 5 3 35 4 45 5 Fig. 9. Output settling time simulation of the SRE OTA and conventional OTA (I bias =5.3 μa, R L =R L =R R =R R =5 kω, R C =7 kω, C load = pf, m=, and n=4). 5 4 3 Simulation results are summarized in Table. The figures of merit (FOs) shown in Table are important quality factors reflecting the driving capability and power dissipation of an amplifier. And FO [], FO [], and FO3 [] are defined as follows: FO = GBWC L Ibias (6) FO = ILmax Ibias (7) FO = ILmax Isupply (8) where I Lmax is the maximum output current provided to the load and I supply is the total quiescent current of the supply voltage. In this work, these factors have been greatly improved. FO, FO, and FO3 have been improved 34%, 78%, and 848% respectively. 5. Conclusions In this study, a sensing resistor in series with the diode configured OS transistor of the current mirror is applied to increase the SR. Therefore, the voltage drop across the resistor produces a term containing the square of the input current in the output current of the SRE current mirror. As a result, the op amp has a greater SR which has been improved by 8.5 times. And at the same time, the UGF is improved by.33 times, whereas, the static power dissipation is reduced.7%. Compared with some common methods of SR enhancing, this method does not lead to more power dissipation and even reduces it, which is a great merit. Especially for today, the use of portable equipment, wireless, and other battery powered systems are prevalent, improving the driving capacity with no more power dissipation has great significance. But, the SR of this method is still not high enough, and it is necessary to improve it more for further study. References [] W.. C. Sansen, Analog Design Essentials; Dordrecht: Springer, 6, ch. 6.
WAN et al.: Efficient Slew-Rate Enhanced Operational Transconductance Amplifier 9 [] E. A. Vittoz, The design of high-performance analog circuits on digital COS chips, IEEE Journal of Solid-State Circuits, vol., no. 3, pp. 657 665, 985. [3] G. C. Cardarilli and G. Ferri, COS adaptive biasing circuits for low-power applications, in Proc. of the st Int. Conf. on icroelectronics, 997, pp. 747 75. [4] S. Baswa, A. J. Lopez-artin, R. G. Carvajal, and J. Ramirez-Angulo, Low-voltage power-efficient adaptive biasing for COS amplifiers and buffers, Electronics Letters, vol. 4, no. 4, pp. 7 9, Feb. 4. [5] K. Nagaraj, COS amplifiers incorporating a novel slew rate enhancement technique, in Proc. of the IEEE 99 Custom Integrated Circuit Conf., 99, pp..6..6.5. [6] R. Krithivasan, L. Yuan, L. Najafizadeh, Z. Chendong, C. Suheng, C. Ulaganathan, and B. J. Blalock, A high-slew rate SiGe BiCOS operational amplifier for operation down to deep cryogenic temperatures, in Proc. of IEEE 6 Bipolar/BiCOS Circuits and Technology eeting, 6, pp. 7 75. [7] H. Lee, P. K. T. ok, and K. N. Leung, Design of low-power analog drivers based on slew-rate enhancement circuits for COS low-dropout regulators, IEEE Trans. on Circuits and Systems II, vol. 5, no. 9, pp. 563 567, 5. [8] X. Lei, D.-B. Fu, D.-. Zhu, and C. Su, A novel high-transconductance operational amplifier with fast setting time, in Proc. of the th IEEE Int. Conf. on Solid-State and Integrated Circuit Technology,, pp. 5 5. [9] A.-R. Kim, H.-R. Kim, Y.-S. Park, Y.-K. Choi, and B.-S. Kong, Low-power class-ab COS OTA with high slew-rate, in Proc. of 9 Int. SoC Design Conf., 9, pp. 33 36. [] A. J. López-artín, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, Low-voltage super class AB COS OTA cells with very high slew rate and power efficiency, IEEE Journal of Solid-State Circuits, vol. 4, no. 5, pp. 68 77, ay 5. Xiao-Peng Wan was born in Shanxi, China in 984. He received the B.S. degree from the Northwest University, Xi an in 7 in electronic science and technology. He is currently pursuing the.s. degree with the School of icroelectronics and Solid-State Electronics, University of Electronic Science and Technology of China (UESTC), Chengdu. His research interests include high speed photocoupler designing and power system managing. Fei-Xiang Zhang was born in Anhui, China in 988. He received the B.S. degree from the Anhui University, Hefei in in microelectronics. He is currently pursuing the.s. degree with the School of icroelectronics and Solid-state Electronics, UESTC. His research interests include high speed photocoupler designing and power system managing. Shao-Wei Zhen was born in Hebei, China, in 98. He received the B.S.,.S., and Ph.D. degrees from the UESTC in 5, 8, and 3, respectively. He is now a lecturer with UESTC. His research interests are analog and mixed signal integrate circuit design technology, including power manager integrate circuit, single chip digital power supply circuit, high speed optical receiver chip. Ping Luo was born in Sichuan, China in 968. She received the B.S. and.s. degrees from the Chongqing University, Chongqing in 99 and 993, respectively. She received the Ph.D. degree in electrical circuit and system from UESTC in 4. She is now a professor with UESTC. As a scholar, she visited the Georgia Institute of Technology from to 3. Her research interests include power management circuit for SoC/CPU and LED driver. Ya-Juan He received her B.S. degree from East China Normal University, Shanghai, China in, and the Ph.D. degree from Nanyang Technological University, Singapore in 8. Since 9, she has been working with the School of icroelectronics and Solid-State Electronics, UESTC, where she is now an associate professor. Her current research interests include digital integrated circuits, low-power techniques, and power management IC design.