The Flipped Voltage Follower (FVF)

ELEN 607 (ESS) The Flipped Voltage Follower (FVF) A useful cell for low-voltage, low-power circuit design part of this material was provided by Profs. A.Torralba J. Ramírez-Angulo 2, R.G.Carvajal, A. López-Martín 3,

OUTLINE. Introduction. 2. The Basic FVF. 3. FVF Structures. 4. Applications. 5. Conclusions. 2

The Basic Flipped Voltage Follower (FVF) a) Conventional Voltage Follower v o v i M b) (FVF) Sourcing Sinking A v g out a) Conventional HIGH < gm b) FVF HIGH = gm gm 2 ro [Ramirez-Angulo 92] J.Ramírez-Angulo, R.G.Carvajal, A.Torralba, J.Galán, A.P.VegaLeal, and J.Tombs. The Flipped Voltage Follower: a useful cell for low-voltage low power circuit design, Proc. ISCAS 02, vol. 3, pp. 65-68, 2002. 3

FVF transistors voltage limits to keep them in saturation 4

The Basic FVF Analysis Open Loop Analysis Dc gain Vi V o A OL = V r / V i = - gm 2 R OLY R OLY = r b gm ro ro 2, R OL (+r b /ro )/gm ro 2 Dominant Pole M At Y: w py = / C Y R OLY V r rb Y Compensation Cc Non-Dominant Pole At : w p = / C R OL C parasitics at node (incl. LOAD) C Y parasitics at node Y (incl. Cc if any) Gain-Bandwidth Product GB = gm 2 / C Y 5

2. The Basic FVF Stability Analysis Stability Criterion: w p > 2 GB wp = / C ROL V i V o For a simple current mirror (r b ro ) C C < Y gm 4gm 2 M V r rb Y Cc C parasitics at node (incl. LOAD) C Y parasitics at node Y (incl. Cc if any) For a cascode current mirror (r b gm ro ro 2 ) C C < Y gm ro usually requires compensation 2 2 6

The Basic FVF Closed Loop Output Resistance v i M Y v o R CL r b ro R gm + ro O = + A gm ro OL ( r gm ro ) For a simple current mirror (rb ro) 2 R CL gm gm ro 2 2 b 2 2 b For a cascode current mirror (r b gm ro ro 2 ) R CL gm gm ro 2 A CL and R CL is only a few Ohms (20 00) in all cases 7

The Basic FVF DC considerations v i M 3 M Y v o V DD MIN = V GS MIN + V DS sat 0.8 V for 0.6μm CMOS technology. It is a lowvoltage cell. But, for large V DD, biasing in saturation is difficult for low v i. A high-voltage version includes a voltage shifter in the feedback loop [Chung-Chih 95] High-voltage version [Chung-Chih 95] H.Chung-Chih, H.Changku, M. Ismail, CMOS low-voltage rail-to-rail V-I converter, Proc. 38th MWSCAS, vol.2, pp. 337-340, 995. 8

The Basic FVF i Z Z v Z v Y Const Relation i M v Y i y v Y = 0 v v i Y Z 3-terminal cell (strong inv.) = v = g = 0 Z + ( I, i ) ( I, i, i, v ) ; f ( I, i ) b f For in saturation g b Y ( I, i, i, v ) b Y Z Y Z = V DD V Tp b Y = V 2 k Tp + 2 k p ( Ib iy i ) p ( W L) ( Ib iy ) ( W L) M b For in ohmic M in saturation g ( I, i, i, v ) b Y Z = V DD V Tp v 2 I k b p i Y i ( W L) v M 2 The most interesting case is for i Y = 0 9

FVF Structures for different applications Current sensor (FVF-CS) I out (ua) saturation 2 5 in b ohmic Y out b M 5 saturation 0

FVF Structures Non-Symmetrical Class-AB Differential Pair (FVF-NDP) 0.0 DM3 7.5 5.0 2.5 0 V - V 3 (mv)

3.FVF Structures Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP) v in CM =(v 3 +v 4 )=V 2

Flipped voltage follower applications 2.5 M3 V V a M M2 V 2 V M Ma M2 V 2 i D i D2 i D i D2 DC TRANSFER CURVES (ua) 0.0 7.5 5.0 2.5 0 I(D2P) I(DP) I(D) I(DP) I(D2) I(D2P) -400-200 0 200 400 VIN (mv) Class A Differential Pair Class AB pseudo Differntial pair V DD, min = VTP + 2VDS, sat Comparison "A new Class AB differential Input stage for implementation of low voltage high slew rate op-amps and linear transconductors," J. Ramirez-Angulo, R. Gonzalez-Carvajal, A. Torralba and Carlos Nieva, IEEE International Symposium on Circuits an Systems, May 6-9, Sidney Australia 3

3.FVF Structures Symmetrical Class-AB Differential Pair (FVF-SDP) 0.0 DM6 DM3 7.5 5.0 2.5 0 V - V 3 (mv) 4

3.FVF Structures. Summary Current sensor (FVF-CS) I in M V b I out M 5 Non-Symmetrical Class-AB Differential Pair (FVF-NDP) V 3 M 3 M V M 4 V 4 Symmetrical Class-AB Pseudo Symmetrical Class-AB I DM3 I DM4 Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) 5

3.FVF Structures. Summary sensor (FVF-CS) Current sensor (FVF-CS) I in V b M I out M 5 Non-Symmetrical Class-AB Differential Pair (FVF-NDP) V 3 M 3 M V M 4 V 4 Symmetrical Class-AB Pseudo Symmetrical Class-AB I DM3 I DM4 Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) 6

3.FVF Structures. Summary Current sensor (FVF-CS) I in M V b I out M 5 Non-Symmetrical Class-AB Differential Class-AB Pair (FVF-NDP) Non-Symmetrical Differential Pair (FVF-NDP) V 3 M 3 M V Y M 4 V 4 Symmetrical Class-AB Pseudo Symmetrical Class-AB I DM3 I DM4 Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) 7

3.FVF Structures. Summary Current sensor (FVF-CS) I in M V b I out M 5 Non-Symmetrical Class-AB Differential Pair (FVF-NDP) V 3 M 3 M V M 4 V 4 I DM3 I DM4 Symmetrical Class-AB Pseudo Differential Symmetrical Pair Class-AB (FVF-PDP) Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) 8

4.FVF-CS Applications Current sensor (FVF-CS) Low voltage current mirrors I B i IN I B V M I OUT M 5 [Rijns 93] J.J.F. Rijns, 54 MHz switchedcapacitor video channel equalizer Electr.Lett., vol. 29, no. 25, pp. 28-282, Dec. 993 V in MIN = V DSsat Very low input resistance (a few Ohms) [Ramirez-Angulo 04] J. Ramírez-Angulo, R.G.Carvajal, A.Torralba, Low-supply voltage high-performance CMOS current mirror with low input and output voltage requirements, IEEE TCAS-II, vol.5, no. 3, pp. 24-29, March 2004. 9

4.FVF-CS Applications Current sensor (FVF-CS) Low voltage current mirrors Technology 0,35μm CMOS AMS [Torralba 02] A. Torralba, R.G.Carvajal, J.Ramírez-Angulo, Output stage for low supply voltage CMOS current mirrors Electr.Lett., vol. 38, no. 24, pp. 528-529, Nov. 2002 Minimum supply voltage Load resistor Bandwidth Input impedance Output impedance Input referred noise (@0MHz) Settling time (%, 4 μa step) THD (0 μa pp, @0KHz) V 0 KOhm 20 MHz A few Ohms GOhm.5 pa/ Hz 20ns -66dB 20

4.FVF-CS Applications Current sensor (FVF-CS) Other applications LINEAR V-I CONVERTER I DD TEST CURRENT SENSOR [Karthikeyan 0] S. Karthikeyan, A. Tamminneedi, E.K.F.Lee, Design of low-voltage front-end interfaces for switched-opamp circuits, IEEE TCAS-II, vol.48, no. 7, pp. 722-726, July 200. [Docudray 03] G.O.Ducodray, R.G.Carvajal, J.Ramírez-Angulo, A high-speed dynamic current sensor scheme for I DD test using a FVF Proc. SSMSD, pp. 50-53, 2003 I in (Φ = HIGH) M Φ M 5 I out [Rout 00] S. Rout, E.K.F.Lee, Design of V switched-current cells in standard CMOS process, Proc. ISCAS, vol.2, pp. 42-424, 2000 M B Φ M B2 SI Circuits 2

4.FVF-NDP Applications Non-Symmetrical Class-AB Differential Pair (FVF-NDP) CLASS-AB OUTPUT BUFFER NON-LINEAR CLASS_AB TRANSCONDUCTOR M P A P M 3P M 4a a b M4b V 2 V M 3a M a M 3b M b V V o2 I oa I ob V o V i V o M 9a V b M 8a M 7a [Peluso 00] V.Peluso, P. Vancorenland, A.M.Marques, M.S.J.Steyaert, W.Sansen, A 900mV low-power ΔΣ A/D converter with 77dB dynamic range, IEEE J.Solid-State Circuits, vol. 35, no. 4, pp. 632-636, April 2000. M 7b M 8b V b M 9b M N B M 2N M 3N [Carvajal 02] R.G.Carvajal, A. Torralba, J.Ramírez-Angulo, J.Tombs, F. Muñoz, Compact low-power high slew-rate CMOS buffer for large capacitive loads, Electron. Lett., vol.38, no. 32, pp. 348-349, Oct. 2002. 22

4. FVF-NPD Applications CLASS-AB OUTPUT BUFFER 2 V supply, 0pF capacitor load, 250 KHz input signal M P P A M 3P Output voltage (V) V i M N M 3N B M 2N V o Output transistor current (A) time (s) [Carrillo 04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.Duque- Carrillo, Rail-to-rail, low-power high slew-rate CMOS analog buffer, Electron. Lett., vol.40, no. 4, July 2004. More than 00uA max. output current with 30uA total quiescent current! 23

4.FVF-NPD Applications CLASS-AB OUTPUT STAGE Biasing STAGE M 3p 50/ : α M outp 500/ 25/ 25/ M p p W I Moutp 2-STAGE AMPLIFIER V AB Y + - I o 3,75 ua 3,75 ua I o M n n 8/ 8/ + - Z V AB I M outn V out V V - + M in I = 00 ua dp M in2 500/ 500/ R c C c Output Stage (figure 3a) V out M 3n M outn 6.5/ : α 65/ a) [Torralba 00] A. Torralba, R.G.Carvajal, J. Martínez-Heredia, J.Ramírez-Angulo, Class-AB output stage for low voltage CMOS op-amps with accurate quiescent current control, Electron. Lett., vol.36, no. 2, pp. 753-754, Oct. 2000. 24

4.FVF Applications CLASS-AB OUTPUT STAGE in a 2-STAGE OP-AMP DC Gain db 65 Phase Margin deg ( o ) 75 º Unity Gain frequency MHz 5 Quiescent output current (µa) 76 Minimum current through output transistors (µa) 38 Supply current (µa) 28 Unitary feedback PSRR CMRR db db 38 45 THD (khz) db 65 Input referred noise (00kHz) nv 2 /Hz 2 Slew Rate * (@ 0.3 V peak) V/µs 0 Peak output current * (@ 0.3 V peak) µa 500 Non-inverting Gain= 5 with 2 internal resistors V DD =.5 V, C L =0pF, 0.8 μm CMOS (Vt 0.85 V) Op-amp comp. C C =0pF, R C =500Ω 25

4.FVF-PDP Applications Symmetrical Class-AB Pesudo-Differential Pair (FVF-PDP) 50 CLASS-AB LINEAR MULTIPLIERS (ua) 30 V - a V b = 300 mv M 5 V a' V M a M a V 2 M 6 V b' V M b 3 M b M 4 V I D2 + I - - D4 I D I D3 I out = 0-0 -30 V - a V b = -300 mv -50-300 -00 00 V d2 =V - V 2 300 a) 70 I D2 +I D4 + I D + I D3 I D ID2 I D3 I D + I D3 I D2 + I D4 b) [Ramirez-Angulo 00] J.Ramírez-Angulo, R.G.Carvajal, J.M.Martínez-Heredia,.4V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency, Proc. ISCAS, vol. 5, pp. 533-536, 2000 [Ramirez-Angulo 03] J.Ramírez-Angulo, S.Thoutam, A.López-Martín, R.G.Carvajal, Low voltage CMOS analogue four quadrant multiplier based on Flipped-Voltage-Followers, Electron. Lett., vol.39, no. 25, Dec. 2003. I D4 (ua) 50 30 0-0 -30 I D + I D3 I D + I D3 - - I D2 I D4 I D2 + I D4 I D2 +I D4 - - I D I D3-50 -500-00 300 700 V d2 =V -V 2 26

4.FVF-PDP Applications NON-LINEAR CLASS_AB TRANSCONDUCTORS V DD V CM 30 MCM M op - 30 30 30 30 M op+ MCM 30 VCM M cas 30 Vcasp 30 Vcasp M 4 45 Vcasp 30 Vcasp 30 M cas 45 45 45 V o - V i - M M V V 3 b i+ V o+ VCMc 0 MCMc M cas M on - 0 0 0 0 =u Vcasn Vcasn Vcasn 0 0 0 0 Vcasn 0 0 M cas M on+ MCMc 0 V CMc V SS [Carvajal 02] R.G.Carvajal, J.Galán, J.Ramírez-Angulo, A. Torralba, Low-power, low voltage differential class-ab OTAs for SC circuits, Electron. Lett., vol.38, no. 22, pp. 304-305, Oct. 2002. [Galan 02] J.Galán, A.P. VegaLeal, F. Muñoz, R.G.Carvajal, A.Torralba, J.Tombs, J. Ramírez-Angulo, A.V very low-power SD modulator for 4-b 6 KHz A/D conversion using a novel class AB transconductance amplifier, Proc. ISCAS, vol. 2, pp. 66-69, 2002. 27

4. FVF-PDP Applications. V, SC Integrator. pf capacitor load, 2MHz switching frequency Differential Voltage Output transistor ( V ) Current ( A ) time (s) 0 V/usec SR with only ua total quiescent current! (0.35 μm CMOS) 28

4.FVF-PDP Applications (Va - Vb) fo C C2 Vin+ Vo- Vin- + + + + + + gm gm2 gm3 gm4 _ + _ + C C2 CMFB CMFB2 + + gm5 Vo+ gm-c Filter (Va - Vb) Q 0.7 MHz 29

4.FVF-PDP Applications gm-c Filter Power supply Technology Chip area Frequency tuning range Q range (@0.7MHz) V o,cm variation in the entire tuning range Power consumption range THD (@0.7MHz) SNR IM3 (@0.7MHz) IIP3 PSRR (@ 0.7 MHz) CMRR (@ 0.7 MHz) 2 V 0.8 μm CMOS.44 mm 2 300 khz 32 MHz 4 50 4 mv.8.8 mw 40dB@200 mv pp 45 db 46 db 8 dbm 39 db 42 db 30

4.FVF-PDP Applications gm-c VCO 850 750 Amplitude (mvpp) 650 550 450 350 250 50 250 260 270 280 290 300 30 Vtuning (Gm3) (mv) [Galan 03] J.Galán, R.G.Carvajal, F. Muñoz, A.Torralba, J. Ramírez-Angulo, A low-power lowvoltage OTA-C sinusoidal oscillator with more than two decades of linear tuning range, Proc. ISCAS, vol., pp. 677-680, 2003. [Galán 04] J. Galan, R. G. Carvajal, A. Torralba, F. Muñoz, and J. Ramirez-Angulo, A low-power, lowvoltage OTA-C simusoidal oscillator with a large tuning range. IEEE Trans. On CAS-II. (to appear) 3

4.FVF Applications Symmetrical Class-AB Pseudo-Differential Pair (FVF-PDP) gm-c VCO Power supply 2 V Chip area 0.63 mm 2 Technology 0.8 μm V tuning control 25 mv 500 mv Frequency tuning range MHz 25 MHz Power consumption range.05.58 mw THD (2 / 25 MHz) @200 mv pp.2% / 0.66% Phase Noise at 0kHz offset 67 dbc/hz 32

3.FVF Structures. Summary Current sensor (FVF-CS) I in M V b I out M 5 Non-Symmetrical Class-AB Differential Pair (FVF-NDP) Y V 3 M 3 M V M 4 V 4 Symmetrical Class-AB Differential Pair (FVF-SDP) Symmetrical Class-AB Pseudo Symmetrical Class-AB I DM3 I DM4 Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) 33

4.FVF-SDP Applications Symmetrical Class-AB Differential Pair (FVF-SDP) SUPER CLASS_AB TRANSCONDUCTORS 0.5 μcmos, V DD = 2 V, C L = 80pF 2 MHz square input signal M 5 V 3 M 3 M 6 M V M 4 Y R R o o Quiescent power consumption = 20 uw SR = 78 V/us, % settling time = 0 ns THD (@00 khz) = 0.5 % [Baswa 04] S. Baswa, A. López-Martín, R.G.Carvajal, J.Ramírez-Angulo, Low voltage micro-power super class- AB CMOS OTA, Electron. Lett., vol.40, no. 4, Feb. 2004. 34

4.Other Applications Translinear loops, Geometric Mean, Square-Root Domain Filters, etc. A.J. López-Martín and A. Carlosena, Current-mode multiplier/divider circuits based on the MOS translinear principle, Analog Integrated Circuits and Signal Processing, vol. 28, no. 3, pp. 265-278, 200. A.J. López-Martín and A. Carlosena, Systematic design of companding systems by component substitution, Analog Integrated Circuits and Signal Processing, vol. 28, no., pp. 9-06, 200. A.J. López-Martín and A. Carlosena, A 3.3V CMOS RMS-DC converter based on the MOS Translinear principle, VLSI Design, 2002 35

4. FVF-NPD Applications CLASS-AB OUTPUT BUFFER [Carrillo 04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.Duque- Carrillo, Rail-to-rail, low-power high slew-rate CMOS analog buffer, Electron. Lett., vol.40, no. 4, July 2004. 36

Conclusions. A new cell, called Flipped Voltage Follower (FVF) has been identified. 2. For low-voltage, low power, class AB operation. 3. Different applications have been reviewed (current mirror, voltage buffer, mixer, OTA, transconductance multiplier and op-amp output stage, filters, VCO, SD modulators ). 4. Simulation and experimental results have been presented that show the potential of the socalled FVF structure. 37