PCB Design Guidelines for GPS chipset designs The main sections of this white paper are laid out follows: Section 1 Introduction Section 2 RF Design Issues Section 3 Sirf Receiver layout guidelines Section 4 Common problems to avoid Section 5 Summary 1. INTRODUCTION This document will present some of the critical issues that arise when laying out a new GPS design based on the SiRFstarIIe and SiRFstarIIeLP chipset. Since the RF# characteristics of the receiver are generally the most critical they will be discussed in detail followed by specific SiRF GPS layout guidelines. All new designs based on the SiRFstarIIe and SiRFstarIIeLP chipset should follow these guidelines. SiRF Applications
1.1 General PCB Guidelines Before discussing the critical RF concerns it is worthwhile summarizing some very basic issues when starting a new layout, since proper connector and component placement is the critical first step to generating a new design. SiRF reference designs are typically done on a 4-layer or 6-layer, 2- sided, standard FR4 board all parts should be surface mount (if possible) connector locations should be placed to avoid noisy system interconnect cables from running across the GPS board all RF components should be placed to minimize trace lengths and crossovers all power pins on all IC s should have.01uf decoupling capacitors placed as close to the IC as possible and connect directly to the power and ground planes of the board reserve space for shielding of the RF and the baseband (adequate shielding is necessary to isolate the sensitive RF section and antenna from other noise-generating circuitry) Shields should be soldered to the board, not simply tacked down. Shields require grounding at 100mil spacing. the RF and digital circuitry should be grouped in separate sections on the board all RF grounds should be directly to the ground plane using a dedicated via high pin-count digital components should be placed to minimize routing of multi-trace bus lines crystal oscillator circuits should be isolated from high slew-rate digital signals the designer should always follow the manufacturer s DFM requirements attempt to use the same components that SiRF specifies as a part of the reference design bill of materials keep the RTC section away from the digital and RF circuitry. The RTC circuitry should be routed over the ground plane if possible. Otherwise, avoid any digital signals underneath the RTC. Although very basic, if these guidelines are adhered to during the initial parts placement then a majority of the PCB related problems can be avoided. 2. RF Design Issues RF circuits present new challenges to designers of lower-frequency digital circuits. RF circuits usually deal in nano-volts and the stability of oscillators has to be in the parts-per- billion! Signals will not stay on lines they are supposed to and components do not act as they are expected to. To be able to actually build circuits correctly it is important to have an understanding of the basic properties of circuits from an RF point of view. The following section discusses some of the basic RF design issues that were addressed in developing SiRFstarI and SiRFstarIIe/IIeLP reference designs. 2.1 Tracks, Pads, and Ground Planes Most RF circuits are built over a ground plane to provide better control of parasitic coupling. All tracks, pads, and components are capacitively coupled by their physical proximity to each other. If a ground plane is used there is a large capacitive element to ground, which reduces the coupling between parts. It also provides for a well-controlled return path for currents, which helps keep signals localized. Component pads also generate a capacitance to ground, which effectively adds small capacitors to ground each time a pad is used. This is usually not a big problem for capacitors
greater than 100pF, but it can be if the capacitors are physically large enough. This occurs if the pads are physically large, or the dielectric (the circuit board material) is very thin. RF engineers strive to keep these capacitance s small enough to not have much effect. Unfortunately, there are other parasitic elements formed by just the copper lines on the board. Any trace over a ground plane actually forms transmission lines and should be kept as short as possible. Vias connecting through the board (to ground) will have a small amount of inductance which could be a problem for RF signals. RF signals require very good grounding. If an IC has numerous ground pins they should all be grounded separately (i.e. with their own vias) to minimize inductance. It is also possible for signals to crosstalk through common vias, so it is good practice to ground everything separately. 2.2 RF Components SiRF has designed a reference GPS receiver using our preferred component vendors but new designers may choose to substitute non-critical parts. When doing this, the RF and parasitic performance of each component should be considered. Chip Resistors- Chip resistors have many parasitic elements, but in general the resistance of the resistor masks most of these effects. The most important RF characteristic of chip resistors is the series inductance due to it s physical length. For 0603 components at GPS frequencies this is usually not a serious problem. Chip capacitors- The series inductance mentioned above for resistors is also the most important characteristic in capacitors which generally cannot be ignored. The capacitor and this inductance resonate at some frequency, and engineers have to be careful of this property. A 12 pf 0603 capacitor (with pads and trace inductance) resonates at GPS frequencies, and this can be used to bypass power lines to stop the GPS signal from going where we don t want it. It can also be used to block DC and pass GPS signals with no degradation. On the other hand a 0.1 uf chip capacitor resonates at about 30 MHz and above resonance is quite inductive, so it will not bypass signals above 100 MHz very well and this is why it is not sufficient to use this as a bypass for GPS frequencies. Chip inductors- These are the most difficult components to model. Their main parasitic component is the parallel resonance formed by their interwinding capacitance, and their own inductance. The parallel capacitance can vary widely from manufacturer to manufacturer, so if the inductor is used near it s parallel resonance, it is important to ensure that any inductor from a new manufacturer is similar to the original. Usually the only time this parallel resonance is used is to act as an RF open-circuit, while allowing DC to pass (such as in bias-t s when it is needed to introduce DC into an RF cable). Inductors of the 0603 size, and with a very small number of turns can cause wide variations in circuit performance, especially when different manufacturer s inductors are compared. If the inductor is used in a matching network there may be large variations in RF performance depending on how the inductor is built, and how it is mounted. It is also important to minimize noise coupling into inductors by either shielding them or placing them as far away from the noise sources as possible. 2.3 Gain, Stability, and By-Passing Too much gain at RF frequencies is hard to control and can cause stability problems if not managed correctly. The GPS signal at 1575.42 MHz is hard to keep stuck on traces, even using a ground plane. Each of the components acts as small antennas that can talk to each other and cause amplifiers to oscillate. A general rule to control this is to keep gain at any one
frequency below about 25 db. If this is not possible, it will be necessary to place a shield over the circuitry to reduce unwanted feedback. The SiRFstar typical reference design uses a single 15dB gain stage in front of the GRF2i/GRF2iLP and a single shield over the entire RF section. It is important to keep all RF signals off the power lines. If RF signals get onto the power lines then circuits can oscillate, or misbehave in other ways. Series resonant capacitors can be used to bypass the power, but they are only good at one frequency and therefore broadband bypassing techniques should be used. If it is necessary to stop more than one frequency it is possible to use 2 different capacitors (e.g..01uf and 100pF), but there is a drawback. Above the resonance of the large capacitor it will look inductive, while the smaller capacitor is still capacitive. This can form a parallel resonator that actually performs worse for frequencies between the two individual resonant frequencies. If it is possible to put a resistor, ferrite bead, or inductor between the two capacitors then it is possible to fashion a better bypass than that made with the two capacitors alone. Ferrite beads have very complicated equivalent circuits, so it is important to understand them before using them. There are many different types that act quite differently. The typical one used in the 0603 size is usually like a parallel resonant inductor, and becomes a resistive element at GPS frequencies. This can make for a fairly good element for a bypass network, when paired with suitable capacitors. There are currently a number of chip components available that look like a capacitor, but also have a grounded center pin. These are feedthrough capacitors, and are very good for bypassing signals. 2.4 Crystal Oscillator Requirements The crystal oscillator needs to have very little noise on it in a GPS system and also not vary too much over temperature. It is therefore critical that the crystal be placed very near the oscillator IC could and be isolated from noise-generating circuits. It should also be placed away from IC s that dissipate a lot of power which can cause large temperature gradients at turn-on. In a GPS receiver, the system can track oscillators that vary smoothly over 10 to 15 parts per million (ppm), but if the oscillator signal is jittering back and forth (even as little as 5 parts per billion), the receiver will have trouble. Therefore it is necessary to keep the oscillator as clean as possible. Short traces, and careful layout, keeping any signal, especially digital ones, away from the circuitry, are important. The oscillator will also be prone to proximity effects, such as waving your hand near it, therefore it should always be shielded! To avoid your GPS crystal oscillator from affecting your sensitivity, ensure that your filter on the output of the GPS crystal is sufficient enough to reduce the drive level of Xtalin to <350mVpp. It has been discovered that at very high drive levels, the doubler in the RFIC will produce side bands due to jitter. This in turn causes the sensitivity of the receiver to degrade by as much as several db. For further information, please speak with your SiRF application engineer. 2.1 RF Power Supply Another source of noise is from the power supply. Ensure the supply is well bypassed for both low and high frequencies. The oscillator generally needs a linear-regulated supply voltage to function well enough in a GPS system. The combination of a good linear regulator and good bypassing ensures that the oscillator supply is as clean as it can be. For bypassing, you only require one tantalum capacitor as close to the regulator output as possible. Additional
capacitors will have little or no effect. Also, when routing the regulator output traces, the thicker the power trace from the regulator to the RFIC, the better the performance. 3. SiRF Receiver Layout Guidelines 3.1 PCB Fabrication Requirements On our SiRFstarI and S2AM reference designs we used a standard 4-layer,.062in FR4 PCB with no special controlled-impedance requirements. This is possible if all RF routing is kept as short as possible (to avoid transmission line effects). When routing signals at 1575.42MHz, if the track length must be longer than about 0.1in, then its width should be chosen to implement a 50ohm microstrip transmission line. All other non-critical routing was with 5mil lines with 5mil spacing using 12mil diameter vias. Because RF performance can be sensitive to pad capacitance, the inner-layer dielectric spacing is critical and should adhere to the 8mil spec (between layer 1-2). If board size is critical then a new design should consider using a 6-layer board and possibly 0402 chip components (although both of these increase cost). With our S2AR SiRFstar IIe reference designs, we used a 6-layer,.062 FRF PCB. You can refer to our S2AR reference design for further info on routing and hole sizes. 3.2 Placement of Components As can be seen from our reference designs, the RF and digital sections are naturally separated. In our 4 layer designs, the RF section is completely shielded and no digital components (or routing) were placed beneath it. In our 6 layer designs, the RF section is on one side, while the digital is kept to the backside. We avoid routing noisy digital lines under our GPS and RTC clocks, as well as our RF loop filter. With all of our reference designs, we attempt to keep the PECL interfaces between the baseband and RF chip, short and straight. If you are required to route the PECL lines around other components/traces, ensure that you change direction at 45 degree angles. Implementing long run PECL s with multiple direction changes can lead to low drive levels to the baseband as well as increase the chances of picking up noise. As an option, you may also want to consider placing a small resistor pack in line with each PECL interface for better noise immunity. The actual resistor value utilized is somewhat dependent on the spacing between the RF and baseband and is typically 1k ohm for very short distances and about 100 ohms for longer distances. 3.1.1. Layer Stacking With respect to 4 layer designs, we recommend the following: Note: For in-depth information, refer to the S2AM reference design, as well as application note #21. Layer 1 is the component (i.e. top) side where SiRF places the baseband and flash memory (from the digital section) alongside the RF chip. The entire RF section is shielded with a small hole in the top to attach an RF cable. Layer 2 is the ground plane. It should be placed directly below the RFcomponents for best isolation. SiRF uses a common ground plane for the digital and RF sections. We highly recommend that you do not split your ground planes. One common ground for the RF and digital should suffice.
Layer 3 is a power plane with typically two different Vcc voltages. The RF section runs on 2.85v while the digital circuits run mostly off of 3.3v. For upgrading to the SiRFstarIIeLP, you may also require the addition of a 1.8V plane, but this can be avoided very easily. We do not recommend any other signal routing in this plane. Layer 4 is typically the solder side where additional memory and non-critical components are usually placed. No digital circuits should be placed under the RF section. With respect to 6 layer designs, we recommend the following: Layer 1 is the component (i.e. top) side where SiRF placed the entire RF circuitry, from the SiRF RF chip to the RF regulator. The entire RF section is shielded with a small hole in the top to attach an RF cable. Layer 2 is the ground plane. It should be placed directly below the RF components for best isolation. SiRF uses a common ground plane for the digital and RF sections. We highly recommend that you do not split your ground planes. One common ground for the RF and digital should suffice. Layer 3 and 4 are inner signal routing. This area should be used for routing all digital signals which interface to memory, reset supervisor s, etc. Do not route any RF signals in the inner layers. Layer 5 is a power plane with typically two different Vcc voltages. The RF section runs on 2.85v while the digital circuits run mostly off of 3.3v. For upgrading to the SiRFstarIIeLP, you may also require the addition of a 1.8V plane, but this can be avoided very easily. We do not recommend any other signal routing in this plane. Layer 6 is utilized as the baseband, memory and supporting circuitry layer. If feasible, try to avoid routing any digital components directly under the GPS crystal. 3.3 Routing Issues With proper component placement routing can usually be straight-forward. A few items to adhere to during routing are; keep all digital lines away from the RF section avoid routing between components (to prevent undesirable coupling) RF routing longer than about.1in should be 50ohm transmission lines RF and bypass grounding should be direct to the ground plane through its own via Isolate the digital noise from the RF section by using separate ground and power planes. This can be quite useful, but care must be taken in how the power and ground signals cross the gap between the two sections. For simplicity and reliability, we recommend using one uniform ground plane. Usually all signal and power lines are bypassed as well as possible, and the ground is connected with a trace at a spot that has been shown to be optimum (usually near the edge of the board). In the case of the SiRF product, if you choose to split ground planes, you should connect them near the differential outputs of the RF chip. It can be quite tricky to accomplish this ground connection to satisfy all the operating conditions. Do not use an inductor or bead to connect the grounds, because when a cable is hooked up to the board a
great deal of 60 Hz and other radiated signals appears across this inductor, and causes the RF section to be totally jammed by noise. If the board is going to be mounted in an enclosure, noise can radiate around the split and effectively cancel out the isolation. If the whole unit is going to be shielded this also cancels out the split because the shield has to connect to both the RF and digital grounds to be effective. SiRF has found that the most practical method of building a GPS receiver is to use the same ground for both the RF and digital sections, but to build a good shield around the RF section. Manufacturability should also be considered when placing and routing components. This includes trace width, trace spacing, component spacing, tooling holes, edge-clearances, testpoints, etc.. 4. Common Problems to Avoid The most common reason for a GPS receiver not functioning (when first integrated), is because the receiver is jammed by digital noise. The receiver is so sensitive that harmonics of the digital signals are much larger than the signals being processed. It cannot be stressed too much that seemingly inconsequential design violations can cause digital noise to get into the front end and degrade system performance. Some mistakes that have caused problems in the past are: not designing the PCB with the required layer1-2 spacing allowing the RF power plane to extend beyond the RF shield passing digital signals near the RF front-end via holes passing unbypassed power into the RF section placing the IF filter inductors too close to noisy circuits routing RF ground pins using long traces using alternate components which do not have the same RF characteristics inadequate shielding long PECL interface between the RF and BB not bypassing any digital outputs to the outside world with 12pF capacitors