Modeling Snapback and Rise-Time Effects in TLP Testing for ESD MOS Devices Using BSIM3 and VBIC Models, Duane Connerney, Ronald Carroll, Timwah Luk Fairchild Semiconductor, South Portland, ME 04106 1
Outline Research Motivation Snapback in MOS Devices and Previous Models Macro Model using BSIM3 and VBIC Advantages of New Macro Model Simulation of Snapback and Rise Time Effect Results and Discussions Conclusion 2
Research Motivation ESD Is a Major IC Reliability Concern: Responsible for 30%~50% Customer Returns Accurate SPICE Models for Integrated ESD Simulation Can Reduce ESD Design Iteration MOSFETs in Snapback Operation Mode Are Widely Used as ESD Protection in CMOS Technology Rise Time of ESD Pulse Has Significant Impact on Performance of MOS ESD Protection A Practical SPICE Macro Model for Snapback of ESD MOS Devices is Needed and Good Understanding on the Rise Time Effect is Helpful. 3
Snapback in MOS Devices Four Regions in I-V Curve (1) Linear Region (2) Saturation Region (3) Avalanche Region (4) Snapback Region Snapback due to Parasitic NPN Holes Created by Impact Ionization in D/B Depletion Layer Are Injected Into Substrate Parasitic NPN turns on when voltage drop cross Rsub ( Vbe of BJT) (Isub Rsub) reaches ~0.7V V G Id Region (1) Region (2) Gate Bias Region (4) Region (3) V S STI P+ STI N+ Electrons Emitted when S/B Junction Is Forward Biased Ids Ib Ic V D N+ Impact Ionization Depletion layer STI Vt1 Pwell Rsub Isub Vd P+ Substrate 4
Previous MOS Snapback Models(1) Numerical SPICE Models Have Been Publicly Reported Four Essential Components: G Main MOS Parasitic BJT Avalanche Current Source Substrate Resistor S Rs Ib Ids Ic Rd D Id=Ids+Ic+Igen Igen The BJT Is Modeled With EM or GP Models Isub B Rsub 5
Previous MOS Snapback Models(2) The Explicit Current Source Is Given by ( M ) ( Ids Ic) I gen = 1 + where M is multiplication fact, given by Miller formula 1 M = 1 K1 exp K 2 Vd Vdsat or M = exp [ k1( Vd Vdsat d1) ] + exp [ k 2( Vd Vdsat d 2) ] The Models Are Implemented either in Proprietary SPICE, or Using Behavior Language Verilog-A or VHDL-A The Verilog-A Models Can Have Low Simulation Speed and May Cause Serious Convergence Problems Proprietary SPICE Has Limited Accessibility to Designers and Needs Extra Support 6
Macro Model Using BSIM3 and VBIC Our New Macro Model Structure Includes Three Main Components: NMOS modeled by BSIM3 Parasitical NPN modeled by VBIC Substrate resistance S The Impact Ionization Current or Avalanche Current Source Is Built in BSIM3 and VBIC Models Isub = α1+ I ave = I c α0 Leff AVC1 Equivalently, We Have Igen = Isub + Iave β 0 Vds Vdeff ( Vds Vdeff ) e Idsa ( ) ( ) ( MC AVC 2 PC Vbci PC Vbci e 1) Rs Cbe Cgs E Cgb B Bi G Isub Rsub C Iave Cgd Rd Cbc D Id=Ids+Ic similar to M = exp[ k1( Vd Vdsat d1) ] + exp[ k 2( Vd Vdsat d 2) ] 7
Advantages of New Snapback Macro Model Simple Structure and Strong Capability Standard components only and no external current source Partially decoupled substrate current for BJT and intrinsic MOS Transient simulation capability from sophisticated capacitance modeling in BSIM3 and VBIC High simulation speed since no Verilog-A or VHDL-A involved Less convergence issues due to no Verilog-A and fine-tuned algorithms of BSIM3 and VBIC VBIC offers simulation capability for self-heating effect A Practical Approach: Easy to Implement and Use No need using behavior languages (Verilog-A, ) No need for special SPICE implementation by individual Users The availability is high since both BSIM3 and VBIC are widely included in various simulators. CAD environment is compatible to non ESD models 8
Simulation of Snapback and Rise Time Effect Snapback was simulated with transient simulation using schematic below Voltage pulse sequences with varied rise time were used as the input The stabilized Vd and Id were measured as the simulation results 50Ω 12 0.24 10 Id 0.20 Voltage source Vd/Vin (V) 8 6 4 Vd Vin 0.16 0.12 0.08 Id (A) 2 0.04 0 0 0 20 40 60 80 100 120 140 160 t (ns) Schematic of TLP Simulation for ggnmos Input voltage Vin, drain voltage Vd and drain current Id vs. time t in a single pulse 9
Results and Discussions(1): Snapback Curves Snapback curves demonstrate that trigger voltage Vt1 decreases as the rise time of the input pulse is reduced The dependence of Vt1 on the rise time was observed in ggnmos and gcnmos configurations 0.35 0.4 0.3 0.35 Id (A) 0.25 0.2 0.15 0.1 Trise=8ns Trise=20ns Id (A) 0.3 0.25 0.2 0.15 0.1 Trise=1.5ns Trise=8.0ns 0.05 0.05 0 2 3 4 5 6 7 8 9 10 Vd (V) Snapback curves of a ggnmos structure (lines: simulation, symbols: measurement) 0 3 3.5 4 4.5 5 5.5 6 6.5 Vd (V) Snapback curves of a NMOS with a 10k resistor between gate and ground (lines: simulation, symbols: measurement) 10
Results and Discussions(2): Trigger Voltage Vt1 Vt1 of gcnmos was observed much more sensitive to the rise time than Vt1 of ggnmos Sensitivity simulation indicates that the overlap capacitance has no impact at all on Vt1 for ggnmos but cause most variation for gcnmos Vt1 for ggnmos is affected by junction capacitance and transit time 12 10 CJ / CJ0 0.8 0.9 1.0 1.1 1.2 Vt1(V) 10 8 6 4 0 4 8 12 16 20 trise (ns) gcnmos ggnmos Vt1 vs. rise time for ggnmos and gcnmos observed in measurement Vt1 (V) 9.6 9.2 8.8 Vt1 vs. CJE 8.4 Vt1 vs. CJC Vt1 vs. Transit Time 8.0 100 200 300 400 500 Transit Time (ps) Vt1 vs. CJC and t F in a ggnmos (Trise=8ns) 11
Results and Discussions(3): Vbe Spike under ESD Pulse Vgs>0 due to gate coupling is the well-known cause of Vt1 drop in gcnmos Vbe of NPN shows a spike at rising edge of input voltage pulse Vbe may drop back to a stabilized value or continue increasing. The dividing point is corresponding to the trigger voltage Vbe (V) 1 0.8 0.6 0.4 0.2 0-0.2-0.4-0.6 Vpulse=8V Vpulse=10V Vpulse=9.15V Vpulse=9.14V -0.8 0 20 40 60 80 100 120 Time (ns) Vbe vs. Time in a single pulse for a ggnmos Vbe (V) 1 0.9 0.8 0.7 0.6 Vbe_max 0.5 0.4 0.3 Vbe_pulse 0.2 Vbe_DC 0.1 0 3 4 5 6 7 8 9 10 11 12 Vpulse (V) Vbe vs. ESD stress voltage in transient (Vbe_pulse and Vbe_max) and quasistatic (Vbe_DC) events for ggnmos 12
Results and Discussions (4) Displacement current through the Drain/Bulk junction causes a Vbe spike in the parasitic NPN in ggnmos. Avalanche current in Drain/Bulk junction is enhanced by the Vbe spike, which eventually results in a lower trigger Vt1. Higher CJC and shorter rise time (higher dv/dt) cause bigger Vt1 reduction. It is important to properly model the Drain/Bulk junction capacitance as well the Source/Bulk junction capacitance and the base transmit time to achieve accurate simulation for the trigger voltage of ggnmos snapback. For NMOS with a resistor between gate and drain, Drain/Gate overlap capacitance is the dominant parameter Vt1 dependence on rise time 13
Conclusion A unique macro model structure for snapback simulation of ESD MOS devices has been developed The model takes the advantage of built-in formulas and finetuned algorithms in sophisticated BSIM3v3 and VBIC models It offers advantages of high simulation speed, wider accessibility, and less convergence issues The model has been used for investigation of Vt1 dependence on the rise time of transmission line pulse (TLP) The simulation demonstrated that the t f and junction capacitance of parasitic BJT have impact on Vt1 even for ggnmos The cause of Vt1 drop in ggnmos is the displacement current due to dv/dt in TLP pulses 14