Sub-1 V Supply Nano-Watt MOSFET-Only Threshold Voltage Extractor Circuit Oscar E. Mattia Microelectronics Graduate Program Federal University of Rio Grande do Sul Porto Alegre, Brazil oemneto@inf.ufrgs.br Hamilton Klimach Electrical Engineering Department Federal University of Rio Grande do Sul Porto Alegre, Brazil hklimach@ufrgs.br Sergio Bampi Informatics Institute Federal University of Rio Grande do Sul Porto Alegre, Brazil bampi@inf.ufrgs.br ABSTRACT This work presents a self-biased MOSFET threshold voltage V T 0 extractor circuit. Its working principle is based on a current-voltage relationship derived from a continuous physical model. The model is valid for any operating condition, from weak to strong inversion, and under triode or saturation regimes. The circuit is MOSFET-only (can be implemented in any standard digital process), and it operates with a power supply of less than 1 V, consuming tenths of nw. Post-layout simulation results show that the extracted V T 0 has an error inferior to 1.3%, when compared to the theoretical value, for a -40 to 125 C temperature range. We present variability results from Monte Carlo simulations that support the extracting behavior of the circuit with good accuracy. The occupied silicon area is 0.0076 mm 2 in a 0.13µm CMOS process. Categories and Subject Descriptors B.7 [INTEGRATED CIRCUITS]: Miscellaneous Keywords CMOS Analog Design; Threshold Voltage Extractor; Nano- Power 1. INTRODUCTION The threshold voltage (V T 0) of an MOS transistor is one of the most fundamental parameters used in all areas of circuit design and test. The measured V T 0 value can be used for process characterization, monitoring and compensation, temperature measurements, bias circuits and voltage references. Many methods have been proposed to measure the threshold voltage value [1], varying widely with the used MOSFET model, the physical meaning of threshold and with the choice of operation region. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. SBCCI 14, September 01 05, 2014, Aracaju, Brazil. Copyright is held by the owner/author(s). Publication rights licensed to ACM. ACM 978-1-4503-3156-2/14/09...$15.00. http://dx.doi.org/10.1145/2660540.2660991. A threshold voltage extractor is a circuit that ideally delivers the estimated V T 0 value as a voltage directly from its operational conditions, without parametric setups, curve fitting and/or any subsequent calculations. Through the years, many circuits have been proposed for this purpose [2], [3], [4], [5] and [6], but all of them are based on the strong inversion quadratic model for the drain current. In a few topologies another inversion regime is used for the MOSFET V T 0 extraction. For example, [7] uses a continuous transistor model [8] and proposes a circuit based on the channel conductance-to-current ratio (g ch /i d ) methodology, requiring a good estimation of the specific current of the fabrication process to correctly bias the transistor. Still it is hard to make any fair comparison, since circuits from [2-6] are based on different definitions for V T 0. We do not state that these solutions are not good but our topology is the only one that works in the nw range, being more interesting for low power applications. In this paper we present a self-biased topology based on the ACM MOSFET model [8] that allows the direct extraction of both the threshold voltage and the specific current for a wide temperature range. It is a small area, low power and resistorless circuit, that can be implemented in standard digital CMOS processes. The text is organized as follows: section 2 presents the threshold voltage extractor concept, the self-cascode (SC) proportional to absolute temperature (PTAT) voltage generator and the complete V T 0 extractor circuit. A design methodology is proposed in section 3, followed by simulation results of the circuit implemented in a 0.13µm CMOS process, including Monte Carlo variability analysis, in section 4. 2. CIRCUIT DESCRIPTION The transistors used in the proposed circuit operate both under weak and moderate inversion levels, meaning that circuit analysis requires a model capable of describing all operation regions continuously using one equation, as done in the ACM MOSFET model [8], which is introduced next. 2.1 ACM MOSFET Model In the ACM model, the drain current I D of a long-channel MOSFET is expressed as I D = I F I R = SI SQ(i f i r) (1)
where I F and I R are the forward and reverse currents, S = W/L is the aspect ratio, W being the width and L the length of the transistor. i f and i r are the forward and reverse inversion coefficients, related to the source and drain inversion charge densities, while I SQ is the sheet normalization transistor current M5 Vdd K1 : 1 M6 I SQ = 1 2 nµc oxφ 2 t (2) where n is the subthreshold slope factor, µ is the channel effective mobility (both slightly dependent on the gate voltage V G), C ox is the gate capacitance per unit area, and φ t is the thermal voltage. The relationship between inversion level i f and i r and terminal voltages is given by M1 M2 V P V S(D) = F (i f(r) ) = 1 + i f(r) 2+ln( 1 + i f(r) 1) φ t (3) where V S and V D are the source and drain voltages (all terminal voltages are referenced to the transistor bulk), and V P is the pinch-off voltage, approximated by + VS2 V P VG VT 0 n being V G the gate voltage, and V T 0 the threshold voltage for zero bulk bias. Over time, very many operational and device physics quantities dependent (inversion charge, for instance) definitions for V T 0 were used. In the ACM MOS- FET model, the threshold voltage has a universal physical meaning, defined as the condition where the drift and diffusion components of the drain current have equal magnitude. The first term (the square root one) in the right side of (3) is related to the drift component of the drain current, being predominant under strong inversion. The last term (the logarithmic one) is related to the diffusion component, being predominant under weak inversion operation. In the forward saturation condition, I F I R, and consequently, I D I F = SI SQi f. In this paper the V T 0 value is then rigorously defined based on (3). 2.2 V T 0 Extractor The V T 0 extractor circuit concept is shown in Fig. 1. The same topology was presented in [9], but was used as a selfbiased current source. In this work we propose a novel use to this topology, that of V T 0 extractor. Since it is functionally different, the design demands a completely new analytical approach, presented next. From (3) and (4), one can see that a saturated nmos- FET with grounded source and operating under a constant inversion level equal to 3 (i f = 3) will have a gate voltage V G equal to the threshold voltage V T 0, because under these conditions, the right side of (3) becomes zero. Suppose that in the circuit shown in Fig. 1, M1 operates under such condition, being in the moderate inversion region. M2 is kept saturated too and sharing the same gate voltage, but with a source voltage different from zero. Using (3) and (4) for M2, knowing that V G1 = V G2 = V T 0 and I D1 = K 1I D2, leads to (5). ( ) 3S1 V S2 = φ tf (i f2 ) = φ tf K 1S 2 From (5) one can conclude that if the resulting M1 current I D1, that was chosen to keep M1 operating with i f1 = 3, is also used to control the drain current of M2 (through the (4) (5) Figure 1: Threshold voltage extractor concept. M5-M6 current mirror), M2 also operates under a constant inversion level, making F (i f2 ) constant. Thus, if a voltage proportional to φ t is attached to the source terminal of M2, with the right proportionality factor F (i f2 ) adjusted (using the current mirror gain K1 and aspect ratio S 2/S 1), the equality of (5) can be satisfied. A non-zero equilibrium point is then reached in this circuit, V G1 = V G2 = V T 0 for any temperature and independently of process parameters, defined only by geometric ratios. Since M2 operates with higher source voltage than M1, its inversion level has to be lower, or F (i f2 ) < 0. This means that in our circuit M2 operates in the weak inversion region, and its source voltage can be generated by the self-cascode topology, presented in the next section. 2.3 Self Cascode PTAT Generator A well-known circuit used to generate a PTAT voltage independent of process parameters is the self-cascode MOS- FET, introduced by Vittoz in 1977 [10] and shown in Fig. 2. M4 M3 I4 K2I4 Figure 2: Self-Cascode PTAT generator schematic.
Transistor M3 has higher drain current than M4 but smaller aspect ratio, leading to different inversion levels on each transistor. While M4 must be in saturation, M3 can be in saturation or in triode. The difference between their gatesource voltages appear across the drain-source terminals of M3. As done in [11], the use of (3) and (4) demonstrates that this voltage is proportional to the thermal voltage, as given by (6). V SC = V DS3 = φ t[f (i f3 ) F (i f4 )] (6) Usually both transistors operate in weak inversion, and the PTAT voltage is determined only by the ratio of current densities between the devices. But, as demonstrated in [11], equation (6) shows that as long as the inversion levels of both MOSFETs are kept constant over temperature, they generate an ideal PTAT voltage under any inversion level. This can be achieved by biasing both transistors with currents proportional to I SQ. 2.4 Complete Circuit The complete circuit of the proposed threshold voltage extractor can be seen in Fig. 3. Transistors M1-M2 form the V T 0 extractor, and M3-M4 the self-cascode PTAT generator. M5-M7 are used for biasing. One can note that K 1 and K 2 in Fig. 3 are then the design parameters we will discuss and optimize in the next section. M1 Vdd K1 : 1 K2 : 1 M5 M6 M7 M2 M4 M3 Figure 3: Proposed threshold voltage extractor schematic. The circuit is designed to make i f1 = 3, meaning that I D1 = 3S 1I SQ, as determined in section 2 (B). The proportional to the specific current of M1 is then mirrored to M2 and to the SC pair M3-M4, meaning that I D2 = I D1/K 1, I D4 = I D1/(K 1K 2) and I D3 = (I D1/K 1)(1 + 1/K 2). Equation (6) then becomes (7). ( ) ( )] V SC = φ t [F 3 S1 K 2 + 1 F 3 S1 1 (7) S 3 K 1K 2 S 4 K 1K 2 From (7) it is clear that the PTAT voltage generated by the SC cell depends only on geometrical factors, and not on fabrication process parameters. Since V G1 = V T 0, the gate voltage of M1 has a temperature dependence equal to that of the threshold voltage, that can be approximated by the linear equation (8). V G1(T ) = V T 0(nom) + K T (T T nom) (8) Where T is the absolute temperature, V T 0(nom) is the threshold voltage at the nominal temperature T nom and K T is the thermal coefficient of the threshold voltage. Previous analysis has imposed that all transistors must be saturated, expect for M3 that can be in triode. Usually the saturation condition is practically defined, for weak inversion, as the drain-to-source bias for which V DS 4φ t [8]. The minimum supply voltage for the operation of the circuit is thus approximated by (9). V DD,min(T ) V T 0(nom) + K T (T T nom) + 4φ t (9) The PTAT voltage that is generated by the SC cell also imposes a condition for the saturation of M2, or a minimum value for the threshold voltage to be extracted, approximated by (10). V T 0,min(T ) V SC(T ) + 4φ t (10) Clearly, the operation of the circuit establishes a relation between the maximum temperature and the minimum V T 0 that can be extracted. Note that the left term of the inequality in (10) decreases with temperature, while the sum of the terms on the right increases. 3. DESIGN METHODOLOGY First of all, we restrict the design space exploration to use only integer values for the current mirror gains and for the width ratios of the transistors, as a way to improve the layout using common-centroid technique and dummy devices. It provides greater layout regularity, resulting in better device matching and consequent lowering of circuit spread from local variability. Our circuit design also prioritizes low power and low voltage operation. As a starting point, the forward inversion level of M1 is set as 3, and the inversion level of M2 (i f2 ) is fixed by the current gain K 1 and by the ratio S 2/S 1. It should be noted that a low i f2 reduces power consumption, but a higher V S2 value is needed to balance the circuit operation. This trade-off is illustrated in Figs. 4 and 5, using eq. (5) at 27 C. Also, a small aspect ratio for M1 and M2 contributes to lower the power consumption, but the designer must remember that smaller transistor area has a severe drawback, namely the increase of the local mismatch from local variability [12]. It is important to realize that V S2 has to be generated by a single SC cell in the circuit of Fig. 3. The maximum PTAT voltage is limited to around 100 mv at room temperature, since this voltage depends on the difference between the inversion levels of M3 and M4, and these levels must be kept in weak inversion to save power. We choose a value of K 1 = 6 and S 2/S 1 = 1 to demonstrate a practical implementation, leading to a V S2 58 mv. We can then proceed to sizing the self-cascode generator. Fig. 6 presents V SC from (7) as a function of current gain K 2 and aspect ratio S 4/S 3 at 27 C. Since we have chosen V S2 58 mv for the equilibrium condition, these curves can be used to determine S 4/S 3 = 4 and K 2 = 1. Note that V SC
The results presented here are for SPICE post-layout simulations of a 0.13µm process, and approximately match the analytical design of section 3. The implementation takes into consideration good matching layout practices such as common-centroid structures and dummies. The occupied silicon area is 0.0076 mm 2, as shown in Fig. 7. Figure 7: Layout of the proposed V T 0 0.13µm CMOS. extractor in Figure 4: Sizing of the V T 0 extractor. i f2 vs K 1. The MOSFETs used in this implementation are standard I/O transistors, that have higher threshold voltage in this process. Using the (g m/i d ) methodology described in [7], an average value of V T 0 resulted, being V T 0(nom) = 476 mv for T nom = 27 C and K T = 500 µv/ C. After a fine adjust through simulation, the design factors used were K 1 = 6 and K 2 = 1, while the aspect ratios are S 1,2 = 1/30, S 3 = 2/50, S 4 = 6.6/50 and S 5 = 10/15. The voltage extractor circuit employs positive feedback, and the stability of the equilibrium point V G1 = V T 0 must be guaranteed. Opening the loop on the gate of M1, and by varying V G1 while observing the resulting V G2, the operating point can be found and the loop gain can be calculated. This is shown in Fig. 8. Figure 5: Sizing of the V T 0 extractor. V S2 vs K 1. is in fact the V S2 DC source shown in Fig. 1, and also is V DS3 in Fig. 2, as defined in (7). Figure 8: DC operating point and loop gain. Figure 6: Sizing of the SC cell, V SC vs S 4/S 3. 4. SIMULATION RESULTS There is only one crossing point of both lines, which happens for V G1 = V T 0. The loop gain ( V G2/ V G1) at the crossing point is less than one, therefore providing a stable operating point. Fig. 9 presents V T 0 over temperature estimated by the (g m/i d ) method [7] (labeled ACM), and simulated in the V T 0 extractor circuit of Fig. 3 (labeled VTEX). The error defined by (11) is presented in Fig. 10. The circuit tracks the ideal threshold voltage with an error inferior to 1.3% under the -40 to 125 C temperature range. ( ) VT EX V ACM ɛ(%) = 100 (11) V ACM Fig. 11 presents the currents in each branch of the circuit. The whole circuit consumes 23 na at 27 o C, reaching
implementation starts operating at around 0.6 V, as shown in Fig. 13. The line sensitivity of V G1 is poor though, being 46 mv/v from 0.6 V to 1.2 V, while the current consumption sensitivity is 14 na/v. Both line sensitivity and PSRR could be increased by adding cascode current sources, for example, at the penalty of increasing the minimum supply voltage. Figure 9: Proposed circuit (VTEX) and g m/i d (ACM) V T 0 vs. temperature, V DD = 1.2 V. Figure 12: PSRR vs. frequency for V DD = 1.2 V and 27 C. Figure 10: Error vs. temperature, V DD = 1.2 V a maximum of 33 na at 125 o C. Startup behavior of the circuit was simulated, having a settling time of less than 3 ms, which is acceptable for our proof of concept. We expect that leakage currents are enough to start the circuit, but in real applications a startup circuit could be necessary for faster settling. Figure 11: Currents over temperature. PSRR simulated at 100 Hz and V DD = 1.2 V, is -30 db for V G1 and -50 db for V SC - Fig. 12. As predicted by (9), this Figure 13: Line Sensitivity of V G1 and I T OT AL vs. V DD, 27 C. To analyze the fabrication variability of the error, Monte Carlo (MC) simulations were done separately for local mismatch effects and average process variations, with 100 runs each. For average process MC all the transistors have their parameters changed equally in each run - Fig. 14 (top histograms). For local mismatch MC, the parameters of each transistor are varied individually in each run - Fig. 14 (middle histograms). Both effects are taken into account in a full variability analysis, shown in Fig. 14 (bottom histograms). The results presented are for V DD = 1.2 V under three different temperatures, -40, 27 and 125 C. As shown in the design methodology, the circuit s equilibrium point depends only on geometrical factors. It is thus less sensitive to average process variations, where V G1 tracks the threshold voltage value with a maximum error (mean and standard deviation) of ɛ(±3σ) = 0.61 ± 1.26%, comprising 99.7% of the samples. Local mismatch analysis, however, affect the current mirror and aspect ratio gains that define this equilibrium, resulting in a higher spread of ɛ(±3σ) = 0.67 ± 5.7%. A combined analysis yields a maximum error of ɛ(±3σ) = 0.73±5.61% for the whole operating temperature range. The mean and the sigma of each temperature and variability condition is shown in Fig. 14.
Figure 14: Histogram for 100 MC runs. Error at -40, 27 and 125 C, as defined in (11). Average process variation, local mismatch and combined variability. 5. CONCLUSION A resistorless ultra-low-power threshold voltage extractor circuit was presented, described by a continuous physical MOSFET model. It is a self-biased topology composed by transistors operating in weak and moderate inversion, that works with V DD,min V T 0 + 4φ t. Typical post-layout simulations of an I/O MOSFET in a 0.13µm CMOS process demonstrate an error for the extracted threshold voltage value inferior to 1.3%, at an extended temperature range of -40 to 125 C. The circuit consumes 28 nw at room temperature under V DD = 1.2 V. Monte Carlo simulations show that the maximum error spread is ɛ(±3σ) = 0.73 ± 5.61% for a combined variability analysis. Acknowledgment The authors are grateful to CNPq, the IC-BRAZIL program and MOSIS Educational Program for financial support. Also to V. Cunha for simulations. 6. REFERENCES [1] A. Ortiz-Conde, F. G. Sanchez, J. Liou, A. Cerdeira, M. Estrada, and Y. Yue, A review of recent {MOSFET} threshold voltage extraction methods, Microelectronics Reliability, vol. 42, no. 4âĂŞ5, pp. 583 596, 2002. [2] Z. Wang, Automatic vt extractors based on an n times;n2 mos transistor array and their application, Solid-State Circuits, IEEE Journal of, vol. 27, no. 9, pp. 1277 1285, Sep 1992. [3] M. Johnson, An input-free vt extractor circuit using a two-transistor differential amplifier, Solid-State Circuits, IEEE Journal of, vol. 28, no. 6, pp. 704 705, Jun 1993. [4] U. Cilingiroglu and S. K. Hoon, An optimally self-biased threshold-voltage extractor [mosfet circuit parametric testing], Instrumentation and Measurement, IEEE Transactions on, vol. 52, no. 5, pp. 1528 1532, Oct 2003. [5] G. Fikos and S. Siskos, Low-voltage low-power accurate cmos vt extractor, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, no. 6, pp. 626 628, Jun 2001. [6] S. Vlassis and C. Psychalinos, Low-voltage cmos vt extractor, Electronics Letters, vol. 43, no. 17, pp. 921 923, August 2007. [7] O. F. Siebel, M. C. Schneider, and C. Galup-Montoro, {MOSFET} threshold voltage: Definition, extraction, and some applications, Microelectronics Journal, vol. 43, no. 5, pp. 329 336, 2012. [8] A. Cunha, M. Schneider, and C. Galup-Montoro, An mos transistor model for analog circuit design, Solid-State Circuits, IEEE Journal of, vol. 33, no. 10, pp. 1510 1519, 1998. [9] E. Camacho-Galeano, C. Galup-Montoro, and M. Schneider, A 2-nw 1.1-v self-biased current reference in cmos technology, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52, no. 2, pp. 61 65, Feb 2005. [10] E. Vittoz and J. Fellrath, Cmos analog integrated circuits based on weak inversion operations, Solid-State Circuits, IEEE Journal of, vol. 12, no. 3, pp. 224 231, 1977. [11] G.-M. C. Rossi, C. and M. C. Schneider, Ptat voltage generator based on an mos voltage divider, in NSTI Nanotech, vol. 3, 2007, pp. 625 628. [12] M. Pelgrom, A. C. J. Duinmaijer, and A. Welbers, Matching properties of mos transistors, Solid-State Circuits, IEEE Journal of, vol. 24, no. 5, pp. 1433 1439, Oct 1989.