Electronic Costing & Technology Experts

Similar documents
Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

Electronic Costing & Technology Experts

21 rue La Noue Bras de Fer Nantes - France Phone : +33 (0) w7-foldite :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

Apple iphone X IR Dot Projector

21 rue La Nouë Bras de Fer Nantes - France Phone : +33 (0) website :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

ams Multi-Spectral Sensor True Color ambient light sensor from Apple iphone X

Autoliv Night Vision System Safety Application Automotive IR Camera

Apple iphone 6s Plus Teardown & Physical Analyses of Key Components

Fan-Out Wafer Level Packaging Patent Landscape Analysis

Fan-Out Solutions: Today, Tomorrow the Future Ron Huemoeller

Laminate Based Fan-Out Embedded Die Technologies: The Other Option

Consumer Physics SCiO Molecular Sensor

Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct , IWLPC

Fraunhofer IZM - ASSID

Market and technology trends in advanced packaging

3D PLUS technology and offer

Fan-Out Wafer Level Packaging Patent Landscape Analysis

HTC Vive VR (Model 0PJT100) Virtual Reality Headset

Electrical Test Vehicle for High Density Fan-Out WLP for Mobile Application. Institute of Microelectronics 22 April 2014

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract)

FO-WLP, Embedded Die, and Alternatives: Market Trends and Drivers

Silicon Interposers enable high performance capacitors

2.5D Platform (Examples of products produced to date are shown here to demonstrate Amkor's production capabilities)

First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration

The Future of Packaging ~ Advanced System Integration

The 3D Silicon Leader

Data Sheet _ R&D. Rev Date: 8/17

Application of 3D PLUS WDoD technology for the manufacturing of electronic modules 25/02/2017 for implantable medical products

Enabling concepts: Packaging Technologies

New wafer level stacking technologies and their applications

TechSearch International, Inc. Corporate Overview E. Jan Vardaman, President

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative

Through Glass Via (TGV) Technology for RF Applications

Advanced Wafer Level Packaging of RF-MEMS with RDL Inductor

Hermetic Packaging Solutions using Borosilicate Glass Thin Films. Lithoglas Hermetic Packaging Solutions using Borosilicate Glass Thin Films

3D ICs: Recent Advances in the Industry

Innovations Push Package-on-Package Into New Markets. Flynn Carson. STATS ChipPAC Inc Kato Rd Fremont, CA 94538

Thin Film Bar MOS Capacitors

Yole Developpement. Developpement-v2585/ Publisher Sample

IC Decoupling and EMI Suppression using X2Y Technology

TCP-3182H. 8.2 pf Passive Tunable Integrated Circuits (PTIC)

= 25 C) Parameter 2.5 GHz 4.0 GHz 6.0 GHz Units Gain db W Power P OUT. = 43 dbm

Image Sensor Advanced Package Solution. Prepared by : JL Huang & KingPak RD division

2D to 3d architectures: back to the future

SiP packaging technology of intelligent sensor module. Tony li

SHELLCASE-TYPE WAFER-LEVEL PACKAGING SOLUTIONS: RF CHARACTERIZATION AND MODELING

WLP Probing Technology Opportunity and Challenge. Clark Liu

Hardware Design Considerations for MKW41Z/31Z/21Z BLE and IEEE Device

Capacitive Fingerprint Sensors Technology and Patent Infringement Risk Analysis

High Power Density Surface Mount TRANSZORB Transient Voltage Suppressors

An innovative plating system

Advanced High-Density Interconnection Technology

Practical Limitations of State of the Art Passive Printed Circuit Board Power Delivery Networks for High Performance Compute Systems

n o. 03 / O ct Newsletter

Texas Instruments X66AK2E05XABD25 Multi-Core DSP + ARM KeyStone II SoC

3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology

MA4AGSW2. AlGaAs SP2T PIN Diode Switch. MA4AGSW2 Layout. Features. Description. Absolute Maximum Ratings TA = +25 C (Unless otherwise specified)

AMD ATI TSMC 28 nm Gate Last HKMG CMOS Process

= 25 C) Parameter 2.7 GHz 2.9 GHz 3.1 GHz 3.3 GHz 3.5 GHz Units Small Signal Gain db

Features. Gain: 14.5 db. Electrical Specifications [1] [2] = +25 C, Rbias = 825 Ohms for Vdd = 5V, Rbias = 5.76k Ohms for Vdd = 3V

Intel Xeon E3-1230V2 CPU Ivy Bridge Tri-Gate 22 nm Process

Smart Power Delivery using CMOS IC Technology: Promises and Needs

Signal Integrity Modeling and Simulation for IC/Package Co-Design

PRELIMINARY DATASHEET

Enhancement Mode phemt

= 25 C) Parameter 5.5 GHz 6.5 GHz 7.5 GHz 8.5 GHz Units Small Signal Gain db P OUT

TARGET SPECIFICATIONS CGY2191UH/C GHz Low Noise Amplifier FEATURES DESCRIPTION APPLICATIONS

TSV MEOL (Mid-End-Of-Line) and its Assembly/Packaging Technology for 3D/2.5D Solutions

Digital Design and System Implementation. Overview of Physical Implementations

Encapsulated Wafer Level Chip Scale Package (ewlcsp ) for Cost Effective and Robust Solutions in FlexLine

Research in Support of the Die / Package Interface

SMD Photovoltaic Solar Cell Protection Rectifier

4-Line BUS-Port ESD Protection

Packaging Roadmap: The impact of miniaturization. Bob Pfahl, inemi Celestica-iNEMI Technology Forum May 15, 2007

Innovative Embedded Technologies to Enable Thinner IoT/Wearable/Mobile Devices

Innovations in EDA Webcast Series

Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M 512 Megabit DDR2 SDRAM Structural Analysis

RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET

Surface Mount Glass Passivated Rectifier

Flexible Hybrid Electronics Fabricated with High-Performance COTS ICs using RTI CircuitFilm TM Technology

Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes

RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET

HMC540SLP3E v db LSB SILICON MMIC 4-BIT DIGITAL POSITIVE CONTROL ATTENUATOR, GHz

High Current Density Surface Mount Glass Passivated Rectifiers

!"#$"%&' ()#*+,-+.&/0(

HMC849ALP4CE SWITCHES - SPDT - SMT. HIGH ISOLATION SPDT NON-REFLECTIVE SWITCH, DC - 6 GHz. Typical Applications. Features. Functional Diagram

EMT 251 Introduction to IC Design

AN4269. Diagnostic and protection features in extreme switch family. Document information

Adaptive Patterning. ISS 2019 January 8th

Proceedings. BiTS Shanghai October 21, Archive - Session BiTS Workshop Image: Zhu Difeng/Dollar Photo Club

Transcription:

Electronic Costing & Technology Experts 21 rue la Nouë Bras de Fer 44200 Nantes France Phone : +33 (0) 240 180 916 email : info@systemplus.fr www.systemplus.fr September 2016 Version 1 Written by Stéphane ELISABETH DISCLAIMER : System Plus Consulting provides cost studies based on its knowledge of the manufacturing and selling prices of electronic components and systems. The given values are realistic estimates which do not bind System Plus Consulting nor the manufacturers quoted in the report. System Plus Consulting is in no case responsible for the consequences related to the use which is made of the contents of this report. The quoted trademarks are property of their owners. 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 1

Glossary 1. Overview / Introduction 4 Executive Summary Reverse Costing Methodology 2. Company Profile 7 Apple Inc. Apple Series Application processor Fan-Out Packaging TSMC Port-Folio TSMC info packaging 3. Physical Analysis 15 Physical Analysis Methodology iphone 7 Plus Teardown 17 A10 Die removal A10 Package-on-Package Analysis 23 A10 Package View, Dimensions A10 Package XRay View A10 Package Opening A10 Package Marking A10 Package Cross-Section A10 Package Cross-Section Adhesive & Passivation A10 package cross-section - TIVs A10 package cross-section Solder Balls A10 package cross-section RDL Land-Side Decoupling Capacitor Analysis 48 Package View, Dimensions & Marking LSC Package integration Cross-Section Package-on-Package Comparison 52 Packages Comparison Overview Packages LSC comparison Package comparison cross-section A10 Die Analysis 57 A10 Die View, Dimensions & Marking A10 Die Cross-Section A10 Die Process Characteristics Comparison with previous generation 65 A9 vs. A10 PoP A9 vs. A10 Process 4. Manufacturing Process Flow 70 Chip Fabrication Unit Packaging Fabrication Unit info Reconstitution Flow 5. Cost Analysis 81 Synthesis of the cost analysis Main steps of economic analysis Yields Hypotheses Die Cost Analysis 86 Wafer Cost Die Cost info Packaging Cost Analysis 90 Packaging Wafer Cost Packaging Cost per process Steps Component Cost 6. Estimated Price Analysis 99 Manufacturer Financial Ratios Estimated Selling Price Contact 102 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 2

This full reverse costing study has been conducted to provide insight on technology data, manufacturing cost and selling price of iphone 7 Plus Application Processors, the Apple A10. Located on the main board, the application processor (AP) (bottom package) and the DRAM Chip (top package) are in Package-on-Package (PoP) configuration. Depending on the version (iphone 7 or iphone 7 Plus), the DRAM memory has different space management. The Apple A10 is a Wafer-Level Package (WLP) using TSMC s packaging technology with copper pillar as Through info Via (TIV) to replace the well-known Through Molded Via (TMV) technology. With this new technology, Apple marked a huge breaking point with the old traditional PoP found in the previous generations of his APs. In this report, we will show the differences and the innovations of this package: Copper Pillars, Redistribution layer, patent identification, silicon high density capacitor integration, The detailed comparison with the Exynos 8 and the Snapdragon 820 will give the pro and the cons of the info technology compared to PoP packaging used in the market. Thanks to this info process, Apple is able to propose a very thin package on package, with a high number of I/O pads and better thermal management. The result is a very cost-effective component that can compete with any well-known PoP. In the report, the cost comparison is also including in order to highlight the difference. This report also includes a technical comparison with previous Apple AP, the A9. 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 3

Apple iphone 7 Plus Main Board (Top view) Wifi FEM and antenna modules 1 st part of RF components A10 processor & baseband processor Power managements IC & NFC 2 nd part of RF components & RF transceiver Apple iphone 7 Plus Main Board (Top view) Apple iphone 7 Plus Main Board (Bottom view) 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 4

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 5

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 6

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 7

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 8

Package RDL Cross-Section SEM View Package RDL Cross-Section SEM View 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 9

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 10

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 11

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 12

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 13

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 14

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 15

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 16

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 17

2016 by SYSTEM PLUS CONSULTING, all rights reserved. 18

Reverse costing analysis represents the best cost/price evaluation given the publically available data, and estimates completed by industry experts. Given the hypothesis presented in this analysis, the major sources of correction would lead to a +/- 10% correction on the manufacturing cost (if all parameters are cumulated). These results are open for discussion. We can reevaluate this circuit with your information. Please contact us: 2016 by SYSTEM PLUS CONSULTING, all rights reserved. 19