A 80MHZ-TO-410MHZ 16-PHASES DLL BASED ON IMPROVED DEAD-ZONE OPEN-LOOP PHASE DETECTOR AND REDUCED-GAIN CHARGE PUMP

Journal of Circuits, Systems, and Computers World Scientific Publishing Company A 80MHZ-TO-410MHZ 16-PHASES DLL BASED ON IMPROVED DEAD-ZONE OPEN-LOOP PHASE DETECTOR AND REDUCED-GAIN CHARGE PUMP SARANG KAZEMINIA * Urumi Graduate Institute Urmia, West Azerbaijan 57159, Iran s.kazeminia@urmia.ac.ir SOBHAN SOFI MOWLOODI Urumi Graduate Institute Urmia, West Azerbaijan 57159, Iran m.s.sofimowloodi@urumi.ac.ir KHAYROLLAH HADIDI Urumi Graduate Institute Urmia, West Azerbaijan 57159, Iran kh.hadidi@urmia.ac.ir Received (Day Month Year) Revised (Day Month Year) Accepted (Day Month Year) In this paper, a low jitter 16-phases DLL is proposed based on a simple and sensitive phase detector. Dead-Zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16- phases in frequency range of 80MHZ to 410MHz, consuming total power of 3.5mW and 5.6mW, respectively. The dead-zone of PD is also reduced from 80ps to 14ps when the pulse generator section is eliminated. Also, RMS jitter of about 45ps and 1.76ps are obtained at 80MHz and 410MHz, respectively, when the supply voltage is subject to around 40mvolts peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05mm 2 active area in a 0.18µm CMOS technology. Keywords: Delay Locked Loop, Charge Pump, Low Jitter DLL, Dead-Zone, Phase Detector. 1. Introduction Generating multiple phases of low jitter reference clock is widely demanded in clock generation of high-speed digital integrated circuits. Furthermore, in resource sharing applications when a single hardware is scheduled for several operations multiphase clock generation is required. For example, three phases of analog comparators within flash ADCs, reset, pre-amplification and latch, can be scheduled in a single stage hardware * Corresponding Author. Another contact Email: sarang.kazeminia@yahoo.com. 1

2 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollah Hadidi applying proper timing strategy. As discussed in other literatures, DLLs are especially used in local oscillators for PCS applications, [1], high-speed clock/data recovery (CDR), [2], frequency multipliers, [3], Time to digital converter (TDC), [4], DRAMs, [5], SRAMs, [6], and high-resolution analog to digital converters. Phase locked loops, PLLs, and delay locked loops, DLLs, are two main candidates of low jitter multiphase clock generation. Although the ability of rejecting input clock jitter, PLLs are implemented in larger area and greater power consumption due to including VCO for generating fresh and low-jitter oscillating signals. In small area and low power applications, DLLs are preferred somewhere the clock generation strategy should be locally repeated inside the chip. Phase/Phase-Frequency detector, PD/PFD, dominantly determines the loop sensitivity in DLLs/PLLs. Hence, RMS jitter in both DLL/PLL loops is directly related to the sensitivity of PD/PFD. Conventional PDs commonly include positive feedback logic devices, [8] and [11], which withstands against developing the phase difference of updated inputs and enlarges the dead-zone, consequently. The proposed open loop PD in [7], is constructed from two sections: main core and pulse generator. Three digital signals, containing two differential reference clocks and 180 degrees delayed one, are applied as inputs. Although small dead-zone is expected from the simple structure of main core, but the pulse generator section dominantly determines sensitivity, due to delay of cascaded logic gates. Another problem initiates from the fact that very small gain requirements cannot be easily provided in regular charge pumps due to problems of generating and mirroring current in submicron ranges. In this paper, the restricting feature of conventional open loop PD, [7], is eliminated to enhance the loop sensitivity. Eliminating pulse generator develops continuous DC values on charge pump inputs and considerably increases loop gain due to opening the charge/discharge path for long time duration. Hence, a compatible charge pump is proposed to produce small charge pack from difference of intentionally mismatched tail current sources. Thus, the sensitivity of PD is enhanced with no longer side effect on loop gain and convergence behavior. The modified structure of PD and the proposed compatible charge pump is discussed in section 2. The modified structure of differential delay elements are presented in section 3. Section 4 is allocated to simulation results and finally section 5 concludes the paper. 2. Building Blocks of the Proposed DLL Fig.1 shows the building blocks of the proposed DLL. Eight differential delay elements are cascaded in loop structure to provide 22.5 phase difference on each output. Input reference clock signals are labeled by Clk_Ref and Clkb_Ref. PD detects the phase difference of reference and generated clock signals. Then, charge pump, CP, produces an analog output relates to the detected phase difference. Analog output of CP adjusts the delay of cascaded delay elements to provide near 360 phase throughout whole cells, when the phase difference at the PD s inputs is reduced to around zero.

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 3 As shown, two phases of 180 and 360 degrees, labeled to Clk_180 and Clk_360 on delay cell s outputs, are fedback to PD to determine the priority or recency in compare to the input reference clock signals. Transferring two digital signals back to PD s input can be considered as the main drawback of this method due to probable complexities in layout pattern. Figure 1. Building Blocks of the Proposed DLL A. The Modified Phase Detector Detail description of the modified PD is shown in Fig.2. Two master-slave clocked inverters are employed, partially similar to the main core of PD in [7]. As shown, one of the input reference clock signals, Clk Ref, is sampled by two generated phasess of 180 and 360 degrees to decide voltage level of PD s output, called UP node. Also, the delayed clock signal of Clk_180 is concurrently sampled by differential input reference clocks in master-slave configuration to propagate high or low level voltage on other output of PD, called DN node. When the falling edge of reference clock arrives befor/afterr the falling edge of clk_180, high/low level of input voltage is buffered to UP/DN node. Two complementary values are expected at UP and DN outputs due to both reference and generated signals participate in sampling. The sensitivity of PD is only restricted by the required time of sampling within clocked inverter. In PD of [7], evaluation of priority is performed by similar sampling method; meanwhile pulse generator section provides narrow pulses to restrict the time duration of charging in charge pump and reducee the loop gain, consequently. Besides the role of gain reduction, dead-zone is increased considering use of logic NAND gates in [7]. Namely, very small differences of falling reference and rising generated clocks can be detected by main core, whereas the NAND gates in pulse generator section might dismiss differences smaller

4 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollah Hadidi than gate delay of a typical NAND gate. Timing representation of PD s inputs and outputs is shown in Fig. 3 for both cases of positive and negativee phase differences. Figure 2. Detail Description of the Proposed PD Figure 3. Behaviour of PD in Response to Phase Differences To estimatee the dead-zone, PD is separately simulated. A test digital signal with the same frequency, but intentionally differedd in phase, is moved toward or away from the reference clock. The points of changing output levels from high to low and vice-versa, are considered. Fig.3 shows a simple comparison between dead-zone of [7] and this work which confirms about 83% improvement when the pulse generator is eliminated.

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 5 Figure 4. Dead-Zone Reduction in Proposed PD in Compare to [7] A novel strategy of gain reduction is proposed inside the charge pump which removes the concern of gain control within the PD section. B. The Proposed Gain-Reducedd Charge Pump Due to eliminating pulse generator in PD, continuous DC values of UP and DN opens the charge/discharge path for large time durations. Hence, large charge packages are pumped during each clock cycle. Two straightforward methods are knownn to decrease the slope of charging in regular charge pumps: firstly, increasing the capacitance in LP filter and secondly, reducing the charging/discharging current. The first option is limited by area constraints. Also, the second one is involved in the problems of generating and mirroring sub-micron currents. Considering that the variations of small currents is comparable to the absolute values of current source, hence current mirrors are not supposed for low current applications. A new idea is that two currents in middle ranges are produced which are intentionally mismatched to provide non-equal currents with small differences. Then, the difference of generated currents can be easily used as the very small current in CP. Fig.5 shows the basic idea of generating small current, separated in two cases. In the case of (a), when UP=1 and DN=0, smalll current of δi is steered to output capacitors from Push to Pull output. Hence, Push/Pull output would be charged/discharged. In the case of (b) current path is reversed to discharge/charge Push/Pull node.

6 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollah Hadidi Figure 5. Basic Idea of Generating Small Currents in CP (a) Charging and (b) Discharging Mode Circuit implementation of Fig.5 is illustrated in Fig.6 in which two NMOS devices with different sizes of (w) and (w+δw) are considered as the down tail current sources. Also, PMOS current sources are proportionally mismatched. Small mismatch is intentionally provided by changing the size of devices, (δw). Hence, the current of (I) and (I+δI) is expected to be producedd in both PMOS and NMOS sides. The value of (δw) should be selected more than the maximum reported value of unwanted process variations or fabrication undesirability. The other non-idealities, such as current variations due to output voltage swings similarly affect tail current sources in identical directions. Differential pairs of Fig..6 steer all currents of tail sources into one side when experience voltage difference of more than 2(ΔV), in whichh ΔV is the overdrive voltage of input devices of differential pair at balanced mode. Hence, the full digital range of UP and DN voltages are not required. Figure 6. CMOS Implementation of Fig.5

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 7 Circuit of Fig. 7(a) is used to reduce the swing of UP and DN signals from digital levels to smaller values, UP_Red and DN Red. Reducing the peak-to-peak voltage swing to around 400mv causes to prevent deep cut-off situation of M1-M8. Also, the voltage level of nodes X1, X2, Y1 and Y2 is preserved in desiredd range to keep the tail current sources on, throughh PD s output variations. Turning tail current sources on for all possible values of PD s output, means passing a constant current from supply to ground which is more important in low-noise applications due to eliminating probable current spikes from supply voltage. Figure 7. CMOS Implementation of (a) Swing Reducing Block (b) Lock Detector C. Lock Detector Charging and discharging mode of charge pump are discussed in the cases of (a) and (b) in Fig.5. When the loop is locked in correct situation, both the outputs rise to one, UP=1 and DN=1, observing the PD of Fig.2. Hence, the charge pump should stop the charging/discharging operation. A simple XOR gate of Fig. 7(b) is utilized to intercept the path of current sources from the output capacitors. The output of Lock Detect, can bring M9 and M10 into cut off region to hold the CP s outputs unchanged, when both Up and DN are rised up to high level. A problem, is the leakage current of capacitors, after locking. Hence, the DLLL loop might periodically exit from lock situation, after thousand cycles of input clock and return to lock state again. 3. The Modified Structure of Differential Delay Elements Differential structure of delay cells is shown in Fig..8. Delay is controlled via two devices, using both the Push and Pull outputs of the charge pump. In the case of Up=1 and DN=0, charge pump will charge the Push and speedss down the delay elements from two directions: firstly, through M Push by decreasing the bias current, and secondly through M Pull by increasing the sink current. M Pull steers some portion of tail current to partially reduce the effective currents of up and down. Concurrent control of the effective current

8 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollah Hadidi of delay elements from two paths might enlarge the operating range of DLLL within the definite range of control voltages. Figure 8. Detail Description of Delay Elements with CM Setting Strategy To avoid the mismatch problems of up and down tail currents, DC setting strategy of [7] is also utilized. Otherwise, the duty cycle of the generated differential clocks undesirably deviate from 50 percent in opposite directions of changing output s CM level. The DCcorrected by level of each stage is sensed at the next one via two resistors, R, and then is changing the up and down tail currents via M CMP and M CMN, as depicted in Fig.8. This means a simple averaging on generated clock signals without reducing effect on speed. 4. Simulation Results DLL loop has been simulated using the BSIM3 model of level49 HSPICE parameters in a 0.18µm CMOS process. In all simulations, inverter gates are considered at output nodes of generated phases to provide the possibility of using outputs with other hardware. Hence, capacitive loads are introduced on all cells which partially reducee the maximumm operating frequency. Layout pattern of the proposed DLL is shown in Fig. 9, includes 8-differential delay elements, charge pump, capacitances of LP filter and phase detector. As estimated, the proposed DLL can be implemented in less than 0.05mm 2 active area in a 0.18µm CMOS technology.

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 9 Figure 9. Layout Pattern of the Proposed DLL The simplified circuit of Fig. 10(a) and 10(b) are simulated for whole range of CP s input voltage representing the conventional bias method and the proposed one. As shown in Fig.11, more silent charging/discharging current is achieved on CP s capacitance, in response to whole range ramp input voltages, in compare to the case of using a single tail current source. The whole-range inputs and the passing current from CP s capacitance are illustrated for both casess in Fig. 11(a) and 11(b), respectively. Results confirm that small currents can be more properly produced and mirrored subtracting two larger bias currents with smaller dependencee to input voltage levels of CP. Figure 10. The Simplified Model of ( a) Conventional (b) Proposed Strategy of Charge Pump

10 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollahh Hadidi Figure 11. (a) The Full-Range Inputs of in1 and in2 (b) The I CP, for Circuits of Fig. 9(a) and 9(b). The intentional mismatch of δw in Fig. 6, is considered such that reliably provide the proper difference of δi in tail current sources. Monte-Carlo analysis with the Gaussian distribution on threshold voltage of tail current source devices is performed and the results are shown in Fig. 12. As clarified in Fig. 12(b), the maximum value of I differs from the minimum value of I+δI more than 4.5µA which provides a good margin, even if 13mVolts variations on threshold voltages of tail devices is occurred. The central values of I and I+δI are selected around 30µA and 45µA, respectively. Figure 12. (a) Threshold Voltage Variations in Gaussian Distribution in Monte-Carlo Analysis (b) The Generated Tail Currents of I and I+δI.

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 11 Locking behavior of closed loop structure is shown in Fig.13 at 100MHz input frequency. The control voltage of Push node is remained unchanged throughh locked area as shown in Fig. 13(a). Inputs of PD, colored in red and black in Fig. 13(b), are finally conformed in phase when the loop is locked. Figure 13. (a) Control Voltage of Push Node (b) PD s Inputs. Through Unlocked and Locked Area All phases of DLL s outputs are shown in Fig.14 at 400MHz frequency of reference clock, through locked area. Considering total phases of 360 degrees, each output is differed from neighbor one equal to 22.5 degrees. Simulation results confirm that about 100 clock cycles are required for complete lock of DLL loop when the control voltage rises up from zero to its final value. The mentioned problem of leakage currents, discussed in section 2.C, is clarified in Fig.15 at 200MHz operating frequency. When the loop is locked, the lock detector circuit of Fig. 7(b) intercepts the path of charging/discharging output capacitance of CP. After locking, both the UP and DN outputs are reached to high level voltage, however, narrow falling pulses are generated by lock-detector circuit to compensate the discharge of CP s output capacitance and brings the output phases of DLL back into lock situation.

12 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollahh Hadidi Figure 14. All Generated Phases at 400MHz Operating Frequency Figure 15. Problem of Leakage Current in Presence of Lock-Detector Circuit (a) Control Voltage at Push Node (b) Falling Pulses of UP Node

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 13 The settling behavior and output pulses of PD are illustrated in Fig. 16 for the mentioned conditions of Monte-Carlo analysiss in which the threshold voltage of all devices randomly experience around 13mVolts peak-to-peak variations. Multiple control voltages and the corresponding PD s pulses are separated by colors in Fig. 16(a), 16(b) and 16(c). Figure 16. (a) Control Voltage at Push Node (b) Falling Pulses of UP Node (c) Rising Pulses of DN Node in Monte-Carlo Analysis and Peak-to-Peak Variations of 10mVolts on Threshold Voltages Variations in different corners are also considered in transient behavior. The control voltage is illustrated in Fig. 17 and Fig. 18 at 400MHz and 80MHz operating frequencies for all process corners. To provide practical conditions of jitter evaluation, noisy supply with the peak-to-peak value of 40mv is applied on 1.8volts supply voltage. Noise pattern is constructed from a set of sinusoidal voltage sources in series combination with the frequency range of 10MHz to 2GHz. Larger amplitudes are allocated to the multiples of input reference clock as might practically occurs via the substrate couplings. Eye diagram and jitter histogram for one of the output phases is illustrated in Fig.19 at 80MHz input frequency, yields the peak-to-peakk and RMS jitter of around 190ps and 45ps, respectively. Jitter analysis is also presented in Fig.20 at 400MHz input frequency, confirms the peak-to-peak and RMS jitter of around 12ps and 1.76ps, respectively.

14 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollahh Hadidi Figure 17. Control Voltage After Settling for TT, FF, SS, SF and FS Corners @ 400MHz Operating Frequency Figure 18. Control Voltage After Settling for TT, FF, SS, SF and FS Corners @80MHz Operating Frequency

Wide-Rangee 16-Phases DLLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 15 Figure 19. Transitions in Eye Diagram and Jitter Histogram at 80MHz Referencee Frequency for 40mv Peak-to- Peak Noise on Supply Voltage Figure 20. Eye Diagram and Jitter Histogram at 400MHz Reference Frequency for 40mv Peak-to-Peak Noise on Supply Voltage

16 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollahh Hadidi RMS jitter of the proposed DLL is plotted in Fig.21 for frequencies of 80, 200, 300 and 400MHz in two cases: Firstly, when the 1.8v supply voltage is subject to 40mv peak-to- noise is peak noise, which is distinguished by solid lines, and secondly, when the supply eliminated, is separated by dashed lines. Figure 21. RMS Jitter for Flat and Noisy Supply Voltage 5. Conclusions A low-jitter 16-phases DLL is proposed in the frequency range of 80-410MHz in a 0.18µm CMOS technology. A sensitive phase detector with small dead-zone is presented. Also, a novel structure of charge pump is proposed to generatee small bias currents and smaller loop gain. Table I summarizess the features of DLL at some operating frequencies. Table I. DLL Specifications at Wide-Range Operating Frequencies. Operating Frequency(MHZ) 80 100 200 300 400 RMS Jitter(ps) for 40mv P-t-P Supply Noise 45 30 15 6.5 1.76 Power Cons. (mw) 3.5 3.8 4.2 4.8 5.6 Control Voltage (volts) of node 1.46 Push 1.42 1.32 1.11 0.81

Wide-Range 16-Phases DLL Based on Improved Dead-Zone Phase Detector and Reduced Gain Charge Pump 17 Power consumption would be increased when the operating frequency is reached near to maximum operating frequency. The RMS jitter is also reduced at higher operating frequencies. Also, the control voltage of Push node would be reduced to provide the larger bias currents at higher operating frequencies. Table II compares the proposed DLL with other similar works. Noisy conditions are also provided to simulate the practical conditions. Table II. Comparison Table. [15] 2011 [10] 2012 [7] 2013 [16] 2013 This Work Process (µm) 0.18 0.18 0.35 0.18 0.18 Operating frequency Range(MHz) 186-650 68-128 20-100 75-1000 80-410 Supply (volts) 1.2 1.8 3.3 1.8 1.8 No. Phases 5 N.A. 16 10 16 PtP Jitter (ps) @freq(mhz) N.A. 13 @128 11 @100 2.52 @1000 12 @400 RMS Jitter (ps) @freq(mhz) 1.5 @650 3 @128 2 @100 0.468 @1000 1.76 @400 Power(mW) @ freq(mhz) 1.1 @650 5.94 @128 16.5 @100 3.4 @1000 5.6 @400 Area (mm 2 ) N.A. 0.066 0.08-0.05

18 Sarang Kazeminia, Sobhan Sofi Mowloodi and Khayrollah Hadidi References 1. G. Chien and P. R. Gray, A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications, IEEE Journal of Solid-State Circuits, Vol.35, No. 12, Dec 2000, pp:1996-1999 2. H. H. Chang, R. J. Yang and S. I. Liu, Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection, IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 51, No. 12, Dec. 2004, pp. 2356 2364. 3. R-J. Yang and S-I. Liu, A 40-550 MHz harmonic- free all-digital delay-locked loop using a variable SAR algoritam, IEEE Journal of Solid-State Circuits, Feb 2007, Vol.42, No. 2, pp:361-373. 4. B. K. Swann, A 100-ps Time-Resolution CMOS Time-to-Digital Converter for Positron Emission Tomography Imaging Applications, IEEE JOURNAL of solid-state circuits. vol. 39. No. 11. Nov 2004. 5. W-J. Yun, H-W. Lee, D. Shin and S.Kim, A 3.57 Gb/s/ pin low jitter all-digital DLL with dual DCC circuit for GDDR3 DRAM in 54-nm CMOS technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(9), 1718 1722.J. 6. N-S. Kim, U-R. Cho and H-G. Byun, Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application, Proceedings of the IEEE Custom Integrated Circuits Conference, 2005, (pp. 533 536, 18 21). 7. S. Kazeminia, Kh. Hadidi and A. Khoei, A Low Jitter 110MHz 16-Phase Delay Locked Loop Based on a Simple and Sensitive Phase Detector, 21st Iranian Conference on Electrical Engineering, ICEE 2013, May 2013. 8. J. Kim and et Al., A Low-Jitter Mixed-Mode DLL for High-Speed DRAM Applications, IEEE Journal of Solid-State Circuits, Vol.35, No.10, October 2000. 9. H-H Chang, J-W Lin, C-Y Yang, and S-I Liu, A Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle, IEEE Journal of Solid-State CircuitsVol. 37, No. 8, pp August 2002. 10. H-G Park, S.Y. Kim, K-Y Lee, A low power DLL based clock and data recovery circuit with wide range anti-harmonic lock, Analog Integrated Circuits and Signal Processing, Springer, pp: 355-364. October 2012. 11. D. J. Foley and et Al., CMOS DLL-Based 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature Compensated Tunable Oscillator, IEEE Journal of Solid-State Circuits, Vol. 36, NO. 3, March 2001. 12. R.C-H. Chang, H-M Chen and P-J. Huang, A Multi-Phase-Output Delay-Locked Loop with a Novel Star-Controlled Phase/Frequency Detector, IEEE Transactions on Circuits and Systems-I, March 2008, Vol. 55, No. 9, pp: 2483-2490. 13. C-C. Chen and S-I. Liu, An Infinite Phase Shift Delay-Locked Loop with Voltage-Controlled Sawtooth Delay Line, IEEE Journal of Solid-State Circuits, Nov 2007, Vol. 43, No. 11, pp: 2413-2421. 14. Cheng Jia, Linda Milor, A DLL Design for Testing I/O Setup and Hold Times, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(9), Vol. 17, No. 11, pp: 1718-1722, November 2009. 15. Moazedi M, Abrishamifar A, Ghanaatian A, A low-power multiphase-delay-locked loop with a self-biased charge pump and wide-range linear delay element, Cyber Journals, Multidisciplinary Journals in Science and Technology, Journal of Selected Areas in Microelectronics (JSAM). April 2011:1-8. 16. S. Mohammadi-Mohaghegh and R. Sabbaghi-Nadooshan, A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology, British Journal of Applied Science & Technology, Vol: 3, Issue: 4, October-December 2013, pp:1187-1200.