December 22, 2004 Matrix Semiconductor 11247-01-99 One Time Programmable Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
Table of Contents Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Polysilicon Diodes with Oxide Anti-Fuse 3.7 Transistors 3.8 Isolation 3.9 Wells and Epi 4 3D Memory Cell Analysis 4.1 Introduction 4.2 3D Memory Plan-View Analysis 4.3 3D Memory Cross-Section 4.4 Memory Density Analysis 5 Materials Analysis 5.1 TEM-EDS Analysis of Dielectrics, Metals and Transistors 5.2 FESEM EDS Analysis of Die 5.3 Spreading Resistance Profiles
Table of Contents Structural Analysis 6 Critical Dimension 6.1 Horizontal Dimensions 6.2 Vertical Dimensions 7 Appendix Report Evaluation
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Juiceware TM Media Chip Vendor Packaging 2.1.2 Juiceware TM Media Cartridge Top View 2.1.3 Juiceware TM Media Cartridge Inside View 2.1.4 Package Top 2.1.5 Package Bottom 2.1.6 TSOP Pin Diagram 2.1.7 Plan-View Package X-Ray 2.1.8 Side-View Package X-Ray 2.1.9 Die Photograph 2.1.10 Die Markings 2.1.11 Die Photograph at Metal 1 2.2.1 Die Corner a 2.2.2 Die Corner b 2.2.3 Die Corner c 2.2.4 Die Corner d 2.2.5 Bond Pads 2.2.6 Minimum Pitch Bond Pads 3 Process Analysis 3.1.1 General Structure 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Ball Bond to Bond Pad 3.2.2 Ball Bond to Bond Pad - Left 3.2.3 Ball Bond to Bond Pad - Right 3.2.4 Bond Pad Edge Figure 3.2.5 3.3.1 Passivation 3.3.2 TEM Image of Passivation 3.3.3 ILD 6 3.3.4 ILD 5 Through ILD 1 General Dielectric Structure 3.3.5 ILD 5 and ILD 4 3.3.6 ILD 3 and ILD 2 3.3.7 ILD 2
Overview 1-2 3.3.8 ILD 1 and PMD 3.3.9 ILD 1 3.3.10 PMD and STI 3.3.11 TEM of PMD-4 3.4.1 Metal 7 3.4.2 TEM Image of Metal 7 3.4.3 Minimum Pitch Metal 6 3.4.4 Minimum Pitch Metal 5 3.4.5 Minimum Pitch Metal 4 3.4.6 Minimum Pitch Metal 3 3.4.7 TEM Image of Minimum Pitch Metal 3 and Metal 4 3.4.8 TEM of Metal 3 3.4.9 Minimum Pitch Metal 2 3.4.10 TEM of Metal 2 3.4.11 Minimum Pitch Metal 1 3.4.12 TEM Image of Metal 1 3.5.1 General Structure Vias and Contacts 3.5.2 Minimum Pitch Via 6 3.5.3 Wide Via 2-6 3.5.4 Complex Via 2-6 3.5.5 TEM Image of Complex Via 2-6 3.5.6 Minimum Pitch Via 2-6 3.5.7 Minimum Pitch Via 1 3.5.8 TEM Image of Minimum Pitch Via 1 3.5.9 TEM Image of Via 1 - Top 3.5.10 Minimum Pitch Contacts to Diffusion 3.5.11 Contact to Poly 3.5.12 TEM Image of Contact - Top 3.5.13 TEM Image of Contact to Diffusion - Bottom 3.6.1 Polysilicon Diodes (Cross-Section 1; Silicon Etch) 3.6.2 Polysilicon Diodes (Cross-Section 2; Glass Etch) 3.6.3 TEM Image of Polysilicon Diodes 3.6.4 SCM Image of Polysilicon Diode Anti-Fuses (Cross-Section 1) 3.6.5 TEM Image of Polysilicon Diode Bottom 3.6.6 TEM Image of Polysilicon Diode with Anti-Fuse Oxide Top 3.6.7 TEM Image of Polysilicon Diode Anti- Fuse Oxide Top Left 3.6.8 TEM Image of Polysilicon Diode Anti-Fuse Oxide
Overview 1-3 3.7.1 Minimium Gate Length MOS Transistor (Glass Etch) 3.7.2 Minimum Gate Length NMOS Transistor (Silicon Etch) 3.7.3 Minimum Gate Length PMOS Transistor (Silicon Etch) 3.7.4 Minimum Gate Length NMOS Transistor (Silicon Etch) 3.7.5 Minimum Pitch Polycide 3.7.6 Large High Voltage NMOS Transistor 3.7.7 TEM Image of Large High Voltage NMOS Transistor 3.7.8 TEM Image of Large High Voltage NMOS Transistor Detail 3.7.9 TEM Image of Thick Gate Oxide 3.7.10 TEM Image of Thin Gate Oxide 3.8.1 Minimum Width STI 3.8.2 Polycide Gate Over STI 3.8.3 Polycide Ending Over STI 3.9.1 SCM Profile of N-well and P-well 4 3D Memory Cell Analysis 4.1.1 Schematic Diagram of 3D Memory Structure 4.2.1 Annotated Die Photo 4.2.2 Memory Array at Metal 6 (Word Lines) 4.2.3 Memory Array at Poly 3 Diode 4.2.4 Memory Array at Metal 5 (Bit Lines) 4.2.5 Memory Array at Metal 4 (Word Lines) 4.2.6 Memory Array at Poly 2 Diode 4.2.7 3D Memory at Metal 3 (Bit Lines) 4.3.1 3D Memory Cross-Section (Word Line Direction) 4.3.2 3D Memory Cross-Section (Bit Line Direction) 4.3.3 TEM Image of 3D Memory Cell 4.3.4 TEM Image of Memory Diode Anode and Anti-fuse Oxide 4.3.5 TEM Image of 3D Memory Diode Cathode 5 Materials Analysis 5.1.1 FESEM Image of 11247-01-99 General Structure 5.1.2 TEM EDS Spectrum of Passivation 5 Nitride 5.1.3 TEM EDS Spectrum of Passivation 4 Oxide 5.1.4 TEM EDS Spectrum of Passivation 3 Oxide 5.1.5 TEM EDS Spectrum of Passivation 2 Oxide 5.1.6 TEM EDS Spectrum of ILD 6-2 Oxide
Overview 1-4 5.1.7 TEM EDS Spectrum of ILD 6-1 Oxide 5.1.8 TEM EDS Spectrum of ILD 5-2 Oxide 5.1.9 TEM EDS Spectrum of ILD 5-1 Oxide 5.1.10 TEM EDS Spectrum of ILD 4 Oxide 5.1.11 TEM EDS Spectrum of ILD 2-2 Oxide 5.1.12 TEM EDS Spectrum of ILD 2-1 Oxide 5.1.13 TEM EDS Spectrum of PMD-4 Oxynitride 5.1.14 TEM EDS Spectrum of PMD-3 Oxide 5.1.15 TEM EDS Spectrum of PMD-2 PSG 5.1.16 TEM EDS Spectrum of PMD-1 Nitride 5.1.17 TEM EDS Spectrum of Metal 7 Barrier TiN/Ti 5.1.18 TEM EDS Spectrum of Metal 9 Cap TiN 5.1.19 TEM EDS Spectrum of Metal 5 TiN Barrier 5.1.20 TEM EDS Spectrum of Metal 3 TiN Below Poly Diode 5.1.21 TEM EDS Spectrum of Transistor Gate Cobalt Silicide 5.1.22 Contact Cobalt Silicide 5.2.1 FESEM EDS Spectrum of Metal 7 Aluminum 5.2.2 FESEM EDS Spectrum of Tungsten Metal 5.3.1 SRP of N-Well 5.3.2 SRP of P-well 1.2 List of Tables 2.2.1 Package and Die Dimensions 3.3.1 Dielectrics Vertical Dimensions 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Vias and Contacts Horizontal Dimensions 3.6.1 Summary Polysilicon Diode with Anti-Fuse Oxide Dimensions 3.7.1 Transistor and Polycide Horizontal Dimensions 3.7.2 Transistor and Polycide Vertical Dimension 3.8.1 Isolation Horizontal Dimension 3.9.1 Wells and Epi Vertical Dimensions 4.4.1 Memory Density Analysis 5.1.1 Summary of Dielectric Composition
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