Features l Advanced Process Technology l Ultra Low On-Resistance l 75 C Operating Temperature l Fast Switching l Repetitive Avalanche Allowed up to Tjmax l Lead-Free Description This HEXFET Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this product are a 75 C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in a wide variety of applications. Absolute Maximum Ratings IRLR395PbF IRLU395PbF HEXFET Power MOSFET V DSS = 55V R DS(on) = 4mΩ I D = 30A Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V (Silicon limited) 6 I D @ T C = 0 C Continuous Drain Current, V GS @ V (See Fig.9) 43 A I D @ T C = 25 C Continuous Drain Current, V GS @ V (Package limited) 30 I DM Pulsed Drain Current 240 P D @T C = 25 C Power Dissipation 20 W Linear Derating Factor 0.77 W/ C V GS Gate-to-Source Voltage ± 6 V E AS Single Pulse Avalanche Energy 200 mj E AS (6 sigma) Single Pulse Avalanche Energy Tested Value 600 I AR Avalanche Current See Fig.2a, 2b, 5, 6 A E AR Repetitive Avalanche Energy mj T J Operating Junction and -55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 300 (.6mm from case ) C Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case.3 R θja Junction-to-Ambient (PCB mount)ˆ 50 C/W R θja Junction-to-Ambient HEXFET(R) is a registered trademark of International Rectifier. www.irf.com G D S D-Pak IRLR395PbF PD - 95090B I-Pak IRLU395PbF /0/
IRLR/U395PbF Electrical Characteristics @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 55 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.057 V/ C Reference to 25 C, I D = ma R DS(on) Static Drain-to-Source On-Resistance 2 4 V GS = V, I D = 30A mω 4 7 V GS = 5.0V, I D = 26A V GS(th) Gate Threshold Voltage.0 3.0 V V DS = V, I D = 250µA g fs Forward Transconductance 42 S V DS = 25V, I D = 30A I DSS Drain-to-Source Leakage Current 20 V DS = 55V, V GS = 0V µa 250 V DS = 55V, V GS = 0V, T J = 25 C Gate-to-Source Forward Leakage 200 V GS = 6V I GSS na Gate-to-Source Reverse Leakage -200 V GS = -6V Q g Total Gate Charge 6 92 I D = 30A Q gs Gate-to-Source Charge 9.0 4 nc V DS = 44V Q gd Gate-to-Drain ("Miller") Charge 7 25 V GS = V t d(on) Turn-On Delay Time 7.4 V DD = 28V ns t r Rise Time 5 I D = 30A t d(off) Turn-Off Delay Time 83 R G = 8.5Ω t f Fall Time 0 V GS = V Between lead, D L D Internal Drain Inductance 4.5 nh 6mm (0.25in.) L S Internal Source Inductance 7.5 from package G and center of die contact S C iss Input Capacitance 870 V GS = 0V C oss Output Capacitance 390 V DS = 25V C rss Reverse Transfer Capacitance 74 pf ƒ =.0MHz, See Fig. 5 C oss Output Capacitance 2380 V GS = 0V, V DS =.0V, ƒ =.0MHz C oss Output Capacitance 290 V GS = 0V, V DS = 44V, ƒ =.0MHz C oss eff. Effective Output Capacitance 540 V GS = 0V, V DS = 0V to 44V Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 6 (Body Diode) showing the A I SM Pulsed Source Current integral reverse G 240 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage.3 V T J = 25 C, I S = 30A, V GS = 0V t rr Reverse Recovery Time 62 93 ns T J = 25 C, I F = 30A, V DD = 25xjkl V Q rr Reverse Recovery Charge 70 nc di/dt = 0A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (Α) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) G fs, Forward Transconductance (S) IRLR/U395PbF 000 00 0 VGS TOP 5V V 5.0V 3.0V 2.7V 2.5V 2.25V BOTTOM 2.0V 00 0 2.0V VGS TOP 5V V 5.0V 3.0V 2.7V 2.5V 2.25V BOTTOM 2.0V 0. 2.0V 0.0 0.00 20µs PULSE WIDTH Tj = 25 C 0. 0 00 V DS, Drain-to-Source Voltage (V) 0. 20µs PULSE WIDTH Tj = 75 C 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 00.00 70 0.00 T J = 25 C T J = 75 C 60 50 T J = 25 C.00 40 30 T J = 75 C.00 20 V DS = 25V 20µs PULSE WIDTH 0..0 3.0 5.0 7.0 9.0.0 3.0 5.0 V GS, Gate-to-Source Voltage (V) 0 0 20 30 40 50 60 I D,Drain-to-Source Current (A) Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance vs. Drain Current www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance(pF) IRLR/U395PbF 0000 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 2 I = D 30A V DS V DS V DS = 44V = 27V = V 00 0 C iss C oss C rss V GS, Gate-to-Source Voltage (V) 8 6 4 2 0 V DS, Drain-to-Source Voltage (V) 0 0 20 30 40 50 60 70 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 00 00 OPERATION IN THIS AREA LIMITED BY R DS (on) 0 I SD, Reverse Drain Current (A) T = 75 J C T = 25 J C V GS = 0 V 0. 0.0 0.5.0.5 2.0 V SD,Source-to-Drain Voltage (V) 0 Tc = 25 C Tj = 75 C Single Pulse 0µsec msec msec 0 00 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
IRLR/U395PbF 70 LIMITED BY PACKAGE 2.5 I D = 6A 60 2.0 I D, Drain Current (A) 50 40 30 20 0 25 50 75 0 25 50 75 T, Case Temperature ( C C) R DS(on), Drain-to-Source On Resistance (Normalized).5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 0 20 40 60 80 T J, Junction Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Normalized On-Resistance vs. Temperature Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 0.02 0.0 SINGLE PULSE (THERMAL RESPONSE) P DM t t 2 Notes:. Duty factor D = t / t 2 2. Peak T J = P DM x Z thjc T C 0.0 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (sec) Fig. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
V GS(th) Gate threshold Voltage (V) IRLR/U395PbF R G V DS 20V V GS tp Fig 2a. Unclamped Inductive Test Circuit tp L D.U.T IAS 0.0Ω V (BR)DSS 5V DRIVER - V DD A E AS, Single Pulse Avalanche Energy (mj) 500 400 300 200 0 TOP BOTTOM 0 25 50 75 0 25 50 75 Starting Tj, Junction Temperature ( C) I D 2A 2A 30A I AS Fig 2b. Unclamped Inductive Waveforms Q G Fig 2c. Maximum Avalanche Energy vs. Drain Current V Q GS Q GD 2.0 V G 2V V GS Current Regulator Same Type as D.U.T..2µF 50KΩ 3mA.3µF Charge Fig 3a. Basic Gate Charge Waveform D.U.T. V - DS.5 I D = 250µA.0 0.5-75 -50-25 0 25 50 75 0 25 50 75 200 T J, Temperature ( C ) I G I D Current Sampling Resistors Fig 3b. Gate Charge Test Circuit Fig 4. Threshold Voltage vs. Temperature 6 www.irf.com
Avalanche Current (A) E AR, Avalanche Energy (mj) IRLR/U395PbF 00 Duty Cycle = Single Pulse 0 0.0 0.05 0. Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25 C due to avalanche losses 0..0E-08.0E-07.0E-06.0E-05.0E-04.0E-03.0E-02.0E-0 tav (sec) Fig 5. Typical Avalanche Current vs.pulsewidth 220 200 80 60 40 20 0 80 60 40 20 0 TOP Single Pulse BOTTOM % Duty Cycle I D = 30A 25 50 75 0 25 50 75 Starting T J, Junction Temperature ( C) Notes on Repetitive Avalanche Curves, Figures 5, 6: (For further info, see AN-05 at www.irf.com). Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 2a, 2b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 5, 6). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see figure ) P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc Fig 6. Maximum Avalanche Energy I av = 2DT/ [.3 BV Z th ] vs. Temperature E AS (AR) = P D (ave) t av www.irf.com 7
IRLR/U395PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 7. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs V DS R D R G V GS D.U.T. - V DD V Pulse Width µs Duty Factor 0. % Fig 8a. Switching Time Test Circuit V DS 90% % V GS t d(on) t r t d(off) t f Fig 8b. Switching Time Waveforms 8 www.irf.com
IRLR/U395PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR20 WITH ASSEMBLY LOT CODE 234 ASSEMBLED ON WW 6, 200 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" "P" in assembly line position indicates "Lead-Free" qualification to the consumer-level INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFR20 6A 2 34 PART NUMBER DATE CODE YEAR = 200 WEEK 6 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFR20 2 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR = 200 WEEK 6 A = ASSEMBLY SITE CODE Notes:. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com 9
IRLR/U395PbF I-Pak (TO-25AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-25AA) Part Marking Information EXAMPLE: THIS IS AN IRFU20 WITH ASSEMBLY LOT CODE 5678 ASS EMBLED ON WW 9, 200 IN THE ASSEMBLY LINE "A" Note: "P" in assembly line position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU20 9A 56 78 PART NUMBER DATE CODE YEAR = 200 WEEK 9 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU20 56 78 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR = 200 WEEK 9 A = AS S EMBLY S ITE CODE Notes:. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing please refer to IR website at http://www.irf.com/package/ www.irf.com
IRLR/U395PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 6.3 (.64 ) 5.7 (.69 ) 6.3 (.64 ) 5.7 (.69 ) 2. (.476 ).9 (.469 ) FEED DIRECTION 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-48 & EIA-54. 3 INCH NOTES :. OUTLINE CONFORMS TO EIA-48. Notes: Repetitive rating; pulse width limited by max. junction temperature. (See fig. ). Limited by T Jmax, starting T J = 25 C, L = 0.45mH, R G = 25Ω, I AS = 30A, V GS =V. Part not recommended for use above this value. ƒ I SD 30A, di/dt 280A/µs, V DD V (BR)DSS, T J 75 C. Pulse width.0ms; duty cycle 2%. 6 mm C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS. Limited by T Jmax, see Fig.2a, 2b, 5, 6 for typical repetitive avalanche performance. This value determined from sample failure population. 0% tested to this value in production. ˆ When mounted on " square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information. /20 www.irf.com