SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging Xiaofei Wang,2 Weichao Xu 2 and Chris H. Kim 2 Intel Corporation, Hillsboro 2 University of Minnesota, Twin Cities xiaofei.wang@intel.com
Asymmetric BTI Aging Effects Duty-Cycle (%) 57 56 55 54 53 52 5 50 2.2V 2.2V 2.2V 2.0V.8V Test Chip Die Photo.2V, 65nm LP 40 C 80 C 20 C 20 C 20 C T CLK =ns, t d =0.5ns 0 0 3 0 5 Stress Time (s) When input is static, PMOS and NMOS in a signal path are alternately stressed In active mode, the st edge propagates through unstressed devices while 2 nd edge propagates through stressed devices only Asymmetric BTI aging 2
Voltage (V) SRAM Timing Path Aging TT, 80 C, 52X256 SRAM Subarray WL.0 0.5 CLK Enable CLK Clock Gater : NBTI : PBTI Pre-decoder Decoder SRAM Ctrl Timing Gen. Paths Driver PRE, SAEN, YSEL, etc..0 0.5.0 0.5 BL PREB BLB WL SAEN After stress Phase Phase 0 Address Decoding WL Driving BL/BLB Discharging SA Sensing BL Precharging Data Latching.0 0.5.0 0.5 YSELB SAOUTB : Fresh : 20% V t Shift SAOUT DOUT.75n 2n 2.25n 2.5n 2.75n Time (s) Internal timing signal paths for SRAM operation are DC stressed when clock is gated off Affects the duty-cycle of critical signals such as WL, SAE, precharge, etc. lower operating frequency 3
SRAM Read Frequency Odometer Structure Test Unit Ctrl Signals VCO Addr. Ctrl. FSM & Mode Ctrl Scan chain Scan In Stressed 6kb SRAM Array Address DOUT Power Switches Address Fresh 6kb SRAM Array DOUT Str. Ref. BFD Data Out Row Decoder Pre-dec. + Timing Column Peripheral One of the two identical 6kb SRAM arrays is stressed, the other one is kept fresh 28X8 Subarray SRAM Array 28X28 28X8 Subarray The dataout signal is looped back to generate selfoscillating signal 28 Ctrl. Stress BL Measure BLB 8 8 Loop back DC stress BL Clock Gen. BLB 8 8 28X8 Subarray BL BLB 8 8 DOUT Data Latch 4
Clock Loop Back Self-Oscillation Read Waveforms Decoding Path WL BL BLB X28 MEAS Start measurement mode Write Driver Controllable delay WE SET RESET Timing Control Circuit DIN PREC CLK T=T d (CLK Data) Feedback Loop YSEL WL PREC MEAS RESET SET DOUT SAOUT BLB BL YSEL SAE MEAS RESET SET SAOUTB SAOUT SAOUTB DOUT Clock Gen. 5
Use Beat Frequency to Detect Aging (/3) Stressed SRAM Reference SRAM A B Phase Comp. Beat Frequency Counter f str : 0.99GHz A B f ref :.00GHz Phase comparator is used to generate the beat frequency At time zero the stressed ROSC is trimmed to be slightly slower than the reference ROSC 6
Use Beat Frequency to Detect Aging (2/3) Stressed SRAM Reference SRAM A B Phase Comp. C Beat Frequency Counter PC_OUT (f beat = f ref - f stress ) Couter: N=00 B C A Phase comparator output: f beat =f ref -f stress Counter counters the number of reference cycle in one period of the beat signal N=(f str -f ref )/f ref 7
Use Beat Frequency to Detect Aging (3/3) Stressed SRAM Reference SRAM A B Phase Comp. C Beat Frequency Counter f stress (GHz): f ref :.00GHz PC_OUT (f beat = f ref - f stress ) Counter: 0.99 N=00 0.98 N=50 % frequency difference before stress N=00 2% frequency difference after stress N=50 Δf or ΔT sensing resolution is 0.0% 8
32nm SRAM Test Chip and Features 9
Degradation of f read with Stress Time Occurrences (%) 35 30 25 20 5 0 5 t=0s (fresh) t=27s t=000s µ=.28 σ=0.0099 Stressed @.8V, 25 C µ=.32 σ=0.0057 µ=.35 σ=0.0043 Decreased µ Increased σ fread Average (GHz).35.3.25.2.5..05 t=0s Stressed @.8V, 25 C µ (GHz) σ (GHz) 0.05 0.04 0.03 0.02 fread Std. Dev. (GHz) 0.25.3.35.4 f read (GHz) 0.0 0 0 3 0 5 Stress Time (s) Mean value (µ) of f read decreases with stress time while its standard deviation (σ) increases BTI induced σ is comparable to that of process variation induced σ for given stress condition 0
Distribution of f read at Different Stress Voltage Occurrences (%) 60 50 40 30 20 0.4V.6V.8V µ decreases; σ increases µ=.28 σ=0.0 Stressed @25 C for 500s µ=.33 σ=0.0065 µ=.34 σ=0.0048 0.25.3.35 f read (GHz) Mean value (µ) of f read decreases with higher stress voltage while its standard deviation (σ) increases
Degradation of f read with Stress Voltage Δfread Average (%) 00 0.8V, n=0.24.6v, n=0.24.4v, n=0.20 Stressed @25 C Δfread Std. Dev. (%) 0 Stressed @25 C.8V, n=0.6.6v, n=0.07.4v, n=0.04 0. 0-0 0 3 0 5 Stress Time (s) 0. 0-0 0 3 0 5 Stress Time (s) σ of the SRAM read frequency degradation (Δf read ) follow power law dependence (t n ) as µ, due to discrete random charge fluctuation Larger degradation at higher stress voltages 2
Impact of Temperature on the Degradation of f read Δfread Average (%) 0 0. Stressed @.8V Stressed @.8V : 25 C, n=0.27 : 35 C, n=0.24 0-0 0 2 0 3 Stress Time (s) The magnitudes of both µ and σ of Δfread at 35 C are more than twice of those at 25 C. Δfread Std. Dev. (%) 0. : 25 C, n=0.4 : 35 C, n=0.09 0-0 0 2 0 3 Stress Time (s) 3
Slope distribution of f read Aging Occurrences (%) 25 20 5 0 5.4V.6V.8V 0 0. 0.5 0.2 0.25 Stressed @ 25 C 25 C Stressed @.8V 35 C 0. 0.5 0.2 0.25 0.3 Time Exponent n The voltage and temperature have little impact on the BTI time slope distribution 4
Reduced SRAM Read Error Rate f read (GHz):.0.35 Failure Column # 8 8 Fresh (short WL pulse width) Stressed at 2.25V for 2000s, then recovered at 0V for 2000s. 64 28 Row # Bit failure rate =.3% Bit failure rate =3.2% Bit failure rate is reduced after stress due to the relaxed WL pulse width 5
Summary Impact of asymmetric BTI aging on SRAM read speed studied for the first time An SRAM read speed odometer based on the beat-frequency detection concept was implemented in HKMG technology with ps resolution and μs measurement interruption SRAM read speed degrades due to the delayed SAE signal SRAM read failure rate decreases after stress due to the relaxed WL pulse width 6