Intelligent Power Module (IPM) 600 V, 0 A Overview This Inverter IPM includes the output stage of a 3-phase inverter, pre-drive circuits, bootstrap circuits, and protection circuits in one package. Function SIP (single in-line package) of the transfer full mold structure. The emitter line of the each lower phase outputs to an external terminal with the option of control using 3-phase current detection with external resistors. Direct input of CMOS level control signals without an insulating circuit is possible. Protective circuits including over current and pre-drive low voltage protection are built in. A single power supply drive is enabled through the use of bootstrap circuits for upper IGBT gate drives. Built-in dead-time for shoot-thru protection. Internal substrate temperature is measured with an internal pulled up thermistor. Certification UL557 (File Number : E3395) Specifications Absolute Maximum Ratings at Tc = 5 C Parameter Symbol Conditions Ratings Unit Supply voltage VCC V+ to VRU(VRV,VRW), surge < 500 V * 50 V Collector-emitter voltage VCE V+ to U(V,W) or U(V,W) to VRU(VRV,VRW) 600 V V+, VRU,VRV,VRW, U,V,W terminal current ±0 A Output current Io V+, VRU,VRV,VRW, U,V,W terminal current at Tc = 00 C ±6 A V+, VRU,VRV,VRW, U,V,W terminal current for a pulse width Output peak current Iop ±0 A of ms Pre-driver voltage VD,,3, VB to U, VB to V, VB3 to W, VDD to VSS * 0 V Input signal voltage VIN HIN,, 3, LIN,, 3 terminals 0.3 to 7 V ITRIP terminal voltage VITRIP ITRIP terminal VSS+5 V Maximum power dissipation Pd IGBT per channel W Junction temperature Tj IGBT,FRD 50 C Storage temperature Tstg 0 to +5 C Operating case temperature Tc IPM case temperature 0 to +00 C Tightening torque Case mounting screws *3 0.9 Nm Withstand voltage Vis 50 Hz sine wave AC minute * 000 VRMS Reference voltage is VSS terminal voltage unless otherwise specified. * : Surge voltage developed by the switching operation due to the wiring inductance between V+ and VRU(VRV,VRW) terminals. * : VD = VB to U, VD = VB to V, VD3 = VB3 to W, VD = VDD to VSS terminal voltage. *3 : Flatness of the heat-sink should be less than 50 m to +00 m. * : Test conditions : AC 500 V, second. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. Semiconductor Components Industries, LLC, 06 Publication Order Number : December 06 - Rev. 3 STK5UC6K-E/D
Electrical Characteristics at Tc 5 C, VD, VD, VD3, VD = 5 V Parameter Symbol Conditions Test circuit Ratings min typ max Power output section Collector-emitter cut-off current ICE VCE = 600 V - - 0. ma Fig. Bootstrap diode reverse current IR(BD) VR(BD) = 600 V - - 0. ma Collector to emitter saturation Io = 0 A, Tj = 5 C -..3 VCE(SAT) Fig. V voltage Io = 5 A, Tj = 00 C -.3 - Io = 0 A, Tj = 5 C -.3. Diode forward voltage VF Fig.3 V Io = 5 A, Tj = 00 C -. - Bootstrap diode forward voltage VF(BD) IF = 0. A - -.0 - V Resistor value for common boot RBC - - - charge line Bootstrap circuit resistance Ω Resister values for separate RBS - - 0 - boot charge lines θj-c(t) IGBT -.5 5.5 Junction to case thermal resistance θj-c(d) FRD - - 5.5 6.5 C/W Thermal resistance case to sink Rth(c-s) W/mK thermal conductivity * - 0. - Protection section FAULT clearance delay time FLTCLR Form time fault condition clears - 6 9 ms t ON Io = 0 A - 0. - Switching time Fig.5 t OFF Inductive load - 0.5 - Reference voltage is VSS terminal voltage unless otherwise specified. * : At 00 μm thickness of the thermal grease. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. Unit μs Electrical Characteristics Driver Function at Tc 5 C Parameter Symbol Test circuit Ratings min typ max Unit Supply section VDD and VBS supply undervoltage protection reset VDD and VBS supply undervoltage protection set V DDUV+ V BSUV+ V DDUV- V BSUV- - 0.5..7 V - 0.3 0.9.5 V VDD and VBS supply undervoltage hysteresis V DDUVH V BSUVH - 0. 0. - V Quiescent VDD supply current I QDD -.0.0 ma Fig. Quiescent VBS supply current I QBS - 0.0 0. ma Input section Logic low input voltage V INL - - - 0. V Logic high input voltage V INH -.5 - V Logic 0 input leakage current I IN+ - 76 60 μa Logic input leakage current I IN- - 97 50 03 μa ITRIP threshold voltage (OUT = LO or OUT = HI) V ITRIP - 3.67.7.67 V Dynamic section Dead time (Internal dead time injected by driver) DT - 0 300 30 ns ITRIP to shutdown propagation delay t ITRIP -.0.. μs ITRIP blanking time t ITRPBL - - 0.9 - μs Reference voltage is VSS terminal voltage unless otherwise specified.
Switching Characteristics at Tc 5 C, VD, VD, VD3, VD = 5 V Parameter Symbol Conditions Ratings min typ max Turn-on switching loss Eon IC = 5 A, V+ = 00 V - 95 - μj Turn-off switching loss Eoff VDD = 5 V, L = 3.9 mh, - - μj Total switching loss Etot Tc = 5 C - 37 - μj Turn-on switching loss Eon IC = 5 A, V+ = 00 V, - - μj Turn-off switching loss Eoff VDD = 5 V, L = 3.9 mh, - 6 - μj Total switching loss Etot Tc = 00 C - 0 - μj Diode reverse recovery time trr IF = 5A, V+ = 00 V, VDD = 5 V, L = 3.9 mh, Tc = 00 C Unit - 70 - ns Reverse bias safe operating area RBSOA Io = 0 A, VCE = 50 V FULL SQUARE - Short circuit safe operating area SCSOA VCE = 00 V - - μs VDD = VB = VB = VB3 = 5 V, VSS = VS = VS = VS3 = 0 V, outputs loaded with nf, all voltage are referenced to VSS ; unless otherwise noted. Internal NTC-Thermistor Characteristics Parameter Conditions Typ. Unit R5 Resistance Tc = 5 C 00 ±3% kω R5 Resistance Tc = 5 C.5 ±3% kω B B-Constant (5 to 50 C) R = R e [B(/T-/T)] 50 ±% K Temperature range - 0 to +5 C Typ. Dissipation constant Tc=5 C mw/ C Notes. The pre-drive power supply low voltage protection has approximately 00 mv of hysteresis and operates as follows. Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn high. Lower side : The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm. 3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction.. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). 3
Equivalent Block Diagram VB3 () W,VS3 () VB () V,VS (5) VB (7) U,VS () RBS RBS RBS V+ (0) BD BD BD U.V. U.V. U.V. RBC VRU () VRV (3) VRW () Level Shifter Level Shifter Level Shifter HIN (5) HIN (6) HIN3 (7) Logic Logic Logic LIN () LIN (9) LIN3 (0) Thermistor T/ITRIP () VDD () Shut down Under voltage DETECT Timer S R Q VSS (3) Vref Latch time about 9ms Module Pin-Out Description Pin Name Description Pin Name Description VB3 High Side Floating Supply Voltage 3 VRU Low Side Emitter Connection Phase W, VS3 Output 3, High Side Floating Supply Offset Voltage 3 3 VRV Low Side Emitter Connection Phase 3 - Without pin VRW Low Side Emitter Connection Phase 3 VB High Side Floating Supply Voltage 5 HIN Logic Input High Side Gate Driver Phase 5 V, VS Output, High Side Floating Supply Offset Voltage 6 HIN Logic Input High Side Gate Driver Phase 6 - Without pin 7 HIN3 Logic Input High Side Gate Driver Phase 3 7 VB High Side Floating Supply Voltage LIN Logic Input Low Side Gate Driver Phase U, VS Output, High Side Floating Supply Offset Voltage 9 LIN Logic Input Low Side Gate Driver Phase 9 - Without pin 0 LIN3 Logic Input Low Side Gate Driver Phase 3 0 V+ Positive Bus Input Voltage T/Itrip Temperature Monitor and Shut-down Pin - Without pin VDD +5 V Main Supply - - - 3 VSS Negative Main Supply
Test Circuit The tested phase U+ shows the upper side of the U phase and U- shows the lower side of the U phase. ICE / IR(BD) U+ V+ W+ U- V- W- M 0 0 0 5 VD=5V 7 M A ICE N 5 3 VD=5V 5 VCE U(BD) V(BD) W(BD) M 7 VD3=5V N 3 3 3 VD=5V 3 N Fig. VCE(SAT) (test by pulse) U+ V+ W+ U- V- W- M 0 0 0 5 VD=5V 7 M N 5 3 m 5 6 7 9 0 VD=5V 5 Io V VD3=5V VCE(SAT) VD=5V m 3 N Fig. VF (test by pulse) U+ V+ W+ U- V- W- M M 0 0 0 5 V VF Io N 5 3 N Fig. 3 ID VD VD VD3 VD ID A M M 7 VD* N 5 3 N Fig. 5
Switching time (The circuit is a representative example of the lower side U phase.) Input signal ( 0 to 5V ) VD=5V VD=5V 7 5 0 VCC Io 90% VD3=5V CS 0% VD=5V Io Input signal ton toff 3 Fig. 5 RB-SOA (The circuit is a representative example of the lower side U phase.) Input signal ( 0 to 5V ) VD=5V VD=5V 7 5 0 VCC Io VD3=5V CS VD=5V Io Input signal 3 Fig. 6 6
Input / Output Timing Diagram OFF VBS undervoltage protection reset signal HIN,,3 ON LIN,,3 VDD * VDD undervoltage protection reset voltage VB,,3 VBS undervoltage protection reset voltage *3 ITRIP terminal Voltage VIT.67V * VIT<3.67V Upper U, V, W ON * OFF Lower U,V, W * Automatically reset after protection (typ.9ms) Fig. 7 Notes * : Shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay externally. * : When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume immediately. *3 : When the upper side voltage at VB, VB and VB3 drops only the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gate voltage rises. * : When VITRIP exceeds threshold all IGBT s are turned off and normal operation resumes 9 ms (typ) after over current condition is removed. 7
Logic level table V+ HIN,,3 (5,6,7) LIN,,3 (,9,0) IC Driver Ho Lo U,V,W (,5,) Itrip HIN,,3 LIN,,3 U,V,W 0 0 V+ 0 0 0 0 X X X X Fig.
Sample Application Circuit STK5UC6K-E VB3 W, VS3 VB V, VS VB U, VS V+ VRU VRV VRW HIN HIN HIN3 LIN LIN LIN3 T / ITRIP VDD VSS. 5. 7. 0. 3 5 6 7 9 0 3 CB CB CB CS Control Logic + - VCC C CD VDD=5V Recommended Operating Conditions at Tc = 5 C Item Symbol Conditions Ratings min typ max Supply voltage VCC Between V+ to VRU(VRV,VRW) 0 0 50 V Pre-driver supply voltage VD,,3 Between VB to U,VB to V,VB3 to W.5 5 7.5 VD Between VDD to VSS * 3.5 5 6.5 ON-state input voltage VIN(ON) HIN,HIN,HIN3,LIN,LIN,LIN3 0-0.3 OFF-state input voltage VIN(OFF) terminal 3.0-5.0 PWM frequency fpwm - - 0 khz Dead time DT Turn-off to turn-on (External) 0.5 - - μs Mounting torque - M3 type screw 0.6-0.9 Nm * : Pre-drive power supply (VD = 5 ±.5 V) must be have the capacity of Io = 0 ma (DC), 0.5 A (Peak). Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Unit V V Usage Precaution. This IPM includes internal bootstrap diode and resistor. By adding a capacitor CB, a single high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of to 7 μf, however, this value needs to be verified prior to production. When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply.. It is essential thet wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of CS is in the range of 0. to 0 μf. 3. VRU, VRV, and VRW terminals are direct outputs of the emitter line of the each lower phase IGBT and can be used to monitor each phase s or collective current with external resistors. IF current is not monitored, each resistor should be short-circuites.. Disconnection of terminals U, V, or W during normal motor operation will cause damage to IPM, use caution with this connection. 5. Zner diode with 0 V is connected with the inside of the signal input terminal. When inputting voltage which exceeds 5 V, connect resistor between the side of the power and the signal input terminal, for the input current of the signal input terminal become equal to or less than 0.5 ma.this resistor is effective with the noise absorption of the signal terminal, too. 6. A fuse on VCC is recommended. 7. Inside the IPM, a thermistor used as the temperature monitor is connected between VDD terminal and T/ITRIP terminal, therefore, an external pull down resistor connected between the T/ITRIP terminal and VSS terminal should be used. The temperature monitor example application is as follows, please refer the Fig.0, Fig., and Fig. below.. All data shown implements an example of the application circuit but does not guarantee a design for the mass production. 9
0000 Thermistor resistance (kω) 000 Minimum Nomal Maximum 00 0-60 -0-0 0 0 0 60 0 00 0 0 Temperature ( C) Fig. 0 Variation of thermistor resistance with temperature.0 3.5 3.0 Vsense (V).5.0.5.0 0.5 0.0 Minimum Nomal Maximum 0 0 0 60 0 00 0 0 Thermistor temperature ( C) Fig. Variation of temperature sense voltage with thermistor temperature by using external bias resistance of.3 kω % and VDD = 5 V 5V VDD () Thermistor Driver IC T/ITRIP () 9.kΩ.3kΩ kω VSS (3).kΩ 7pF Fig. Sample application circuit for temperature monitoring 0
The characteristic of PWM switching frequency STK5UC6K-E Maximum RMS Output Current / Phase (A) 0 6 0 0 6 0 6 0 PWM Switching Frequency (khz) Fig. 3 Maximum sinusoidal phase current as function of switching frequency at Tc = 00 C, VCC = 00 V
Switching waveform 0 9 7 Current Voltage 500 50 00 350 Current (A) 6 5 3 300 50 00 50 Voltage (V) 00 50 0 0 - -50 0.0 0. 0. 0.6 0..0 Time (μs) Fig. IGBT Turn-on. Typical turn-on waveform at Tc = 00 C, VCC = 00 V 0 500 9 50 00 Current (A) 7 6 5 3 Current Voltage 350 300 50 00 50 Voltage (V) 00 50 0 0 - -50 0.0 0. 0. 0.6 0..0 Time (μs) Fig. 5 IGBT Turn-off. Typical turn-off waveform at Tc = 00 C, VCC = 00 V
CB capacitor value calculation for bootstrap circuit Calculate conditions Parameter Symbol Value Unit Upper side power supply VBS 5 V Total gate charge of output power IGBT at 5 V QG 9 nc Upper limit power supply low voltage protection UVLO V Upper side power dissipation IDMAX 95 μa ON time required for CB voltage to fall from 5 V to UVLO TONMAX - S Capacitance calculation formula Thus, the following formula are true VBS CB - QG - IDMAX TONMAX = UVLO CB therefore, CB = (QG + IDMAX TONMAX) / (VBS - UVLO) The relationship between TONMAX and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of to 7 μf, however, this value needs to be verified prior to production. 00 Capacitance Cb (μf) 0 0. 0.0 0. 0 00 000 Tonmax (ms) Fig. 6 TONMAX vs CB characteristic 3
VCE Ic 90% Ic 50% HIN/LIN HIN/LIN 0% Ic tr ton Fig. 7 Input to output propagation turn-on delay time Ic VCE 90% Ic 50% HIN/LIN HIN/LIN 0% Ic tf toff Fig. Input to output propagation turn-off delay time IF VCE HIN/LIN Irr trr Fig. 9 Diode reverse recovery
PACKAGE DIMENSIONS unit : mm 56.0 missing pin ;3,6,9, note note3 R.7 DB00 STK5UC6K 3. (0.9). note 3 9.0.0.0 X.0=.0.0 0.6 +0. -0.05 0.5 +0. -0.05 5.0.3 3. 0.5 6. 5.0 50.0 6.0.0 note : Mark for No. pin identification. note : The form of a character in this drawing differs from that of IPM. note3 : This indicates the lot code. The form of a character in this drawing differs from that of IPM. The tolerances of length are +/ 0.5 mm unless otherwise specified. ORDERING INFORMATION STK5UC6K-E Device Package Shipping (Qty / Packing) SIP3 (Pb-Free) / Tube ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent-marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 5