Power MOSFET IRFBN50, SiHFBN50 PRODUCT SUMMRY V DS (V) 500 R DS(on) (Ω) V GS = V 0.52 Q g (Max.) (nc) 52 Q gs (nc) 3 Q gd (nc) 8 Configuration Single FETURES Low Gate Charge Q g Results in Simple Drive Requirement Improved Gate, valanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and valanche Voltage and current Lead (Pb)-free vailable vailable RoHS* COMPLINT TO-220 G DS G D S N-Channel MOSFET PPLICTIONS Switch Mode Power Supply (SMPS) Uninterruptible Power Supply High Speed Power Switching PPLICBLE OFF LINE SMPS TOPOLOGIES Two Transistor Forward Half and Full Bridge Power Factor Correction Boost ORDERING INFORMTION Package Lead (Pb)-free SnPb TO-220 IRFBN50PbF SiHFBN50-E3 IRFBN50 SiHFBN50 BSOLUTE MXIMUM RTINGS T C = 25 C, unless otherwise noted PRMETER SYMBOL LIMIT UNIT Drain-Source Voltage V DS 500 V Gate-Source Voltage V GS ± 30 Continuous Drain Current V GS at V T C = 25 C I D T C = C 7.0 Pulsed Drain Current a I DM 44 Linear Derating Factor.3 W/ C Single Pulse valanche Energy b E S 275 mj Repetitive valanche Current a I R Repetitive valanche Energy a E R 7 mj Maximum Power Dissipation T C = 25 C P D 70 W Peak Diode Recovery dv/dt c dv/dt 6.9 V/ns Operating Junction and Storage Temperature Range T J, T stg - 55 to 50 Soldering Recommendations (Peak Temperature) for s 300 d C Mounting Torque 6-32 or M3 screw Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Starting T J = 25 C, L = 4.5 mh, R G = 25 Ω, I S = (see fig. 2). c. I SD, di/dt 40 /µs, V DD V DS, T J 50 C. d..6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply lbf in. N m Document Number: 994 S-8243-Rev. B, 2-Jul-08
IRFBN50, SiHFBN50 THERML RESISTNCE PRMETER SYMBOL TYP. MX. UNIT Maximum Junction-to-mbient R thj - 62 Case-to-Sink, Flat, Greased Surface R thcs 0.50 - C/W Maximum Junction-to-Case (Drain) R thjc - 0.75 SPECIFICTIONS T J = 25 C, unless otherwise noted PRMETER SYMBOL TEST CONDITIONS MIN. TYP. MX. UNIT Static Drain-Source Breakdown Voltage V DS V GS = 0 V, I D = 250 µ 500 - - V Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 250 µ 2.0-4.0 V Gate-Source Leakage I GSS V GS = ± 30 V - - ± n V DS = 500 V, V GS = 0 V - - 25 Zero Gate Voltage Drain Current I DSS V DS = 400 V, V GS = 0 V, T J = 50 C - - 250 µ Drain-Source On-State Resistance R DS(on) V GS = V I D = 6.6 b - - 0.52 Ω Forward Transconductance g fs V DS = 50 V, I D = 6.6 6. - - S Dynamic Input Capacitance C iss V GS = 0 V, - 423 - Output Capacitance C oss V DS = 25 V, - 208 - Reverse Transfer Capacitance C rss f =.0 MHz, see fig. 5-8. - pf V DS =.0 V, f =.0 MHz - 2000 - Output Capacitance C oss V GS = 0 V V DS = 400 V, f =.0 MHz - 55 - Effective Output Capacitance C oss eff. V DS = 0 V to 400 V - 97 - Total Gate Charge Q g - - 52 I D =, V DS = 400 V Gate-Source Charge Q gs V GS = V - - 3 nc see fig. 6 and 3 b Gate-Drain Charge Q gd - - 8 Turn-On Delay Time t d(on) - 4 - Rise Time t r V DD = 250 V, I D = - 35 - Turn-Off Delay Time t d(off) R G = 9. Ω, R D = 22 Ω, see fig. b - 32 - ns Fall Time t f - 28 - Drain-Source Body Diode Characteristics MOSFET symbol D Continuous Source-Drain Diode Current I S - - showing the integral reverse Pulsed Diode Forward Current a G I SM p - n junction diode - - 44 S Body Diode Voltage V SD T J = 25 C, I S =, V GS = 0 V b - -.5 V Body Diode Reverse t rr - 5 770 ns Recovery Time T J = 25 C, I F =, di/dt = /µs b Body Diode Reverse Recovery Charge Q rr - 3.4 5. µc Forward Turn-On Time t on Intrinsic turn-on time is negligible (turn-on is dominated by L S and L D ) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. ). b. Pulse width 300 µs; duty cycle 2 %. c. C oss effective is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80 % V DS. Document Number: 994 2 S-8243-Rev. B, 2-Jul-08
IRFBN50, SiHFBN50 TYPICL CHRCTERISTICS 25 C, unless otherwise noted I D, Drain-to-Source Current () VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V I D, Drain-to-Source Current () T J = 50 C T J = 25 C 4.5V 20µs PULSE WIDTH 0. T J = 25 C 0. V DS, Drain-to-Source Voltage (V) Fig. - Typical Output Characteristics V DS= 50V 20µs PULSE WIDTH 0. 4.0 5.0 6.0 7.0 8.0 9.0 V GS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics I D, Drain-to-Source Current () VGS TOP 5V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 20µs PULSE WIDTH 4.5V T J = 50 C V DS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics R DS(on), Drain-to-Source On Resistance (Normalized) 3.0 I D = 2.5 2.0.5.0 0.5 V GS = V 0.0-60 -40-20 0 20 40 60 80 20 40 60 T, Junction Temperature ( J C) Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 994 S-8243-Rev. B, 2-Jul-08 3
IRFBN50, SiHFBN50 C, Capacitance (pf) 2400 2000 600 200 800 400 V GS = 0V, f = MHz C iss = C gs C gd, C ds SHORTED C rss = Cgd C oss = C ds Cgd iss oss rss I SD, Reverse Drain Current () T J = 50 C T J = 25 C 0 0 V DS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage V GS = 0 V 0. 0.0 0.4 0.8.2.6 V SD,Source-to-Drain Voltage (V) Fig. 7 - Typical Source-Drain Diode Forward Voltage V GS, Gate-to-Source Voltage (V) 20 6 2 8 4 I = D 6.6 V DS = 400V V DS = 250V V DS = V FOR TEST CIRCUIT SEE FIGURE 3 0 0 20 30 40 50 Q G, Total Gate Charge (nc) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage I D, Drain Current () 0 OPERTION IN THIS RE LIMITED BY R DS(on) us us ms ms TC = 25 C TJ = 50 C Single Pulse 0. 0 00 V DS, Drain-to-Source Voltage (V) Fig. 8 - Maximum Safe Operating rea Document Number: 994 4 S-8243-Rev. B, 2-Jul-08
IRFBN50, SiHFBN50 2 V DS R D R G V GS D.U.T. - V DD I D, Drain Current () 8 6 4 2 V Pulse Width µs Duty Factor 0. % Fig. a - Switching Time Test Circuit V DS 90 % 0 25 50 75 25 50 T C, Case Temperature ( C) % V GS t d(on) t r t d(off) t f Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. b - Switching Time Waveforms Thermal Response (Z thjc ) 0. D = 0.50 0.20 0. 0.05 t 0.02 SINGLE PULSE t2 0.0 (THERML RESPONSE) Notes:. Duty factor D = t / t 2 0.0 2. Peak T J = P DM x Z thjc TC 0.0000 0.000 0.00 0.0 0. t, Rectangular Pulse Duration (s) Fig. - Maximum Effective Transient Thermal Impedance, Junction-to-Case PDM V DS 5 V t p V DS L Driver R G 20 V t p D.U.T. I S 0.0 Ω - V DD I S Fig. 2a - Unclamped Inductive Test Circuit Fig. 2b - Unclamped Inductive Waveforms Document Number: 994 S-8243-Rev. B, 2-Jul-08 5
IRFBN50, SiHFBN50 E S, Single Pulse valanche Energy (mj) 600 500 400 300 200 TOP BOTTOM I D 4.9 7.0 0 25 50 75 25 50 Starting T, Junction Temperature ( J C) Fig. 2c - Maximum valanche Energy vs. Drain Current V V G Q GS Q G Q GD Charge Fig. 3a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. 50 kω 2 V 0.2 µf 0.3 µf 660 D.U.T. V - DS V DSav, valanche Voltage (V) 640 620 600 V GS 3 m I G I D Current sampling resistors Fig. 3b - Gate Charge Test Circuit 580 0.0.0 2.0 3.0 4.0 5.0 6.0 7.0 I av, valanche Current () Fig. 2d - Typical Drain-to-Source Voltage vs. valanche Current Document Number: 994 6 S-8243-Rev. B, 2-Jul-08
IRFBN50, SiHFBN50 Peak Diode Recovery dv/dt Test Circuit D.U.T - Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by duty factor "D" D.U.T. - device under test - V DD Driver gate drive P.W. Period D = P.W. Period V GS = V* D.U.T. I SD waveform Reverse recovery current Body diode forward current di/dt D.U.T. V DS waveform Diode recovery dv/dt V DD Re-applied voltage Inductor current Body diode forward drop Ripple 5 % I SD * V GS = 5 V for logic level devices Fig. 4 - For N-Channel maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http:///ppg?994. Document Number: 994 S-8243-Rev. B, 2-Jul-08 7
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