April 25, 2005 PowerDsine/Freescale PD64004 4 Channel Power-Over-Ethernet (POE) Manager Process Review For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0515 www.chipworks.com
Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 LDMOS Transistors 3.8 Bipolar Transistors 3.9 Diffusion Resistors 3.10 Isolation 3.11 Wells and Epi 4 Critical Dimensions 4.1 Package and Die 4.2 Vertical Dimensions 4.3 Horizontal Dimensions 5 Report Evaluation
Overview 1 Overview 1.1 List of Figures 2 Package and Die 2.1.1 NETGEAR ProSafe Switch with POE Top 2.1.2 NETGEAR ProSafe Switch with POE Bottom 2.1.3 NETGEAR FS108P Board 2.1.4 PD64004 on NETGEAR FS108P Board 2.1.5 Package Top 2.1.6 Package Bottom 2.1.7 Package Top with White Sticker Removed 2.1.8 Package X-Ray 2.2.1 Die Photograph 2.2.2 Die Markings 2.2.3 Die Photograph at Metal 1 2.2.4 Die Photograph at Poly 2.2.5 Die Corner a 2.2.6 Die Corner b 2.2.7 Die Corner c 2.2.8 Die Corner d 2.2.9 Minimum Pitch Bond Pads 2.2.10 Bond Pads 2.2.11 Bipolar Transistors 2.2.12 Diodes and Resistors 2.2.13 Capacitors and Bipolar Transistors 2.2.14 Bipolar Transistors and Resistors 2.2.15 Annotated Die Photograph 3 Process 3.1.1 General Structure Including LDMOS Transistors 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Bond Pad 3.2.2 Bond Pad Edge Detail 3.3.1 General Dielectric Structure 3.3.2 Passivation 3.3.3 IMD 3 3.3.4 IMD 2 1-1
Overview 3.3.5 IMD 1 3.3.6 PMD and STI 3.3.7 PMD Detail 3.4.1 Minimum Pitch Metal 4 3.4.2 Minimum Pitch Metal 3 3.4.3 Minimum Pitch Metal 2 3.4.4 Minimum Pitch Metal 1 3.5.1 Minimum Pitch Via 3s 3.5.2 Minimum Pitch Via 2s and Via 1s 3.5.3 Minimum Pitch Contacts to Substrate 3.5.4 Contacts to Polycide and Substrate 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 Minimum Space NMOS Transistors 3.6.3 Minimum Gate Length PMOS 3.6.4 PMOS Transistors 3.6.5 MOS Transistors (Glass Etch Only) 3.6.6 Minimum Pitch MOS Transistors (Glass Etch Only) 3.7.1 LDMOS Block at Metal 1 Plan-View 3.7.2 LDMOS Metal 1 Detail Plan-View 3.7.3 LDMOS Poly Detail Plan-View 3.7.4 LDMOS Transistor at Edge of Array (Length Direction) 3.7.5 LDMOS Transistors (Length Direction) 3.7.6 LDMOS Transistor Poly Gate (Parallel to Length Direction) 3.7.7 LDMOS Transistor Poly Gate Contact (Parallel to Width Direction) 3.7.8 SCM Image of LDMOS Transistor Array Edge (Length Direction) 3.7.9 SCM Image of LDMOS Transistors Detail (Length Direction) 3.7.10 Edge of LDMOS Array Showing DTI Ring (Length Direction) 3.7.11 LDMOS Gate Metal Wiring Plan-View 3.8.1 NPN Bipolar Transistors Plan-View 3.8.2 NPN Bipolar Transistors Plan-View at Metal 1 3.8.3 NPN Bipolar Transistors Plan-View at Poly 3.8.4 NPN Bipolar Transistor 3.8.5 SCM Image of NPN Bipolar Transistor 3.8.6 NPN Bipolar Transistor Emitter and Base 3.8.7 SCM Image of NPN Bipolar Transistor Emitter and Base 3.8.8 NPN Bipolar Transistor Emitter 3.8.9 NPN Bipolar Transistor Base and Emitter 1-2
Overview 3.8.10 NPN Bipolar Transistor Base and Collector 3.9.1 Diffusion Resistors Plan-View 3.9.2 Diffusion Resistor 3.9.3 Diffusion Resistor Contacts 3.10.1 Minimum Width STI 3.10.2 Poly over STI 3.10.3 DTI 3.10.4 DTI Top Detail 3.10.5 DTI Bottom Detail 3.11.1 SRP Analysis of P-Well 3.11.2 SRP Analysis of N-Well 3.11.3 SCM Image N-Well and P-Well Separated by DTI 3.11.4 N-Well and P-Well Separated by DTI 3.11.5 SRP Analysis in LDMOS Array 4 Critical Dimensions 5 Report Evaluation 1.2 List of Tables 1.5.1 Device Summary 1.6.1 Summary of Major Findings 2.2.1 Package and Die Dimensions 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Thicknesses 3.4.2 Minimum Pitch Metals 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 LDMOS Transistor Block Critical Parameters 3.8.1 NPN Bipolar Transistor Vertical Dimensions 3.10.1 Isolation Horizontal and Vertical Dimension 3.11.1 Wells and Epi Vertical Dimension 1-3
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