Analysis of Different Topologies of Inverter in 0.18µm CMOS Technology and its Comparision Ashish Panchal (Senior Lecturer) Electronics & Instrumentation Engg. Department, Shri G.S.Institute of Technology and Science, Indore, India Mobile no.:-+919691243624 ashish_panchal@ymail.com Rajkumar Gehlot (Senior Lecturer) School of Electronics Department, Devi Ahillya Vishwa Vidyalaya, Indore, India Mobile no.:-+919893146830 rajkumar.gehlot85@gmail.com Nidhi Maheshwari (Senior Lecturer) Electronics & Instrumentation Engg. Department, Shri G.S.Institute of Technology and Science, Indore, India Mobile no.:-+919039969095 er.nidhi17@ymail.com Prafful Dubey (Lecturer) Electronics & Communication Engg. Department, Laxmi Narayan College of Technology and Science, Indore, India Mobile no.:-+919329516355 praffuldubey@gmail.com Abstract:-In this paper we study inverter topologies under various criteria and caracteristics using Cadence tool. This paper includes analysis of inveter topologies utilized in VLSI that includes CMOS, Pseudo NMOS and Dynamic families. The characteristics include DC transfer characteristics, current Vs voltage characteristics, area and delay. The inverter topologies has been designed in 0.18μm CMOS technology with 1.8V supply voltage. SPECTRA RF simulator is used for circuit simulation. This paper also revels an application specific utility of each topology in accordance to their performance. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8124
Introduction:- VLSI (Very Large Scale Integration) is an upcoming technology that brought us in the world of miniaturization leading to various types of functionality to be incorporated on a single chipset. VLSI first developed in 1950s bringing drastic change in technology. It is the key enabling technology to function in micro and nano domain. Inveter is one of the most basic circuit implemented in VLSI. It finds number of application in amplification, logic inversion, as test circuit for advancements providing it with large acceptance in higher level circuits. The basic inverter circuit consist of a resistor and PDN (Pull Down Network) joined at their drain from where output is taken is shown in figure 1. The circuit have some disadvantages such as area consideration and static power dissipation so this circuit is replaced by Pull-up and Pull-down network. The Pull-up network (PUN) consist of PMOS and Pull-down network (PDN) consist of NMOS as shown in figure 2. The PDN will conduct for all input combination that require low output and will then pull the output node down to ground, the PUN will be OFF. On the other hand, all input combination that call for high output will Figure 1:-Resistive Load Inverter cause the PUN to conduct, and the PUN will then pull the output node up to Vdd, PDN will be OFF. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8125
Figure 2:-Pull-up and Pull-down Network This makes it important to have detailed study of inverter and its characteristics so as to bring avancement to VLSI technology.this paper provides inverter utility for applications involving low power design, driving capability, area constraints etc. In this paper we analyzed various topologies of inverter which includes: CMOS inverter, Pseudo NMOS inverter and Dynamic inverter. The remaining paper is organized as follows. In next section circuit description of inverter topologies is described, after that we introduces simulation results and conclusion. Circuit Description:- 1. CMOS Inverter:-This is basic topology used in VLSI. The CMOS inverter circuit consist of PMOS and NMOS. PMOS acts as pull-up network and NMOS acts as pull-down network. PMOS is connected to Vdd at its source while NMOS source is connected to ground is shown in figure 3. The input is applied on gate-source terminal and output is taken from drain-source terminal. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8126
Figure 3:-Schematic of CMOS Inverter It provide full output voltage swing between 0V to Vdd and the steady-state power dissipation of CMOS inverter is negligible. 2. Pseudo NMOS Inverter:- The large area requirement of CMOS gates presents a problem in high density design. In order to overcome this problem Pseudo inverter is proposed. Pseudo NMOS inverter is the topology that utilizes a constant load i.e., a PMOS transistor that is permanently grounded through its gate terminal is shown in figure 4. PMOS transistor precharges output to high logic so as to reduce delay for high output. Pseudo inverter is also known as ratioed inverter. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8127
Figure 4:-Schematic of Pseudo Inverter This circuit has more power dissipation and current with reduction in delay for high logic. 3. Dynamic Inverter:-Dynamic inverter is an improvement to Pseudo NMOS. In this circuit clock is applied to PMOS and input voltage is applied to NMOS as shown in figure 5. Dynamic circuit operate in two modes: Precharge mode and Evaluation mode. During Precharge mode, clock signal is low. The PMOS transistor is conducting while NMOS transistor is OFF. So, the output capacitance is charged to Vdd. The input voltages are also applied during this mode. During Evaluation mode, clock signal is high. The NMOS transistor is conducting while PMOS transistor is OFF. So, the output capacitance is discharged through ground depending upon the applied inputs. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8128
Figure 5:-Schematic of Dynamic Inverter Its static power dissipation is less than that of Pseudo NMOS inverter but greater than CMOS inverter. It is more complex, and less robust design. Results:- 1) DC Transfer Characteristics:-This is the characteristic drawn for Vout Vs Vin for an inverter. Here we find the variation in output voltage (Vout) depending upon the input voltage (Vin). This can be done graphically, analytically or through simulation. In this paper we used simulation mechanism using Cadence tool. The graphical characterization for various topologies is given below. a) CMOS Inverter:-The graph gives characteristics for output voltage Vs input voltage shown in figure 6. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8129
Figure 6:-DC Transfer Characteristic of CMOS Inverter Table 1:-CMOS Inverter S.No. Vin Vout 1 0 to 0.79V High(1) 2 0.79 to 0.854V Not defined 3 0.854 to 1.8V Low(0) b) Pseudo NMOS Inverter:-The DC transfer characteristic for Pseudo inverter is shown in figure 7. The graph revels that the inverter has high noise and its characteristics is highly deviated from ideal characteristics. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8130
Figure7:-DC Transfer Characteristics of Pseudo NMOS Inverter Table 2:-Pseudo NMOS Inverter S.No. Vin Vout 1 0 to 1.1V High(1) 2 1.1 to 1.6V Not defined 3 1.6 to 1.8V Low(0) c) Dynamic Inverter:- The DC transfer characteristic for Dynamic inverter is shown in figure 8. Its characteristics is better than that of Pseudo inverter. The deviation is reduced by reducing the width of PMOS. Table 3:-Dynamic Inverter S.No. Vin Vout 1 0 to 0.9V High(1) 2 0.9 to 1.6V Not defined 3 1.6 to 1.8V Low(0) ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8131
Figure 8:-DC Transfer Characteristic of Dynamic Inverter 2) Voltage Transfer Characteristics:-This characteristic is drawn between input voltage and output current. Here we analyze the changes in output current corresponding to variation in input voltage. a) CMOS Inverter:-The I-V characteristic of CMOS inverter is shown in figure 9. This graph suitable for low power application and reduces driving capability because of the presence of peak for very little instant time. So its not suitable for switching application. b) Pseudo NMOS Inverter:-The I-V characteristic of Pseudo NMOS inverter is shown in figure 10. This characteristic defines that current is found constant at peak value for input voltage 3Vdd/5 and its power dissipation high, at the same time its driving capability increases. c) Dymamic inverter:-the I-V characteristic of Dynamic inverter is shown in figure 11. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8132
Figure 9:-I-V Characteristic of CMOS Inverter Figure 10:-I-V Characteristic of Pseudo NMOS Inverter ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8133
Figure 11:-I-V Characteristic of Dynamic Inverter 3) Area and Delay Effects:-VLSI targets large circuits on minimum possible area, it targets the circuit area to be as low as possible reliable to have more compact and user friendly. It also targets on the output to be as fast as possible. a) CMOS Inverter:-The CMOS inverter occupy more area because the width of PMOS transistor is larger than thatof NMOS transistor. As the number of inputs increases, the number of transistors also increases two times (2N). But its delay time is much lesser than that of others as shown in figure 12. b) Pseudo NMOS Inverter:-The Pseudo NMOS inverter occupy less area as compare to CMOS inverter because when the number of inputs increases, number of transistors increases by N+1 times. But the delay time of this inverter is large which is shown in figure 13. c) Dynamic inverter:- The Dynamic inverter occupy less area as compare to CMOS inverter but greater than that of Pseudo inverter because the number of inputs increases so the number of transistors also increases by N+2 times. But its delay time is less which is shown in figure 14. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8134
Figure 12:-Delay Characteristic of CMOS Inverter Figure 13:-Delay Characteristic of Pseudo Inverter ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8135
Figure 14:-Delay Characteristic of Dynamic Inverter Table 4:-Comparision of Inverter Topologies S.No. CHARACTERISTICS CMOS INVERTER PSEUDO INVERTER DYNAMIC INVERTER 1 No. of transistors 2 2 2 2 Delay (theoretical) 3RC 3RC 3RC 3 Delay (practically) 17ns 22ns 25ns 4 Area More Less as compare to CMOS inverter Less than CMOS and greater than Pseudo inverter 5 IV-Characteristics Slop is steep Slop is gradual Slop is gradual 6 DC-Characteristics Transition occur at Vdd/2 Transition occur at 7Vdd/10 Transition occur at 7Vdd/10 7 Effect of noise least More than CMOS More than CMOS 8 Use of clock No No Yes CONCLUSION:-The DC transfer characteristics of CMOS inverter are more reliable and performs better for low power design and finds applications in watches, calculator etc. It is ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8136
analyzed that Pseudo and Dynamic inverter acts same except for low current and low power dissipation for dynamic family due to presence of clock. Pseudo inverter having good driving capability but at the same time it consumes more power as compare to dynamic inverter due to high current. REFERENCES:- [1] VLSI Technology by S.M.SZE. [2] CMOS VLSI Design by Neil H.E. Weste. [3] CMOS Digital Integrated Circuits Analysis and Design by Sung-Mo Kang and Yusuf Leblebici. [4] Microelectronic Circuits by Sedra A, Smith K. [5] Introduction to Inverter-Wikipedia. ISSN : 0975-5462 Vol. 3 No. 11 November 2011 8137