ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Introduction to the Long Channel MOSFET Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Electrical and 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu 8-18-2015 MOSFET_L.ppt Page 1
OUTLINE MOSFET s Long Channel vs. Short Channel MOSFET I-V Characteristics MOS Threshold Voltage Design Example References Page 2
NMOS Sub p Gate S MOSFET TRANSISTORS G starting wafer Drain Sub Source D SYMBOL CROSSECTION Gate D G Drain Sub Source n n p p NMOS well well PMOS S PMOS Sub In most MOSFETs the source and drain are symmetrical. The source is the source of carriers (electrons in NMOS, holes in PMOS) and the drain is the drain of carriers. The external circuitry will determine the direction of current flow. Holes flow in the same direction as current, electrons flow in the opposite direction. n Page 3
THE LONG CHANNEL MOSFET Long-channel MOSFET is defined as devices with width and length long enough so that edge effects from the four sides can be neglected Channel length L must be much greater than the sum of the drain and source depletion widths Depletion Channel Depletion L L L Long Channel Device Short Long Tiny Long Channel Page 4
LONG CHANNEL NMOS I-V CHARACTERISTICS +Ids +Id Family of Curves Ids vs Vgs +Vgs +5 +4 +3 +2 +Vds Vsub = 0 Saturation Region Id Vgs=Vds + D G - S Id (Amps) + Vgs - Non Saturation Region Vd = 0.1 Volt D G S Id Vsub Vto -1-2 -3 volts +Vg 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 Vt Sub Vt Slope (mv/dec) Subthreshold Vgs Page 5
LONG CHANNEL THRESHOLD VOLTAGE, VT Xox Flat-band Voltage V FB = ms - Q ss - 1 X (x) dx C C 0 ox ox X ox p-type substrate n-type substrate (n-channel) (p-channel) Q ss = q N ss Bulk Potential : p = -KT/q ln (N A /n i ) n = +KT/q ln (N D /n i ) Work Function: M S = M - ( X + Eg/2q + [ p ]) M S = M - ( X + Eg/2q - [ n ]) Difference *Maximum Depletion Width: 4 s[ p ] 4 s[ n ] of channel qna qnd NMOS Threshold Voltage: VT = V FB + 2 [ p ] + 1 2 s q Na ( 2[ p ]) p-type substrate C ox PMOS Threshold Voltage: VT = V FB - 2 [ n ] - 1 2 s q Nd ( 2[ n ]) n-type substrate C ox Page 6
n+ Poly p+ Poly MAJOR FACTORS AFFECTING VTO Gate work function, n+, p+, aluminum Substrate doping, Nd or Na Oxide thickness, Xox Surface State Density, Nss or Qss +3 +2 Threshold Voltge 650Å +4 +3 n+ poly gate left scale p+ poly gate right scale Nss= 0 Vbs = 0 implant dose = zero Nss is never zero, typically adds 0.5 volts that is shifts both scales up 0.5 volts +1 0-1 -2-3 650Å 250Å 150Å 150Å 250Å +2 +1 0-1 -2 10 14 10 15 10 16 10 17 Substrate doping Page 7
APPROXIMATE EQUATION FOR ID IN NON-SATUATION REGION p n S Q Vg L Vd I D n I D = µw Cox (Vg-Vt-V d /2)V d L Cox = Cox/Area = o r/xox and Area = WL and Xox is gate oxide thickness Estimate I D = charge in transit divided by the transit time charge in transit Q = (Q source end + Q drain end) ave Q = CV = [Cox(Vg-Vs-Vt)+Cox(Vg-Vd-Vt)]/2 Q = Cox(Vg-Vt-Vd/2) = Cox WL(Vg-Vt-Vd/2) Transit time = distance/velocity = L/v = L/µE = L/µ(Vd/L) = L 2 /µvd E is electric field mobility Page 8
NON SATURATION REGION CHARACTERISTICS + Vgs G - +Id S D Id Vto Vsub Vd = 0.1 Volt Vsub = 0-1 -2-3 volts +Vg Body Effect +Ids Non Saturation Region S n G +5 +4 +3 +2 Vsub +Vgs +Vds D nmosfet with Vt=1, since the Drain is at 0.1 volts and the source is at zero. Both drain and source will be on at gate voltages greater than 1.1 volt. the transistor will be in the non saturation region. n p Page 9
APPROXIMATE EQUATION FOR ID IN SATURATION REGION p n S Q Vg L Vd I D n I Dsat = µw Cox (Vg-Vt) 2 2L If Vd increases eventually Vg-Vd will be less than Vt and further increases in Vd will not cause increases in ID (because the additional voltage will be across the gap region at the drain end where it can not reduce the transit time) So substitute Vg-Vd = Vt or Vd = Vg-Vt into equation for non saturation region to get equation for saturation region. Page 10
SATURATION REGION CHARACTERISTICS +Id G S D Id Vto + Vgs=Vds - Vsub Vsub = 0-1 -2-3 volts +Vg NMOS Body Effect +Ids S n Saturation Region +5 G Vsub +4 +Vgs +3 +2 +Vds nmosfet with Vt=1, Drain end is never on because Voltage Gate to Drain is Zero. Therefore this transistor is always in Saturation Region if the gate voltage is above the threshold voltage. D n p Page 11
Ids CALCULATOR FOR IDEAL I-V CHARACTERISTICS ROCHESTER INSTITUTE OF TECHNOLOGY mosfetiv.xls zip/excell/tools/ MICROELECTRONIC ENGINEERING 9/21/99 CALCULATION OF MOSFET I-V CHARACTERISTICS Dr. Lynn Fuller To use this spreadsheet change the values in the white boxes. The rest of the sheet is protected and should not be changed unless you are sure of the consequences. The calculated results are shown in the purple boxes. CONSTANTS VARIABLES CHOICES 1=yes, 0=No T= 300 K Na = 1.00E+16 cm-3 Aluminum gate 0 KT/q = 0.026 volts Nd = 1.00E+15 cm-3 n+ Poly gate 1 Select one type of gate ni = 1.45E+10 cm-3 Nss = 3.00E+10 cm-2 p+ Poly gate 0 Eo = 8.85E-14 F/cm Xox = 1000 Ang N substrate 0 Select one type of substrate Er si = 11.7 P substrate 1 Er SiO2 = 3.9 E affinity = 4.15 volts Carrier Mobility, µ 250 cm2/v-s q = 1.60E-19 coul Eg = 1.124 volts L (length) = 20 µm Gate W (width) = 200.00 µm Source Vg CALCULATIONS: RESULTS Vs METAL WORK FUNCTION = 4.122988528 volts SEMICONDUCTOR POTENTIAL = +/- 0.349542622 volts OXIDE CAPACITANCE / CM2 = 3.4515E-08 F/cm2 METAL SEMI WORK FUNCTION DIFF = -0.938554094 volts FLAT BAND VOLTAGE = -1.077624063 volts THRESHOLD VOLTAGE = 1.01589127 volts L Ids = µ W Cox'/L (Vgs-Vt-Vd/2)Vd in Non Saturation Region Ids = µ W Cox' / 2L (Vgs - Vt)^2 in Saturation Region Drain Vd See: http://www.people.rit.edu/lffeee Vgs 5 7 9 11 Idsat Vds Ids Ids Ids Ids Ids 0 0 0 0 0 0 0.4 0.0001306 0.0002 0.0003 0.000337699 6.9E-06 0.8 0.0002474 0.00039 0.0005 0.000661591 2.8E-05 1.2 0.0003504 0.00056 0.0008 0.000971678 6.2E-05 1.6 0.0004396 0.00072 0.001 0.001267958 0.00011 2 0.000515 0.00086 0.0012 0.001550433 0.00017 2.4 0.0005766 0.00099 0.0014 0.001819101 0.00025 2.8 0.0006243 0.00111 0.0016 0.002073964 0.00034 3.2 0.0006583 0.00121 0.0018 0.00231502 0.00044 3.6 0.0006785 0.0013 0.0019 0.002542271 0.00056 4 0.0006848 0.00138 0.0021 0.002755715 0.00069 4.4 0.0006774 0.00144 0.0022 0.002955354 0.00084 4.8 0.0006561 0.00148 0.0023 0.003141186 0.00099 5.2 0.000621 0.00152 0.0024 0.003313213 0.00117 5.6 0.0005722 0.00154 0.0025 0.003471433 0.00135 6 0.0005095 0.00154 0.0026 0.003615848 0.00155 6.4 0.000433 0.00154 0.0026 0.003746456 0.00177 6.8 0.0003427 0.00152 0.0027 0.003863259 0.00199 7.2 0.0002386 0.00148 0.0027 0.003966255 0.00224 7.6 0.0001207 0.00143 0.0027 0.004055446 0.00249 8-1.097E-05 0.00137 0.0028 0.00413083 0.00276 8.4-0.0001565 0.00129 0.0027 0.004192409 0.00304 8.8-0.0003158 0.0012 0.0027 0.004240181 0.00334 9.2-0.0004889 0.0011 0.0027 0.004274148 0.00365 MOSFET I-V Characteristics 5.00E-03 4.50E-03 4.00E-03 3.50E-03 3.00E-03 2.50E-03 2.00E-03 1.50E-03 1.00E-03 5.00E-04 0.00E+00 0 2 4 6 8 10 Vds Vgs = 5 Vgs = 7 Vgs = 9 Vgs = 11 Idsat Page 12
CHANNEL LENGTH MODULATION Channel length modulation is a description of the effective decrease of the channel length as the voltage on the drain increases causing an increase in the drain-tosubstrate junction reverse bias and an increase in the width of the drain-to-substrate junction space charge layer. This effect begins as soon as the voltage on the drain is greater than zero. As a result it effects both the non-saturation and the saturation region of operation. Resulting in an increase in current in both regions. Professor David Hodges suggested modeling this effect by adding current linearly with voltage drain-to-source using a channel length modulation parameter called lambda adding the term (1+l Vds) to the equations for Ids. NMOS +Ids Channel length modulation causes the current to be higher +5 +4 +Vgs +3 +2 +Vds Page 13
CHANNEL LENGTH MODULATION n Channel Length Modulation Parameter l l = Slope/ Idsat S Vg L - L L Vd2 Vd1 I Dsat = µw Cox (Vg-Vt) 2 (1+ lvds) 2L in saturation region Vd n p Slope +Ids Idsat Vd1 NMOS Saturation Region +5 +4 +Vgs +3 +2 Vd2 +Vds NMOS Transistor in Saturation Region DC Model, l is the channel length modulation parameter and is different for each channel length, L. I D = µw Cox (Vg-Vt-V d /2)V d (1+ lvds) L in non-saturation region Page 14
MEASURED LONG CHANNEL n-mosfet ID-VDS 16/8 L=16µ W=8µ Page 15
MEASURED LONG n-channel MOSFET 16/8 L=16µ W=8µ Page 16
SUMMARY The ideal long channel MOSFET does not really exist. Most MOSFETs will exhibit some short channel behavior such as channel length modulation. However, the equations are easy to work with and to understand and are often used as a starting point for the study of MOSFETs. Similarly SPICE (Simulation Program for Integrated Circuit Engineering) modeling of MOSFETs originated using these long channel equations. The Level 1 model by Shichman and Hodges uses basic device physics equations for MOSFET threshold voltage and drain current in the saturation and non-saturation regions of operation. Mobility is assumed to be a function of total doping concentration only and a parameter called LAMBDA is used to model channel length modulation. Newer models (BSIM-3) do a better job including short channel effects. David A. Hodges hodges@eecs.berkeley.edu Page 17
EXAMPLE PROBLEM Design a transistor that can switch 24 volts in a 200 ohm resistor using a 0 5 Volt gate signal. V VIN R VOUT Page 18
EXAMPLE PROBLEM Lets first check the Drain and source p/n junctions: N+ with Nd = ~1E19 cm-3 Substrate Na =? Find Na and smallest transistor length L Electric Field Breakdown ~ 3E5 V/cm Find at Na = 1E16, Wsc = 1.9µm with Vr = 24 V So L min > 1.9µm + 0.34µm, pick 5µm Page 19
EXAMPLE PROBLEM Lets next find the gate oxide thickness, Xox Use maximum electric field = 4M V/cm Efield = Vmax /Xox = 24 V / Xox = 4M V/cm Xox = 600 E -8 = 600 Å Then calculate the threshold voltage, Vt Vt = -.24 volts So need threshold adjust dose ~ 3.56E11 x 2 to get Vt = 1.0 volts Page 20
EXAMPLE PROBLEM Now lets find transistor width to give the desired current. I = V / R = 24 / 200 = 0.12 Amps use Vgs = 5, Vt=1, L = 5µm, mobility µ = 1250 But divide by 2 to account for surface scattering use µ = 625 I Dsat = µw Cox (Vg-Vt) 2 2L Cox = o r / Xox =4.6E-8 F/cm find: W = 1400µm Page 21
EXAMPLE PROBLEM Finally lets calculate the field threshold voltage. For 10,000Å oxide thickness find Vt= -0.2 volts but need > 24volts so need a channel stop implant to make substrate in field area heavier doped Page 22
FINAL TRANSISTORS Xox = 600 Å N+ Source Gate Drain Metal Xfield = 10,000 Å N+ N+ N+ P type Wafer Na=1E16 Channel Stop B11 2E12 Threshold Adjust B11 3.56e11 Page 23
REFERENCES 1. Microelectronic Circuits, any Edition, Adel Sedra and Kenneth Smith, Oxford University Press, latest edition. 2. Device Electronics for Integrated Circuits, Richard S. Muller, Theodore I. Kamins, John Wiley & Sons., 1977. 3. MOSFET Modeling with SPICE, Daniel Foty, 1997, Prentice Hall, ISBN-0-13-227935-5 4. The MOS Transistor, Yannis Tsividis, 2 nd Edition, McGraw Hill, 1999 Page 24
HOMEWORK INTRO TO MOSFET 1. Calculate the IDS -VDS characteristics for a PMOS transistor for 0<VDS <5 built with the following parameters: substrate doping ND = 1E15 cm-3, Xox = 500 Å, N+ poly gate, Nss = 3E11, W = 32 µm, L = 16 µm 2. Use SPICE to simulate the IDS-VDS characteristics for the PMOS transistor above. Compare SPICE versus hand calculated (Excel). Page 25