N-Channel Power MOSFET 6 V, A, 39 m Features Low R DS(on) High Current Capability % Avalanche Tested These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS ( unless otherwise noted) Parameter Symbol Value Unit Drain to Source Voltage V DSS 6 V Gate to Source Voltage Continuous V GS ± V Gate to Source Voltage Non Repetitive (t p < s) Continuous Drain Current (R JC ) Power Dissipation (R JC ) Steady State V GS ±3 V T C = C I D A T C = C 13 T C = C P D 36 W Pulsed Drain Current t p = s I DM 76 A Operating Junction and Storage Temperature T J, T stg to 1 Source Current (Body Diode) I S A Single Pulse Drain to Source Avalanche Energy (V DD = V, V GS = V, R G =, I L(pk) = 19 A, L =.1 mh, ) Lead Temperature for Soldering Purposes (1/8 from case for s) C E AS 18 mj T L 6 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. THERMAL RESISTANCE MAXIMUM RATINGS Parameter Symbol Value Unit Junction to Case (Drain) R JC 3. C/W Junction to Ambient Steady State (Note 1) R JA 1. Surface mounted on FR board using 1 in sq pad size (Cu area = 1.17 in sq [ oz] including traces. V (BR)DSS 6 V G 1 3 DPAK CASE 369AA (Surface Mount) STYLE R DS(on) MAX 39 m @ V m @. V MARKING DIAGRAMS & PIN ASSIGNMENT Drain Drain AYWW 8 67NLG 1 Drain 3 Gate Source D S I D MAX N Channel 1 3 IPAK CASE 369D (Straight Lead) STYLE AYWW 8 67NLG A 18 A 1 3 Gate Drain Source A = Assembly Location* Y = Year WW = Work Week 867NL = Device Code G = Pb Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information on page of this data sheet. Semiconductor Components Industries, LLC, 1 September, 1 Rev. 3 1 Publication Order Number: NTD867NL/D
Input Capacitance C iss ELECTRICAL CHARACTERISTICS ( unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = A 6 V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J 6 mv/ C Zero Gate Voltage Drain Current I DSS VGS = V, 1. A V DS = 6 V T J = 1 C Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ± na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A 1. 1.8. V Negative Threshold Temperature Coefficient V GS(TH) /T J. mv/ C Drain to Source On Resistance R DS(on) V GS = V, I D = A 6 39 m V GS =. V, I D = A 33 Forward Transconductance g FS V DS = 1 V, I D = A 8. S CHARGES, CAPACITANCES AND GATE RESISTANCES 67 pf Output Capacitance C oss V GS = V, f = 1. MHz, V DS = V 68 Reverse Transfer Capacitance C rss 7 Total Gate Charge Q G(TOT) 1 nc Threshold Gate Charge Q G(TH) V GS = V, V DS = 8 V, 1. Gate to Source Charge Q GS. Gate to Drain Charge Q GD.3 Total Gate Charge Q G(TOT) V GS =. V, V DS = 8 V, 7.6 nc Gate Resistance R G 1.3 SWITCHING CHARACTERISTICS (Note 3) Turn On Delay Time t d(on) 6. ns Rise Time t r V GS = V, V DD = 8 V, 1.6 Turn Off Delay Time t d(off), R G =. 18. Fall Time t f. DRAIN SOURCE DIODE CHARACTERISTICS Forward Diode Voltage V SD VGS = V, I S = A.87 1. V T J = C.78 Reverse Recovery Time t RR 17 ns Charge Time ta V GS = V, dis/dt = A/ s, 13 Discharge Time tb I S = A. Reverse Recovery Charge Q RR 1 nc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.. Pulse Test: Pulse Width 3 s, Duty Cycle %. 3. Switching characteristics are independent of operating junction temperatures.
TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ) 3 V V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 1. On Region Characteristics V GS, GATE TO SOURCE VOLTAGE (VOLTS) V Figure 3. On Resistance vs. Gate to Source Voltage R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I D, DRAIN CURRENT (AMPS) V DS V 3 3 3.8 V 3.6 V 3. V 1 1 T J = 1 C 3. V 3. V.8 V T J = C 1 3 3.6...3. V. 3 6 7 8 9 3..3.3.. V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. Transfer Characteristics V GS =. V V GS = V 1 I D, DRAIN CURRENT (AMPS) Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED).. 1.8 1.6 1. 1. 1..8 V GS = V.6 7 1 1 T J, JUNCTION TEMPERATURE ( C) Figure. On Resistance Variation with Temperature I DSS, LEAKAGE (na) V GS = V T J = 1 C T J = 1 C 3 6 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 6. Drain to Source Leakage Current vs. Drain Voltage 3
TYPICAL PERFORMANCE CURVES C, CAPACITANCE (pf) V GS = V 9 8 7 C iss 6 3 C oss C rss 3 6 DRAIN TO SOURCE VOLTAGE (VOLTS) V GS, GATE TO SOURCE VOLTAGE (VOLTS) 8 6 Q gs Q gd Q T Q G, TOTAL GATE CHARGE (nc) VGS V DS = 8 V 1 Figure 7. Capacitance Variation Figure 8. Gate To Source Voltage vs. Total Charge t, TIME (ns) V DD = 8 V V GS = V t f t d(off) t r t d(on), SOURCE CURRENT (AMPS) 1 V GS = V IS 1 1 R G, GATE RESISTANCE (OHMS)..6.7.8.9 V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) 1. Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure. Diode Forward Voltage vs. Current ID, DRAIN CURRENT (AMPS) 1 V GS = V SINGLE PULSE T C = C s s 1 ms ms dc EAS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) R DS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT.1 1 7 1 1 V DS, DRAIN TO SOURCE VOLTAGE (VOLTS) T J, JUNCTION TEMPERATURE ( C) 1 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 1. Maximum Avalanche Energy vs. Starting Junction Temperature
TYPICAL PERFORMANCE CURVES r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1..1..1...1.1 D =..1 SINGLE PULSE.1 P (pk).1 t, TIME (s) Figure 13. Thermal Response t 1 t R JC (t) = r(t) R JC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t 1 T J(pk) T C = P (pk) R JC (t).1.1.1 DUTY CYCLE, D = t 1 /t ORDERING INFORMATION NTD867NL 1G Order Number Package Shipping IPAK (Straight Lead) (Pb Free) 7 Units / Rail NTD867NLTG DPAK (Pb Free) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD811/D.
PACKAGE DIMENSIONS L3 L b e E b3 1 3 b A D B DETAIL A c. (.13) M C A DPAK (SINGLE GUAGE) CASE 369AA ISSUE B C c H L GAUGE PLANE L L1 DETAIL A ROTATED 9 CW SOLDERING FOOTPRINT* 6.. A1.8.1 H C 3..118 Z SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.M, 199.. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z.. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED.6 INCHES PER SIDE.. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. INCHES MILLIMETERS DIM MIN MAX MIN MAX A.86.9.18.38 A1....13 b..3.63.89 b.3..76 1.1 b3.18.1.7.6 c.18..6.61 c.18..6.61 D.3..97 6. E..6 6.3 6.73 e.9 BSC.9 BSC H.37. 9..1 L..7 1. 1.78 L1.8 REF.7 REF L. BSC.1 BSC L3.3..89 1.7 L. 1.1 Z.1 3.93 STYLE : PIN 1. GATE. DRAIN 3. SOURCE. DRAIN.8.8 1.6.63 6.17.3 SCALE 3:1 mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
PACKAGE DIMENSIONS IPAK (STRAIGHT LEAD DPAK) CASE 369D ISSUE C V B R C E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y1.M, 198.. CONTROLLING DIMENSION: INCH. S T SEATING PLANE F 1 3 G A K D 3 PL J.13 (.) M T H Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A.3..97 6.3 B..6 6.3 6.73 C.86.9.19.38 D.7.3.69.88 E.18.3.6.8 F.37..9 1.1 G.9 BSC.9 BSC H.3..87 1.1 J.18.3.6.8 K.3.38 8.89 9.6 R.18.1.. S...63 1.1 V.3..89 1.7 Z.1 3.93 STYLE : PIN 1. GATE. DRAIN 3. SOURCE. DRAIN ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 163, Denver, Colorado 817 USA Phone: 33 67 17 or 8 3 386 Toll Free USA/Canada Fax: 33 67 176 or 8 3 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 8 8 98 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 1 33 79 9 Japan Customer Focus Center Phone: 81 3 817 7 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD867NL/D