Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) FEATURE Industrial range available ( 40 C to +85 C) Multifunction capability Non-inverting data path 3-tate outputs ee 74F258A for inverting version DECRIPTION The has four identical 2-input multiplexers with 3-tate outputs which select 4 bits of data from two sources uncer control of a common elect () input. The I0a inputs are selected when the common elect input is Low and the In inputs are selected when the common elect input is High. Data appears at the outputs in true non-inverted form from the selected inputs. The is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the common lect input. Outputs are forced to a high impedance off state when the Output Enable () is High. All but one device must be in high impedance state to avoid currents that would exceed the maximum rating if the outputs were tied together. Design of the Output Enable signals must eure that there is no overlap when outputs of 3-state devices were tied together. PIN CONFIGURATION TYPE I0a Ia Ya I0b Ib Yb GND 2 3 4 5 6 7 8 TYPICAL PROPAGATION DELAY 6 5 4 3 2 0 9 V CC I0d Id Yd I0c Ic Yc F00673 TYPICAL UPPLY CURRENT (TOTAL) 4.3 2mA ORDERING INFORMATION DECRIPTION COMMERCIAL RANGE V CC = 5V ±0%, T amb = 0 C to +70 C ORDER CODE INDUTRIAL RANGE V CC = 5V ±0%, T amb = 40 C to +85 C DRAWING NUMBER 6-pin plastic DIP NN IN OT38-4 6-pin plastic O ND ID OT09- INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PIN DECRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I0n, In Data inputs.0/.0 20µA/0.6mA Common elect input.0/.0 20µA/0.6mA Output Enable input (active Low).0/.0 20µA/0.6mA Ya Yd Data outputs 50/33 ma/20ma NOTE: One (.0) FAT unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC YMBOL LOGIC YMBOL (IEEE/IEC) 2 3 5 6 0 4 3 5 EN G 5 I0a Ia I0b Ib I0c Ic I0d Id 2 3 5 6 MUX 4 7 0 9 V CC = Pin 6 GND = Pin 8 4 7 9 2 F00674 3 4 2 F00675 995 Mar 3 853 0360 5059
Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) LOGIC DIAGRAM I0a Ia I0b Ib I0c Ic I0d Id 5 2 3 5 6 0 4 3 FUNCTION TABLE INPUT OUTPUT I0 I Y H X X X Z L H X L L L H X H H L L L X L L L H X H H = High voltage level L = Low voltage level X = Don t care Z = High impedance off state 4 7 9 2 V CC = Pin 6 GND = Pin 8 F00676 APPLICATION 2 ENABLE C B A 74F39 Y0 Y Y2 Y3 0 WORD A WORD B WORD C WORD D WORD E WORD F WORD G WORD H I0a Ia I0b Ib I0c Ic I0d Id I0a Ia I0b Ib I0c Ic I0d Id I0a Ia I0b Ib I0c Ic I0d Id I0a Ia I0b Ib I0c Ic I0d Id 4-BIT DATA BU F00677 995 Mar 3 2
Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) ABOLUTE MAXIMUM RATING (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) YMBOL PARAMETER RATING V CC upply voltage 0.5 to + V V IN Input voltage 0.5 to + V I IN Input current 30 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 48 ma T amb Operating free-air temperature range Commercial range 0 to +70 C Industrial range 40 to +85 C T stg torage temperature range 65 to +50 C RECOMMENDED OPERATING CONDITION YMBOL PARAMETER LIMIT MIN NOM MAX V CC upply voltage V V IH High-level input voltage V V IL Low-level input voltage 0.8 V I IK Input clamp current 8 ma I OH High-level output current 3 ma I OL Low-level output current 24 ma T amb Operating free-air temperature range Commercial range 0 +70 C Industrial range 40 +85 C 995 Mar 3 3
Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) DC ELECTRICAL CHARACTERITIC (Over recommended operating free-air temperature range unless otherwise noted.) YMBOL PARAMETER TET CONDITION MIN TYP 2 MAX LIMIT V OH High-level output voltage V CC = MIN, V IL = MAX, ±0%V CC 2.4 V V IH = MIN, I OH = MAX ±5%V CC 2.7 3.3 V V OL Low-level output voltage V CC = MIN, V IL = MAX, ±0%V CC 0.35 0.50 V V IH = MIN, I OL = MAX ±5%V CC 0.35 0.50 V V IK Input clamp voltage V CC = MIN, I I = I IK 0.73.2 V I I Input current at maximum input voltage V CC = MAX, V I = V 00 µa I IH High-level input current V CC = MAX, V I = 2.7V 20 µa I IL Low-level input current V CC = MAX, V I = 0.5V 0.6 ma I OZH I OZL Off state output current, High-level voltage applied Off state output current, Low-level voltage applied V CC = MAX, V O = 2.7V 50 µa V CC = MAX, V O = 0.5V 50 µa I O hort-circuit output current 3 V CC = MAX -60 50 ma I CCH 9.0 ma I CC upply current 4 (total) I CCL V CC = MAX 2 ma I CCZ 2 ma NOTE:. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I O, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I O tests should be performed last. 4. Measure I CC with all outputs open and inputs grounded. AC ELECTRICAL CHARACTERITIC YMBOL t PZH t PHZ PARAMETER Propagation delay In to Propagation delay to Output Enable time to High or Low level Output Disable time from High or Low level TET CONDITION Waveform Waveform Waveform 2 Waveform 3 Waveform 2 Waveform 3 T amb = +25 C V CC = +V LIMIT T amb = 0 C to +70 C V CC = +V ± 0% T amb = 40 C to +85 C V CC = +V ± 0% MIN TYP MAX MIN MAX MIN MAX 3.5 6.5 3.5 9.5 0.5 8.0 0.5 995 Mar 3 4
Philips emiconductors Quad 2-line to -line selector/multiplexer, non-inverting (3-tate) AC WAVEFORM For all waveforms, =.5V. In or Waveform. F00679 Propagation Delay, Data and elect to Output t PZH t PHZ V OH 0.3V V OL +0.3V F0023 Waveform 2. 3-tate Output Enable Time to High Level and Output Disable Time from High Level F0024 Waveform 3. 3-tate Output Enable Time to Low Level and Output Disable Time from Low Level TET CIRCUIT AND WAVEFORM PULE GENERATOR V IN V CC D.U.T. V OUT R L V NEGATIVE PULE 0% t THL ( t f ) t w t TLH ( t r ) 0% AMP (V) R T C L R L Test Circuit for 3-tate Outputs WITCH POITION TET WITCH closed closed All other open POITIVE PULE 0% t TLH ( t r ) t THL ( t f ) t w Input Pulse Definition 0% AMP (V) DEFINITION: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F INPUT PULE REQUIREMENT amplitude rep. rate t w t TLH t THL V.5V MHz 500 2.5 2.5 F00678 995 Mar 3 5