54ABT Bit Transparent Latch with TRI-STATE Outputs
|
|
- Jason Cain
- 6 years ago
- Views:
Transcription
1 54ABT Bit Transparent Latch with TRI-STATE Outputs General Description The ABT16373 contains sixteen non-inverting latches with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. Ordering Code: Features n Separate control logic for each byte n 16-bit version of the ABT373 n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcircuit Drawing (SMD) Military Package Package Description Number 54ABT16373W-QML WA48A 48-Lead Cerpack Logic Symbol Pin Description Pin Names OE n LE n D 0 D 15 O 0 O 15 Description Output Enable Input (Active Low) Latch Enable Input Data Inputs Outputs DS Connection Diagram Pin Assignment for Cerpack July ABT Bit Transparent Latch with TRI-STATE Outputs DS TRI-STATE is a registered trademark of Corporation Corporation DS
2 Functional Description The ABT16373 contains sixteen D-type latches with TRI-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LE n ) input is HIGH, data on the D n enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LE n is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE n. The TRI-STATE standard outputs are controlled by the Output Enable (OE n ) input. When OE n is LOW, the standard outputs are in the 2-state mode. When OE n is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagrams Truth Tables Inputs Outputs LE 1 OE 1 D 0 D 7 O 0 O 7 X H X Z H L L L H L H H L L X (Previous) Inputs Outputs LE 2 OE 2 D 8 D 15 O 8 O 15 X H X Z H L L L H L H H L L X (Previous) H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH to LOW transition of LE DS DS
3 Absolute Maximum Ratings (Note 1) Storage Temperature 65 C to +150 C Ambient Temperature under Bias 55 C to +125 C Junction Temperature under Bias Ceramic 55 C to +175 C V CC Pin Potential to Ground Pin 0.5V to +7.0V Input Voltage (Note 2) 0.5V to +7.0V Input Current (Note 2) 30 ma to +5.0 ma Voltage Applied to Any Output in the Disabled or Power-Off State 0.5V to +5.5V in the HIGH State 0.5V to V CC Current Applied to Output in LOW State (Max) twice the rated I OL (ma) DC Latchup Source Current: OE Pin 350 ma (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) Recommended Operating Conditions 500 ma 10V Free Air Ambient Temperature Military 55 C to +125 C Supply Voltage Military +4.5V to +5.5V Minimum Input Edge Rate ( V/ t) Data Input 50 mv/ns Enable Input 20 mv/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT16373 Units V CC Conditions Min Typ Max V IH Input HIGH Voltage 2.0 V Recognized HIGH Signal V IL Input LOW Voltage 0.8 V Recognized LOW Signal V CD Input Clamp Diode Voltage 1.2 V Min I IN = 18 ma V OH Output HIGH Voltage 54ABT 2.5 I OH = 3 ma 54ABT 2.0 I OH = 24 ma V OL Output LOW Voltage 54ABT 0.55 V Min I OL = 48 ma I IH Input HIGH Current 5 µa Max V IN = 2.7V (Note 4) 5 V IN = V CC I BVI Input HIGH Current Breakdown Test 7 µa Max V IN = 7.0V I IL Input LOW Current 5 µa Max V IN = 0.5V (Note 4) 5 V IN = 0.0V V ID Input Leakage Test 4.75 V 0.0 I ID = 1.9 µa All Other Pins Grounded I OZH Output Leakage Current 50 µa 0 5.5V V OUT = 2.7V; OE = 2.0V I OZL Output Leakage Current 50 µa 0 5.5V V OUT = 0.5V; OE = 2.0V I OS Output Short-Circuit Current ma Max V OUT = 0.0V I CEX Output High Leakage Current 50 µa Max V OUT = V CC I ZZ Bus Drainage Test 100 µa 0.0 V OUT = 5.5V; All Others GND I CCH Power Supply Current 2.0 ma Max All Outputs HIGH I CCL Power Supply Current 85 ma Max All Outputs LOW I CCZ Power Supply Current 2.0 ma Max OE = V CC All Others at V CC or GND I CCT Additional I CC /Input Outputs Enabled 2.5 ma V I = V CC 2.1V Outputs TRI-STATE 2.5 ma Max Enable Input V I = V CC 2.1V Outputs TRI-STATE 2.5 ma Data Input V I = V CC 2.1V All Others at V CC or GND I CCD Dynamic I CC No Load ma/ Max Outputs Open, LE = V CC (Note 4) 0.15 MHz OE = GND, (Note 3) Note 3: For 8 bits toggling, I CCD < 0.8 ma/mhz. Note 4: Guaranteed, but not tested. One Bit Toggling, 50% Duty Cycle 3
4 AC Electrical Characteristics Symbol Parameter 54ABT Units T A = 55 C to +125 C V CC = 4.5V to 5.5V C L = 50 pf Min Max t PLH Propagation Delay ns t PHL D n to O n t PLH Propagation Delay ns t PHL LE to O n t PZH Output Enable Time ns t PZL t PHZ Output Disable Time ns t PLZ AC Operating Requirements Symbol Parameter 54ABT Units T A = 55 C to +125 C V CC = 4.5V to 5.5V C L = 50 pf Min Max t s (H) Setup Time, HIGH 2.4 ns t s (L) or LOW D n to LE 2.4 t h (H) Hold Time, HIGH 2.2 ns t h (L) or LOW D n to LE 2.2 t w (H) Pulse Width, 3.3 ns LE HIGH Capacitance Symbol Parameter Typ Units Conditions (T A = 25 C) C IN Input Capacitance 5 pf V CC = 0V C OUT (Note 5) Output Capacitance 11 pf V CC = 5.0V Note 5: C OUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method
5 AC Loading DS *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS FIGURE 2. Test Input Signal Levels DS FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times DS Amplitude Rep. Rate t w t r t f 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS
6 54ABT Bit Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Corporation Americas Tel: Fax: support@nsc.com Europe Fax: +49 (0) europe.support@nsc.com Deutsch Tel: +49 (0) English Tel: +49 (0) Français Tel: +49 (0) Italiano Tel: +49 (0) Asia Pacific Customer Response Group Tel: Fax: sea.support@nsc.com Japan Ltd. Tel: Fax: National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
74ABT Bit Transparent D-Type Latch with 3-STATE Outputs
March 1994 Revised November 1999 74ABT16373 16-Bit Traparent D-Type Latch with 3-STATE Outputs General Description The ABT16373 contai sixteen non-inverting latches with 3-STATE outputs and is intended
74ABT273 Octal D-Type Flip-Flop
Octal D-Type Flip-Flop General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load
54FCT240 Octal Buffer/Line Driver with TRI-STATE Outputs
54FCT240 Octal Buffer/Line Driver with TRI-STATE Outputs General Description The 54FCT240 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented
74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs
Octal Buffer/Line Driver with 3-STATE Outputs General Description The ABT244 is an octal buffer and line driver with 3-STATE outputs designed to be employed as a memory and address driver, clock driver,
74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs
September 1991 Revised November 1999 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs General Description The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs
74ABT Bit Registered Transceiver with 3-STATE Outputs
November 1993 Revised August 2001 16-Bit Registered Traceiver with 3-STATE Outputs General Description The ABT16952 is a 16-bit registered traceiver. Two 8-bit back to back registers store data flowing
74F794 8-Bit Register with Readback
74F794 8-Bit Register with Readback General Description The F794 is an 8-bit register with readback capability designed to store data as well as read the register information back onto the data bus. The
74ABT373 Octal Transparent Latch with 3-STATE Outputs
Octal Traparent Latch with 3-STATE Outputs General Description The ABT373 coists of eight latches with 3-STATE outputs for bus organized system applicatio. The flip-flops appear traparent to the data when
74ABT Bit Transceiver with 3-STATE Outputs
74ABT16245 16-Bit Traceiver with 3-STATE Outputs General Description The ABT16245 contai sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applicatio. The
74ABT377 Octal D-Type Flip-Flop with Clock Enable
Octal D-Type Flip-Flop with Clock Enable General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all
74F573 Octal D-Type Latch with 3-STATE Outputs
74F573 Octal D-Type Latch with 3-STATE Outputs General Description The F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. This device
74FR Bit Bidirectional Transceiver with 3-STATE Outputs
74FR9245 9-Bit Bidirectional Transceiver with 3-STATE Outputs General Description The FR9245 contains nine non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus-oriented applications.
74F2245 Octal Bidirectional Transceiver with TRI-STATE Outputs
November 1996 2245 Octal Bidirectional Transceiver with TRI-STATE Outputs General Description The F2245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented
74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker
74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker General Description The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
Low Power Octal ECL/TTL Bi-Directional Translator with Latch
100328 Low Power Octal ECL/TTL Bi-Directional Translator with Latch General Description The 100328 is an octal latched bi-directional translator designed to convert TTL logic levels to 100K ECL logic levels
74F540 74F541 Octal Buffer/Line Driver with 3-STATE Outputs
74F540 74F541 Octal Buffer/Line Driver with 3-STATE Outputs General Description The F540 and F541 are similar in function to the F240 and F244 respectively, except that the inputs and outputs are on opposite
74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
April 1992 Revised November 1999 74ABT646 Octal Traceivers and Registers with 3-STATE Outputs General Description The ABT646 coists of bus traceiver circuits with 3- STATE, D-type flip-flops, and control
54AC00 54ACT00 Quad 2-Input NAND Gate
54AC00 54ACT00 Quad 2-Input NAND Gate General Description The AC/ ACT00 contains four 2-input NAND gates. Features n I CC reduced by 50% Logic Symbol IEEE/IEC n Outputs source/sink 24 ma n ACT00 has TTL-compatible
74F373 Octal Transparent Latch with 3-STATE Outputs
74F373 Octal Traparent Latch with 3-STATE Outputs General Description The 74F373 coists of eight latches with 3-STATE outputs for bus organized system applicatio. The flip-flops appear traparent to the
SCAN182373A Transparent Latch with 25Ω Series Resistor Outputs
January 1993 Revised August 2000 SCAN182373A Traparent Latch with 25Ω Series Resistor Outputs General Description The SCAN182373A is a high performance BiCMOS traparent latch featuring separate data inputs
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver
DS26C31T/DS26C31M CMOS Quad TRI-STATE Differential Line Driver General Description The DS26C31 is a quad differential line driver designed for digital data transmission over balanced lines. The DS26C31T
54F/74F04 Hex Inverter
54F/74F04 Hex Inverter General Description This device contains six independent gates, each of which performs the logic INVERT function. Ordering Code: See Section 0 Features n Guaranteed 4000V minimum
54AC191 Up/Down Counter with Preset and Ripple Clock
54AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature
SCAN16512 Low Voltage Universal 16-bit IEEE Bus Transceiver with TRI-STATE Outputs
SCAN16512 Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver with TRI-STATE Outputs General Description The SCAN16512 is a high speed, low-power universal bus transceiver featuring data inputs organized
74F827 74F Bit Buffers/Line Drivers
10-Bit Buffers/Line Drivers General Description The and 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have
74F540 74F541 Octal Buffer/Line Driver with 3-STATE Outputs
Octal Buffer/Line Driver with 3-STATE Outputs General Description The 74F540 and 74F541 are similar in function to the 74F240 and 74F244 respectively, except that the inputs and outputs are on opposite
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers
DS96172/DS96174 RS-485/RS-422 Quad Differential Line Drivers General Description The DS96172 and DS96174 are high speed quad differential line drivers designed to meet EIA Standard RS-485. The devices
DS3486 Quad RS-422, RS-423 Line Receiver
DS3486 Quad RS-422, RS-423 Line Receiver General Description National s quad RS-422, RS-423 receiver features four independent receivers which comply with EIA Standards for the electrical characteristics
DS3695/DS3695T/DS3696/DS3697 Multipoint RS485/RS422 Transceivers/Repeaters
DS3695/DS3695T/DS3696/DS3697 Multipoint RS485/RS422 Transceivers/Repeaters General Description The DS3695, DS3696, and DS3697 are high speed differential TRI-STATE bus/line transceivers/repeaters designed
SCAN16512A Low Voltage Universal 16-bit IEEE Bus Transceiver with TRI-STATE Outputs
Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver with TRI-STATE Outputs General Description The SCAN16512A is a high speed, low-power universal bus transceiver featuring data inputs organized into
74F00 Quad 2-Input NAND Gate
74F00 Quad 2-Input NAND Gate General Description This device contains four independent gates, each of which performs the logic NAND function. Ordering Code: Features n Guaranteed 4000V minimum ESD protection
74LVT LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs
74LVT16374 74LVTH16374 Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs General Description The LVT16374 and LVTH16374 contain sixteen non-inverting D-type flip-flops with 3-STATE outputs and is
54AC08 Quad 2-Input AND Gate
08 Quad 2-Input AND Gate General Description The AC08 contains four, 2-input AND gates. Features n I CC reduced by 50% n Outputs source/sink 24 ma Logic Symbol IEEE/IEC July 2003 n Standard Microcircuit
DS75451/2/3 Series Dual Peripheral Drivers
DS75451/2/3 Series Dual Peripheral Drivers General Description The DS7545X series of dual peripheral drivers is a family of versatile devices designed for use in systems that use TTL logic. Typical applications
DS1488 Quad Line Driver
DS1488 Quad Line Driver General Description The DS1488 is a quad line driver which converts standard TTL input logic levels through one stage of inversion to output levels which meet EIA Standard RS-232D
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS34C87T CMOS Quad TRI-STATE Differential Line Driver General Description
74ABT126 Quad Buffer with 3-STATE Outputs
74ABT126 Quad Buffer with 3-STATE Outputs Features Non-inverting buffers Output sink capability of 64mA, source capability of 32mA Guaranteed latchup protection High impedance glitch free bus loading during
74F14 Hex Inverter Schmitt Trigger
74F14 Hex Inverter Schmitt Trigger General Description The F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming
DM74ALS652/74ALS652-1 Octal 3-STATE Bus Transceiver and Register
DM74LS652/74LS652-1 Octal 3-STTE us Transceiver and Register General Description Connection Diagram March 1998 This device incorporates an octal transceiver and an octal D-type register configured to enable
74LVT LVTH16373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs
74LVT16373 74LVTH16373 Low Voltage 16-Bit Traparent Latch with 3-STATE Outputs General Description The LVT16373 and LVTH16373 contain sixteen non-inverting latches with 3-STATE outputs and is intended
DS16F95, DS36F95 EIA-485/EIA-422A Differential Bus Transceiver
DS16F95, DS36F95 EIA-485/EIA-422A Differential Bus Transceiver General Description The DS16F95/DS36F95 Differential Bus Transceiver is a monolithic integrated circuit designed for bidirectional data communication
DS7830/DS8830 Dual Differential Line Driver
DS7830/DS8830 Dual Differential Line Driver General Description The DS7830/DS8830 is a dual differential line driver that also performs the dual four-input NAND or dual four-input AND function. TTL (Transistor-Transistor-Logic)
DS90C031 LVDS Quad CMOS Differential Line Driver
DS90C031 LVDS Quad CMOS Differential Line Driver General Description The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates.
DS3486 Quad RS-422, RS-423 Line Receiver
Quad RS-422, RS-423 Line Receiver General Description National s quad RS-422, RS-423 receiver features four independent receivers which comply with EIA Standards for the electrical characteristics of balanced/unbalanced
DM74ALS373 Octal D-Type TRI-STATE Transparent Latch
DM74ALS373 Octal D-Type TRI-STATE Transparent Latch General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance
74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The ALVC16500 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops
DS7833 DS8833 DS7835 DS8835 Quad TRI-STATE Bus Transceivers
DS7833 DS8833 DS7835 DS8835 Quad TRI-STATE Bus Transceivers General Description This family of TRI-STATE bus transceivers offers extreme versatility in bus organized data transmission systems The data
DS3662 Quad High Speed Trapezoidal Bus Transceiver
DS3662 Quad High Speed Trapezoidal Bus Transceiver General Description The DS3662 is a quad high speed Schottky bus transceiver intended for use with terminated 120Ω impedance lines. It is specifically
LMS75LBC176 Differential Bus Transceivers
LMS75LBC176 Differential Bus Transceivers General Description The LMS75LBC176 is a differential bus/line transceiver designed for bidirectional data communication on multipoint bus transmission lines.
74ALVC Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in A Port Outputs
74ALVC162245 Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in A Port Outputs General Description The ALVC162245 contains sixteen non-inverting
P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic
P54FCT373T/74fct373T OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.6ns max (MIL) Reduced VOH (typically = 3.3 V)
74LVT245 74LVTH245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
74LVT245 74LVTH245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs General Description The LVT245 and LVTH245 contain eight non-inverting bidirectional buffers with 3-STATE outputs
DM74LS75 Quad Latches
DM74LS75 uad Latches General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present
DS36C279 Low Power EIA-RS-485 Transceiver with Sleep Mode
DS36C279 Low Power EIA-RS-485 Transceiver with Sleep Mode General Description The DS36C279 is a low power differential bus/line transceiver designed to meet the requirements of RS-485 Standard for multipoint
DS36950 Quad Differential Bus Transceiver
DS36950 Quad Differential Bus Transceiver General Description The DS36950 is a low power, space-saving quad EIA-485 differential bus transceiver especially suited for high speed, parallel, multipoint,
74F157A Quad 2-Input Multiplexer
74F157A Quad 2-Input Multiplexer General Description The F157A is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The
P54FCT373/74fct373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic
P54FCT373/74fct373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.6ns max (MIL) Output levels compatible with TTL
DS485 Low Power RS-485/RS-422 Multipoint Transceiver
DS485 Low Power RS-485/RS-422 Multipoint Transceiver General Description The DS485 is a low-power transceiver for RS-485 and RS-422 communication. The device contains one driver and one receiver. The drivers
DS7830 Dual Differential Line Driver
DS7830 Dual Differential Line Driver General Description The DS7830 is a dual differential line driver that also performs the dual four-input NAND or dual four-input AND function. TTL (Transistor-Transistor-Logic)
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS26LV31T 3V Enhanced CMOS Quad Differential Line Driver General Description
FSTU32160A 16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch with 2V Undershoot Protection
June 1999 Revised December 2000 FSTU32160A 16-Bit to 32-Bit Multiplexer/Demultiplexer Bus Switch with 2V Undershoot Protection General Description The Fairchild Switch FSTU32160A is a 16-bit to 32-bit
74ABT573 Octal D-Type Latch with 3-STATE Outputs
74ABT573 Octal D-Type Latch with 3-STATE Outputs Features Inputs and outputs on opposite sides of package allow easy interface with microprocessors Useful as input or output port for microprocessors Functionally
DS90C032 LVDS Quad CMOS Differential Line Receiver
DS90C032 LVDS Quad CMOS Differential Line Receiver General Description TheDS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data
74F32 Quad 2-Input OR Gate
74F32 Quad 2-Input OR Gate General Description This device contains four independent gates, each of which performs the logic OR function. Ordering Code: April 1988 Revised August 2000 74F32 Quad 2-Input
DS14185 EIA/TIA Driver x 5 Receiver
DS14185 EIA/TIA-232 General Description 3 Driver x 5 Receiver The DS14185 is a three driver, five receiver device which conforms to the EIA/TIA-232-E standard. The flow-through pinout facilitates simple
54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers
54LS125A DM54LS125A DM74LS125A Quad TRI-STATE Buffers General Description This device contains four independent gates each of which performs a non-inverting buffer function The outputs have the TRI-STATE
74F132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description Ordering Code: April 1988 Revised September 2000 The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard
Low Power Quint AND/NAND Gate
100304 Low Power Quint AND/NAND Gate General Description The 100304 is monolithic quint AND/NAND gate. The Function output is the wire-nor of all five AND gate outputs. All inputs have 50 kω pull-down
DS90C032B LVDS Quad CMOS Differential Line Receiver
LVDS Quad CMOS Differential Line Receiver General Description TheDS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
74ACTQ821 Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs
Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs General Description The ACTQ821 is a 10-bit D-type flip-flop with non-inverting 3-STATE outputs arranged in a broadside pinout. The ACTQ821 utilizes
74F139 Dual 1-of-4 Decoder/Demultiplexer
Dual 1-of-4 Decoder/Demultiplexer General Description The F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four
FST Bit Low Power Bus Switch
2-Bit Low Power Bus Switch General Description The FST3306 is a 2-bit ultra high-speed CMOS FET bus switch with TTL-compatible active LOW control inputs. The low on resistance of the switch allows inputs
74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs
74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs Features Non-inverting buffers Output sink capability of 64mA, source capability of 32mA Guaranteed output skew Guaranteed multiple output switching
DS9637A Dual Differential Line Receiver
Dual Differential Line Receiver General Description The DS9637A is a Schottky dual differential line receiver which has been specifically designed to satisfy the requirements of EIA Standards RS-422 and
DS8922/DS8922A/DS8923A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pairs
DS8922/DS8922A/DS8923A TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pairs General Description The DS8922/22A and DS8923A are Dual Differential Line Driver and Receiver pairs. These devices
74F583 4-Bit BCD Adder
4-Bit BCD Adder General Description The F583 high-speed 4-bit, BCD full adder with internal carry lookahead accepts two 4-bit decimal numbers (A 0 A 3, B 0 B 3 ) and a Carry Input (C n ). It generates
DS14C238 Single Supply TIA/EIA x 4 Driver/Receiver
Single Supply TIA/EIA-232 4x4Driver/Receiver General Description The DS14C238 is a four driver, four receiver device which conforms to the TIA/EIA-232-E standard and CCITT V.28 recommendations. This device
DM74LS126A Quad 3-STATE Buffer
DM74LS126A Quad 3-STATE Buffer General Description This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled,
DM74ALS652 Octal 3-STATE Bus Transceiver and Register
DM74LS652 Octal 3-STTE us Transceiver and Register General Description This device incorporates an octal transceiver and an octal D-type register configured to enable transmission of data from bus to bus
NC7SZ32 TinyLogic UHS 2-Input OR Gate
NC7SZ32 TinyLogic UHS 2-Input OR Gate General Description The NC7SZ32 is a single 2-Input OR Gate from Fairchild s Ultra High Speed Series of TinyLogic. The device is fabricated with advanced CMOS technology
FST32X Bit Bus Switch
FST32X245 16-Bit Bus Switch General Description The Fairchild Switch FST32X245 provides 16-bits of high speed CMOS TTL-compatible bus switching in a standard flow-through mode. The low On Resistance of
LM161/LM261/LM361 High Speed Differential Comparators
LM161/LM261/LM361 High Speed Differential Comparators General Description The LM161/LM261/LM361 is a very high speed differential input, complementary TTL output voltage comparator with improved characteristics
DS1489/DS1489A Quad Line Receiver
DS1489/DS1489A Quad Line Receiver General Description The DS1489/DS1489A are quad line receivers designed to interface data terminal equipment with data communications equipment. They are constructed on
74AC573 74ACT573 Octal Latch with 3-STATE Outputs
74AC573 74ACT573 Octal Latch with 3-STATE Outputs General Description The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable (LE) and buffered common Output Enable (OE)
74LCX125 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs
Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs General Description The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing
DM7411 Triple 3-Input AND Gate
DM7411 Triple 3-Input AND Gate General Description This device contains three independent gates with three data inputs each which perform the logic AND function Connection Diagram Dual-In-Line Package
DS DS Series Dual Peripheral Drivers
DS55451 2 3 4 DS75451 2 3 4 Series Dual Peripheral Drivers General Description Features Y The DS7545X series of dual peripheral drivers is a family of versatile devices designed for use in systems that
ADC Bit µp Compatible A/D Converter
ADC1001 10-Bit µp Compatible A/D Converter General Description The ADC1001 is a CMOS, 10-bit successive approximation A/D converter. The 20-pin ADC1001 is pin compatible with the ADC0801 8-bit A/D family.
74ACQ241 Octal Buffer/Line Driver with 3-STATE Outputs
74ACQ241 Octal Buffer/Line Driver with 3-STATE Outputs General Description The ACQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented
Low Power Hex TTL-to-ECL Translator
100324 Low Power Hex TTL-to-ECL Translator General Description The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or
DS90LV017A LVDS Single High Speed Differential Driver
DS90LV017A LVDS Single High Speed Differential Driver General Description The DS90LV017A is a single LVDS driver device optimized for high data rate and low power applications. The DS90LV017A is a current
DM74LS30 8-Input NAND Gate
DM74LS30 8-Input NAND Gate General Description This device contains a single gate which performs the logic NAND function. Features n Alternate Military/Aerospace device (54LS30) is available. Contact a
FSTD Bit Bus Switch with Level Shifting
FSTD16861 20-Bit Bus Switch with Level Shifting General Description The Fairchild Switch FSTD16861 provides 20-bits of highspeed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows
DM74AS651 DM74AS652 Octal Bus Transceiver and Register
DM74AS651 DM74AS652 Octal Bus Transceiver and Register General Description These devices incorporate an octal transceiver and an octal D-type register configured to enable transmission of data from bus
INTEGRATED CIRCUITS. 74ABT125 Quad buffer (3-State) Product specification Supersedes data of 1996 Mar 05 IC23 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1996 Mar 05 IC23 Data Handbook 1998 Jan 16 FEATURES Quad bus interface 3-State buffers Live insertion/extraction permitted Output capability: +64mA/ 32mA Latch-up
DS75160A DS75161A DS75162A IEEE-488 GPIB Transceivers
DS75160A DS75161A DS75162A IEEE-488 GPIB Transceivers General Description This family of high-speed-schottky 8-channel bi-directional transceivers is designed to interface TTL MOS logic to the IEEE Standard
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DS26LS31C/DS26LS31M Quad High Speed Differential Line Driver General Description
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs
74AC244 74ACT244 Octal Buffer/Line Driver with 3-STATE Outputs General Description The AC/ACT244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and
74AC374 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
74AC374 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs General Description The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and
DS36C279 Low Power EIA-RS-485 Transceiver with Sleep Mode
DS36C279 Low Power EIA-RS-485 Transceiver with Sleep Mode General Description The DS36C279 is a low power differential bus/line transceiver designed to meet the requirements of RS-485 Standard for multipoint