Socware, Pacwoman & Flexible Radio Peter Nilsson Program Manager Socware Research & Education Associate Professor Digital ASIC Group Department of Electroscience Lund University
Socware: System-on-Chip Ware A cluster to increase the SoC activities in Sweden University, research institute, and industry cooperation Three Universities LU (CCCD), LiU, and KTH Two parts Research & Education
Why Socware: Design Methodology Schematics Design Compilers Synthesis Layout System-on-Chip MEMS? Layout Layout Processor Core Analog 20K Gates 50K Gates 500K Gates 3 Million Gates 3µ 1µ 0.5µ 0.18µ ( MEMS = MicroElectroMechanical Systems )
Education Program New Engineers on Master level New exit in existing programs (EE, CS etc.) Bachelors from Swedish university colleges Bachelors from international universities 1 year courses and ½ year thesis work
Socware Education in Lund Analog/RF, Mixed Signal, Digital, and Embedded Systems
Research Projects in Lund Flexible Radio (Socware) Flexible CMOS Radio Front-end Embedded Re-configurable Low-Power A/D converter for a Flexible Radio Terminal Flexible Coding/Decoding for PAN Design Space Exploration Highly effective SoC execution platform for mobile multimedia terminals Related projects (CCCD/INTELECT) MIMO - System Modeling of Future Wireless Architectures Flexible OFDM systems for PAN Adaptive Antennas Pacwoman An EU project on PAN
Research Projects in Lund Flexible Radio Projects at ES & CS Departments - Analog/RF - Mixed Signal - Digital - Embedded Systems Socware (CS co-operation) Part of the Pacwoman EU project Design space Exploration SoC Platforms for Mobile Terminals Flexible Radio Frontend Flexible ADC MIMO & Adaptive antennas Flexible Coding Decoding Flexible OFDM Co-integrated Socware Socware PCC CCCD PCC CCCD Intelect Socware Intelect
Flexible CMOS Radio Front-end Complex downconverter: Low-IF or Direct Conversion Flexibility in: Frequency, Noise and Linearity To achieve: Multiple Standards and Adaptivity Kittichai Phansathitwong
Flexible Radio Front-end Initial Work + V out - V in + V in - Simplified Tuning Circuit Common-Gate LNA Chip will contain also mixers Cover two frequency bands (2.4 & 5GHz) Simulations started in 0.18um CMOS process Kittichai Phansathitwong
Re-configurable low-power ADC for flexible radio Re-configurable architecture Minimum power for a given task Adaptive control Input Clock V r Passive S/H Passive S/H Passive S/H Variable clock generation and power management Common reference voltage generator Low power ADC unit Low power ADC unit Low power ADC unit Digital background calibration Reconfigurable output register Output Resolution: Sampling rate: Power: Voltage: 6-12 bits 100MHz - 1MHz 200mW - 10mW 1.0-2.5 V Martin Anderson
MIMO Receiver RF A/D Channel Estimation H r Detector s Decoder Channel Matrix Pseudo-inversion, Doubled to Support High Data Rates H BUFFER r Iterative Nulling & Cancellation X X X CORDIC CORDIC RAM CORDIC X SLICER s Optimal Ordering By SNR RAM RAM ^2 A VLSI Architecture for V-BLAST Detector Zhan Gou
MIMO A VLSI Architecture for V-BLAST Detector Based on the Square Root detection algorithm - Optimal and Numericaly Stabile Low Complexity: CORDIC based channel matrix rotations - Only shifts and additions Results 120 Mbps f clock = 60 MHz (post synthesis simulation) 4 Tx/Rx antennas 16-QAM, Packet Length = 100 symbols Zhan Gou
Implementation of Algorithms for Adaptive Antennas Project phases: 1 Matrix inversion chip 2 Implementation of the music algorithm 3 Build a sounding testbed in cooperation with Telia/PCC Live Beamforming Testbed Algorithm for matrix inversion Fredrik Edman
Adaptive Antennas Matrix Inversion Processor Array for Beamforming Section B perform inversion of the triangular matrix R and multiplies it with Q Section A perform QRfactorisation based on the Squared Givens plane rotation algorithm (SGR) Fredrik Edman
Flexible Coding/Decoding Flexible decoding architectures for PAN Trade-off flexibility and performance in wireless architectures Efficient implementation of multiple coding/decoding algorithms Initial work: Flexible encoding hardware for a wide class of codes Select Self Configuring Block Codes Convol. Codes Turbo Codes Special Parameter Set Common Hardware Encoder Decoder Matthias Kamuf
Flexible Coding/Decoding n 1 Initial work: FPGA realization Convolutional codes 16 feed-forward (n), 1 feedback Memory m=10 Reg Reg Reg 1 Reg m 16 parallel encoders coding flexibility and speed Power saving (shut-down) logic incorporated Tested up to 50 MHz and in post-synthesis simulation up to 95 MHz Interleaver design for turbo codes Investigation of common blocks of decoding algorithms HW reusability Matthias Kamuf
Flexible OFDM OFDM transmitter Maps BPSK, QPSK, 8PSK, 16QAM and 64QAM constellation on each each sub carrier (bit loading) Flexible coder Constellation mapper with bit loading Pipelined 32-1024 points IFFT/FFT processor which can be used in both transmitter and receiver 32-1024 point IFFT processor Signal reordering and CP insertion Variable choice of cyclic prefix (CP) Unused parts are turned off, for low power consumption D/A converter Compatible with the physical layer of Hiperlan2 and IEEE802.11a Fredrik Kristensen
Design Space Exploration Example Constraints Executable specification Hardware/software partitioning and co-design Optimize: Performance, cost, power consumption flexibility, design time etc Simulation, Design Space Exploration, Refinement, Synthesis OBJ ARM7 Instruction Set Simulator HW Bluetooth Wireless Technology used as an industrial example (ISS) intc Addr[15:0] Data[23:0] MCS nwr nrd Henrik Svensson
Pacwoman Personal Area Networks WPANs is a step towards realization of a 4G system segment Ad-hoc networking, low-power scalable radio, layeredarchitecture, networking mechanisms PAN a part of a wider network with gateway capabilities Partners: Imec (BE), CSEM (CH), CPK (DK), U. Cantabria (ES), NTUA (GR), Lund (SE), Motorola (UK), and Miltech (GR) Pacwoman is a Hermes outcome
PAN - A Network of three networks Personal Area Network (PAN) Only you! Community Area Network (CAN) Only you, me and the coffee machine Wide Area Network (WAN)
PAN - A Network of three networks Scalable - 100bps to 10Mbps - Different devices (different complexity/cost) Low-power -Low-rate WPAN - High-rate WPAN Radio integration - single chip Lund part - Silicon realization of critical components - MAC layer optimization (Telecom. Dept.)