Di/dt Mitigation Method in Power Delivery Design & Analysis Delino Julius Thao Pham Fattouh Farag DAC 2009, San Francisco July 27, 2009
Outlines Introduction Background di/dt Mitigation Modeling di/dt Mitigation Simulation Results Bench Measurements Conclusion 2
Abbreviations DVD Dynamic Voltage Drop EA Early Analysis Cdie, Rdie Effective pad to- pad die Cap & Res Icc(t) Equivalent Dynamic Die Current PD Power Delivery PDN Power Delivery Network PI Power Integrity VCD Value-Change-Dump (Vector-based) VLS Vectorless WC Worst Case 3
Introduction Extended On-Die VLS PI analysis for PD di/dt mitigation Developed Extended On-Die dynamic VLS PI simulation flow to enable PD analysis to mitigate di/dt issues Using Early Analysis method, enables the PD designers to influence architectural or micro-architectural direction/choices to improve system-level robustness and performance On-die noise can impact system-level voltage margin Mitigation concepts and techniques for di/dt can reduce ondie noise Result: improved system-level voltage margins 4
Background: Problem Statement Worst-case (WC) power delivery (PD) noise is not necessarily the result of high-power ops. High-power ops (i.e.., virus-like behavior) results in high % of cell activity for long duration of time WC power delivery noise results from events that occur on the time-scale of Power Delivery Network (PDN) resonance Examples: SCAN, power management (gating), performance or operating mode changes (hi<->low or change frequency of operation) Influencing architectural or micro-architectural design choices requires tools that architects find credible and flexible to use (represent arch performance at the proper level of abstraction with the what-if analysis capabilities) 5
Design info. Background: Stages for PD-EA --- Concept/VLS to design/vcd Engineering estimates of model Extracted models from layout VLS database available VCD vectors available We have implemented PD-EA Power Delivery Early Analysis, a way to use tools intended primarily for post-layout at early stages in the design cycle while limited design collaterals available Specific di/dt vectors are generally not available for PD designers until later stage of the design cycle Design collaterals and specific vectors (VCD) may not be compatible at early stages of the design. VLS based analysis can be made to closely represent the global conditions for the VCD-based when given the proper system level parameters (e.g. power, clocking schemes and refined partition level -floorplan- distribution) Time 6
di/dt Mitigation concept Sharp di/dt is a risk event associated with fast current transients. di/dt mitigation is a design concept to reduce the sharpness and the impact of those fast current transients Causes and ways to mitigate di/dt issue Clock gating & ungating Power gating & ungating Staggering logic activities So, di/dt mitigation is modifying the events and sequences, to lower the di/dt thus reducing the DVD (dynamic voltage drop) Di/dt mitigation concept Original Power event without di/dt mitigation enabled With di/dt mitigation 7
Modeling di/dt Mitigation method Extension of dynamic vectorless, allow the users to specify different power at different stages Default VLS assumes a constant power for clock-clock power analysis Enhanced VLS approach enable scaling power per time region to implement di/dt mitigation concepts at the PDN time scale. Beside the on-die clock-clock operation, the focus is on the Power Delivery larger time scale events (e.g. micro seconds scale for low and mid-frequency operations) Simple input text (or TCL) format allows the users to control: initial, final power and transition time Simple text file input to specify the power profile Clock cycle Power (W) 1 0.4 11 0.5 12 0.7 13 0.8 25 0.6 30 0.4 31 0.25 41 25 Icc(t) or Power with default VLS with constant power Icc(t)/Power with di/dt mitigation feature enabled 8
Usage Flow Layout, Libraries, Package/Board models Power / activity target #1 Power / activity target #2 Power / activity target #n Duration of Duration of Duration of mode mode mode Combined scenario Total duration ~ sum of all mode durations Time domain, multi-cycle analysis 9
Simulation Results This is an example of a large clock-clock di/dt (when pico-second time scale current variation is large compared to the nano-second current variation) applied di/dt mitigation method BEFORE: default vectorless Icc(t) with constant average power which can not reflect w/c DVD condition for some power management schemes BEFORE: DVD of the typical package and board PDN when excited by default vectorless Icc(t) AFTER: Icc(t) in the enhanced dynamic vectorless mode to present an example of power management scheme AFTER: DVD in the enhanced dynamic vectorless Icc(t) to reflect power management schemes Top) Supply current Icc(t) in default VLS mode with constant average power not reflecting w/c DVD Dynamic voltage droop (DVD) of the typical package and board PDN when (Bottom) Supply current Icc(t) in Dynamic VLS enhanced 10 07.27.2009 Di-Dt Mitigation Method in Power Delivery Design & excited Analysis by large time-scale current variation Icc(t) mode with power variation in larger time scale in certain power management scheme (Top) DVD stimulated by Icc(t) in default VLS mode with constant average power (peak to peak DVD is 48mV) which does not reflect the w/c DVD (Bottom) with di/dt mitigation mode, DVD shows significant larger noise
Simulation Results This is an example of small clock-clock scale di/dt (when pico-second time scale current variation is small compared to the nano-second current variation) while applying di/dt mitigation BEFORE: default vectorless Icc(t) with constant average power which can not reflect w/c DVD condition for some power management schemes BEFORE: DVD of the typical package and board PDN when excited by default vectorless Icc(t) AFTER: Icc(t) in the enhanced dynamic vectorless mode to present an example of power management scheme AFTER: DVD in the enhanced dynami vectorless Icc(t) to reflect power management schemes Enhance VSL mode to control power magnitude and slew rates in power management scenarios Worst case DVD in enhanced VSL reflecting different slew rate, power magnitudes 11
Simulation Results This is an example of a di/dt mitigation Large scale clock-clock di/dt Di/dt mitigation feature enables the analysis of different Power Architecture changes. Different Power Architecture modes would provide different power transitions resulting in different dynamic voltage drop impacts Dynamic voltage droop impact due to different Power Architecture changes. Dynamic VLS enables the analysis of the DVD impacts of such Power Architecture changes. 12
Bench Measurements of di/dt mitigation On-die measurements shows the impact of di/dt mitigation enabled design (significant reduction of on-die P-P noise) di/dt mitigation DISABLED on-die noise 349.4 mvpp di/dt mitigation ENABLED on-die noise 201.1 mvpp Silicon measurements show that di/dt mitigation improves the dynamic voltage droop significantly 13
Bench measurement of di/dt mitigation --2 On-die measurement with di/dt mitigation DISABLED (Zoom-in) Zoom-in view of dynamic voltage drop without di/dt mitigation 9.8ns 9.8ns 284.4mVpp 258.0mVpp 933MHz Dynamic voltage 1 st droop follows PDN resonant frequency of ~ 100Mhz (9.8nS) 33.5ns Similarly, dynamic voltage 1 st bounce follows PDN resonant frequency of ~ 100Mhz (9.8nS) 14
Bench measurement data of di/dt mitigation On-die measurement with di/dt mitigation ENABLED (Zoom-in) Zoom-in view of dynamic voltage drop with di/dt mitigation impact 933MHz 201mVpp 15 di/dt mitigation reduces the dynamic voltage 1 st droop/bounce.
Conclusion In enabling a power delivery design & analysis flow from pre-layout to post-layout, we found a need for a full-chip simulation that would have sufficient credibility to enable architectural what-if analysis and changes. In pre-layout phase, we use Vectorless PI-EA (Power Integrity Early Analysis). In post-layout phase, we use vector-driven VCD-based dynamic simulations. Between these two phases, dynamic vectorless is applied and we have enhanced this dynamic vectorless to simulate di/dt mitigation to meet the PDN needs. di/dt mitigation can effectively reduce on-die noise caused, for example, by clock gating, power gating and abrupt changes in activity. In future work we intend to combine this capability with timing or frequency impact so that accurate cost-benefit analysis can be associated with proposed architectural changes. 16