RF Comparator XT06 DATA SHEET FEATURES FUNCTIONAL BLOCK DIAGRAM Single-supply operation: 3 V to 5 V 4 ns propagation delay at 5 V supply voltage Up to 150 MHz input Latch function HIGHLIGHTS Low input bias current Output signal latching APPLICATIONS High-speed ADC s Digital communications Clock recovery and clock distribution Phase detectors High speed sampling Zero-crossing detector DELIVERABLES Datasheet GDSII database Customer support GENERAL DESCRIPTION The is a low power RF comparator with 4 ns propagation delay designed for using in applications, where continuous-into-discrete signal conversion or comparison of voltages is required. The comparator can be used in digital systems for clock recovery. The device is equipped with the latching (fixation) function of the output signal. The input stage cascade is implemented in CMOS transistors providing low input bias current. The comparator operation is specified over the industrial temperature range (-40 C to +85 C). GDSII database contains a ring of pads with built-in ESD protection up to 2000 V. 1/6
LIST OF CONTENTS Features 1 Functional block diagram 1 Highlights 1 Applications 1 Deliverables 1 General description 1 Device parameters 3 Pin configuration 4 Pin functional description 5 Esd-protection 5 Equivalent circuits 5 Timing diagram 6 2/6
DEVICE PARAMETERS V+ = 5 V; V- = 0; TA = 25 0 С, unless otherwise noted. Parameter Conditions Min Typ Max DYNAMIC PERFORMANCE Input Frequency, MHz 400 mv p-p sine wave 150 200 mv step with 100 mv overdrive 2.50 3 Propagation Delay, ns -40 C TA 125 C Rise time, ns Fall Time, ns 200 mv step with 5 mv overdrive СL=10 pf, 20% to 80% СL=10 pf, 80% to 20% DIGITAL OUTPUTS 5.25 0.25 0.20 Logic 1 Voltage, V IOH = 10mA, ΔVIN>250mV 4.90 Logic 0 Voltage, V IOL = 10mA, ΔVIN>250mV 0.06 LATCH ENABLE INPUT Logic 1 Voltage Threshold, V 1.65 Logic 0 Voltage Threshold, V 1.60 Minimum pulse width, ns 0.20 Setup Time, ns 0.85 Hold Time, ns 0.85 INPUT CHARACTERISTICS Offset Voltage, mv 1-σ 3.3 3.7 Input Common-Mode Voltage Range, V Common-Mode Rejection Ratio, db 0 3 0V VCM 3V 80 Input Capacitance, pf 0.97 POWER SUPPLY Power Supply Rejection Ratio, db 4.5V V+ 5.5V 75 Ground Supply current, ma 8.8 9.5 3/6
DEVICE PARAMETERS (continued) V+ = 3 V; V- = 0; TA = 25 0 С, unless otherwise noted. Parameter Conditions Min Typ Max DYNAMIC PERFORMANCE Propagation Delay, ns 100 mv step with 20 mv overdrive DIGITAL OUTPUTS 4.65 Logic 1 Voltage, V IOH = 10mA, ΔVIN>250mV 2.86 Logic 0 Voltage, V IOL = 10mA, ΔVIN>250mV 0.08 INPUT CHARACTERISTICS Offset Voltage, mv 1-σ 3.5 3.7 Input Common-Mode Voltage Range, V Common-Mode Rejection Ratio, db 0 1 0V VCM 1V 57 POWER SUPPLY Power Supply Rejection Ratio, db 2.7V V+ 6V 57 Ground Supply current, ma 3.7 3.8 PIN CONFIGURATION Figure 1. Pin configuration 4/6
PIN FUNCTIONAL DESCRIPTION Pin name Description Comments 1 V+ Positive Supply Terminal Typical value: 5 V 2 LATCH Latch enable input Typical value: 0/5 V 3 QA Complementary Output (-) 4 QA Complementary Output (+) 5 GND Negative Logic Supply Typical value: 0 V 6 V- Negative Supply Terminal Typical value: 0 V 7 IN- Analog Input (-) of the Differential Input Stage 8 IN+ Analog Input (+) of the Differential Input Stage ESD-PROTECTION ESD-protection of not less than 2 kv level for HBM discharge is provided for all analog inputs and outputs of the comparator. EQUIVALENT CIRCUITS PAD I/O ESDstructure Figure 2. Analog input/output 5/6
TIMING DIAGRAM Figure 3. Timing diagram of the Comparator The time diagram (Fig. 3) represents graphic information in case of 200mV input signal step with 100mV overdrive. There is also shown the latch function. 6/6