Int. J. Signal and Imaging Systems Engineering, Vol. 7, No. 1, 2014 3 A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator P. Ghosal* Department of Information Technology, Bengal Engineering and Science University, Shibpur Howrah 711103, India Fax: 91-33-26682916 E-mail: prasun@ieee.org *Corresponding author H. Rahaman Department of Information Technology, Bengal Engineering and Science University, Shibpur Howrah 711103, India Fax: 91-33-26682916 E-mail: rahaman h@yahoo.co.in Koyel Mukherjee, Dibyendu Ballabh School of VLSI Technology, Bengal Engineering and Science University, Shibpur Howrah 711103, India E-mail: koyel.666@gmail.com, dibyendu.ballabh@gmail.com Abstract: DLL based clock generation has proven itself a viable alternative in today s clock design segment over the traditional PLL based design by offering lower design complexity with satisfying low power budget. In this paper, a novel design of an on-chip clock generator of very low frequency of 250 KHz and 50% duty cycle using a Digital Delayed Locked Loop (DLL) has been presented. The worst case jitter produced by the clock is only 11.3 ns. The clock has rise time and fall time of 164.39 ps and 123.7 ps (on an average) respectively with a glitch of 6 mv. The clock produces a very low power of 3.92 mw. The design was implemented under 180 nm process technology and assuming 1.8 V power supply. Keywords: Low frequency clock generator; DLL based clock design. Reference to this paper should be made as follows: Ghosal, P., Rahaman, H., Mukherjee, K., and Ballabh, D. (2011) A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator, Int. J. Signal and Imaging Systems Engineering, Vol. 1, Nos. 3/4, pp.197 212. Biographical notes: Prasun Ghosal has completed his M.Tech. (2005) as well as B.Tech. (2002) in Radio Physics and Electronics Engineering from Institute of Radio Physics & Electronics, University of Calcutta, India. He is also an Honours Graduate (major in Physics) from Ramakrishna Mission Vidyamandira, Belur (1999) under University of Calcutta. Presently he is pursuing for his Doctoral Award and submitted his dissertation. He is currently associated as an Assistant Professor with the Department of Information Technology in Bengal Engineering & Science University. Prior to this he has served the same University as a Lecturer and Senior Research Fellow. He is the recipient of Young Scientist Research Award (National) for the year 2010-11 from Indian Science Congress Association in the area of Information and Communication Science & Technology (including Computer Science). He is a member of the IEEE, ACM, IAENG, and ISCA. His research interests include VLSI Physical Design, Design of Embedded Systems, Networkon-Chip, and Mobile Computing. Hafizur Rahaman received the Bachelor of Electrical Engineering degree from Calcutta University, India in 1986, the Master degree in Electrical Engineering, from Jadavpur University, Calcutta, India in 1988. He served CMPD Institute (R & D organization), India from 1988 to 1995. He served as a faculty member at Indian Institute of Information Technology-Calcutta, India from 1995 to 2003. In 2003, he wrote his doctoral thesis Copyright c 2009 Inderscience Enterprises Ltd.
4 P. Ghosal et al. on Studies in Deign for Testability Techniques for Stuck-open and Delay Faults at the Department of Computer Science and Engineering, Jadavpur University, Calcutta, India. Since 2003, Dr. Rahaman has been on the faculty of the Bengal Engineering and Science University, Shibpur, India, where he is full professor. Dr. Rahaman visited as Post Doctoral Research Fellow at the department of Computer Science, Bristol University, UK during 2006-2007. His research interest includes logic synthesis and testing of VLSI circuits, fault-tolerant computing, synthesis and testing of reversible quantum circuits and design and testing of Galois Field Arithmetic circuits. He has published several research articles in archival journals and refereed conference proceedings. He is the coordinator of the department of Information Technology (DIT), MCIT, Govt. of India funded SMDP (Special Manpower Development in VLSI Design and related Software) research project at Bengal Engineering and Science University, Shibpur, India. Dr. Rahaman is a Member of the VLSI Society of India (VSI), the IEEE, the IEEE Computer Society, and ACM Sigda. He served on the conference committees of the International Conference on VLSI Design, the VLSI Design and Test Workshop (VDAT), Asian Test symposium (2005). Koyel Mukherjee has completed her B.Tech.(2008) in Electronics and Communication Engineering under West Bengal University of Technology, India, and M.Tech.(2010) in VLSI Technology under Bengal Engineering & Science University, Shibpur, India. Presently she is associated with ECE Dept, Seacom Engineering College, Howrah, India as a Lecturer. Dibyendu Ballabh has completed his B.Tech.(2007) in Electronics and Communication Engineering under West Bengal University of Technology, India, and M.Tech.(2010) in VLSI Technology under Bengal Engineering & Science University, Shibpur, India. He is currently working as a Software Engineer in Tata Consultancy Services. 1 Introduction Most of the clock generators used in today s high performance micro-processors employ Phase Locked Loop (PLL),Kurita et al. (1991)Yang et al. (2009) which includes Voltage Controlled Oscillators (VCO). But the frequency generated by these clocks are either a few GHz or at least a few MHz. The present design was targeted to design a circuit to generate a clock signal of 250 KHz, which is, indeed a very low frequency compared to the available ones. These types of clocks are finding greater applications in different domains nowadays, viz. in some embedded systems, in electronic gas or pressure sensors for mining applications etc. 1.1 PLL vs DLL The PLL is a higher order system with high design complexity (Moorthi et al., 2008) (Kurita et al., 1991). Its loop bandwidth (critical for stable operation) can change due to process, voltage and temperature (PVT) variation. It suffers from high jitter problems that accumulates over the oscillation cycles causing peak phase error considerably larger than original phase variation (Yang et al., 2009). Moreover it takes an input clock and generates a clock which has frequency much higher than the input clock. But since the target of the proposed job is to design clock with a frequency in the range of few hundred KHz which is much lower than the available ones, hence PLL approach for the present job was not the right one. On the other hand, a DLL can be designed with minimum circuit complexity. (Rantala et al., 2007) (Mesgarzadeh et al., 2009) (Kim et al., 2002). Here a DLL based Clock generator with first order loops has been proposed that does not incorporate VCO. Moreover it is preferred due to its lower power consumption, smaller area, low noise sensitivity, lower jitter, and higher flexibility on supply voltage. A simplified DLL based clock generator (Figure 1) consists of a phase detector, delay controller, and delay line. The output of the Delay Line is compared with the reference clock, utilizing a phase detector (PD). Based on the phase difference between the inputs of the PD, a control signal is generated for a delay controller. The delay controller controls the total delay in the delay line by producing proper signals. This delay controller can be a charge pump in an analog DLL or a counter in digital DLL. When the delay difference between the output of the delay line and the reference clock is exactly one period of the reference clock, the DLL is correctly locked. At this point, the edge of the output clock starts to move back and forth around the edge of the reference clock to keep the DLL in the lock condition. The rest of the paper is organized as follows. Section 2 summarizes the background and motivation of the work. Section 3 describes the proposed architecture of the design in detail. Section 4 describes the layout implementation issues. Experimental results and observations are summarized in section 5, and finally section 6 concludes the paper.
A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator 5 P n Phase Detector Delay Controller Reference Clock (2MHz) Phase Detector Phase Error Compensator Loop Control Unit Delay Line Delayed Clock DCDL Ref Frequency Divider ( / 8) P 1 P 2 P 3 P n Figure 1 Simplified Block Diagram of a DLL Based Clock Generator Output Clock (250 KHz ) Figure 2 Block diagram of proposed DLL based low frequency clock generator 2 Background and Motivation The Delay Locked Loop (DLL) and their applications have been studied during the last few years. DLL used in designing clock generator and Phase Generator, has proven itself a viable alternative to provide very good performance (Rantala et al., 2007) (Mesgarzadeh et al., 2009) (Kim et al., 2002). In theory a clock DLL could have many delay stages as required to generate different phases, though the proposed clock generator is designed to generate single phase clock. 2.1 Low Frequency Clock Generation Problem A Clock generation technique with a very low frequency in the range of few hundred KHz is comes with a number of problems. Any Clock generation technique by using either PLL or DLL requires an external clock at the input provided by some oscillator. These external clocks so far available have at least operating frequency of 1MHz. so to obtain the 250KHz clock, a frequency divider circuit is required in addition with the PLL/DLL. Thus an additional power and area consumption and timing delay is introduced in the circuit. If the frequency division is done prior the DLL operation, the input of the DLL would become so low that it would require a very high value of passive components for filtering purpose. These high value of passive components themselves demand for almost the same area as rest of the circuit. Thus the chip area becomes larger and power consumption becomes more. But if the frequency divider circuit is placed at the output of the DLL, the DLL can operate with clock of higher frequency at the input, so it would require comparatively lower value of passive components. So the area and power consumption also becomes lower. 3 Proposed Architecture A block diagram of the proposed architecture (Figure 2) of the design of the low frequency clock generator consists of the following units. Phase Detector (PD) Delay Control Unit (DCU) Phase Error Compensating (PEC) Block Digitally Controllable Delay Line (DCDL) Frequency Divider (by 8) The basic building block of the entire design is a positive edge triggered master-slave D type flip flop. This D flip flop has been used as the fundamental block for the 5 bit counter, 5 bit register and the frequency divider circuit. The D flip flop is designed using Transmission gate logic (as transmission gate based logic has proven itself a competent alternative for designing low power VLSI circuits). The master is negatively edge triggered and the slave is positively edge triggered. The D flip flop could have been designed using pass transistor logic also. But pass transistor logic results in lowering of voltage swing when they are cascaded, as they are implemented using either nmos or pmos. But since in the pass transistor logic both the nmos and the pmos are connected in parallel, so full voltage swing is always achieved. The Phase Detector (PD) compares the phases of the input clock and the delayed output of the DLL. If the phases match, the PD generates a logic 0 output and logic 1 otherwise. At the same time the PEC averages these output value to a DC or almost DC level and compares result with an externally applied reference voltage of 700 mv. If the phase difference is very high, the corresponding average value will also be high. If this value exceeds the V ref the comparator output of the PEC
6 P. Ghosal et al. becomes high. That means the DLL is not locked. It is in open loop condition. Similarly if the clocks are in same phase, the comparator output will become zero to indicate that the DLL is locked. The PEC output controls the performance of the Delay Control Unit by acting as the select lines of the MUX (multiplexer) network. The 5 bit counter and the 5 bit register of the Delay Control Unit keeps track of the delay between the input and the DLL output. The output of the DCDL is 8 times frequency divided to obtain the desired clock of 250 KHz. 3.1 Phase Detector The phase detector is basically an XOR gate. The XOR gate is built using transmission gate. The external reference clock frequency is assumed to be equal to 2 MHz and its delayed version are applied as the input to the XOR gate. Depending on whether there is a phase difference or not between the two input clocks, the XOR gate generates a signal HIGH or LOW. If the reference clock leads the delayed clock, then the output is an UP signal. If the delayed clock leads the reference clock, the output is a DOWN signal. 3.2 Delay Control Unit (DCU) A 5 bit counter, 5 bit register and a multiplexer (MUX) network form the Delay control Unit. The bit count of the counter and the register depends on the selection of the reference voltage of the comparator in the PEC block. The reference voltage of the comparator is formulated as V ref = V dd /2 n (1) where, V dd = 1.8 V and n = Bit count of the counter. Since the reference voltage of the comparator is 56 mv, so the calculated value of the bit count of the counter (n) is 5. Had the bit count of the counter been greater than 5, the reference voltage of the comparator would be very low. It is experimented that such a low value of reference voltage produces a large delay and the rising edge and the falling edge of the output pulse of the comparator would not pass through the points where the input of the comparator just crosses the reference voltage. If n < 5, then the V ref would be very high. In that case the V ref may stay higher than LPF output in most of the time, thus resulting in constant LOW output at the comparator. For n = 5, we may get a satisfactory DLL result. As mentioned already, the counter and the register are built using positive edge triggered master-slave D flip flop. Depending upon the phase error produced by the phase detector circuit, the 5 bit counter can generate 2 n = 32 combinations of output. The 5 bit register stores the value of the counter output. Until the phase difference between the reference clock and the delayed clock remains less than the total time period of the reference clock, the entire circuit remains closed loop. As soon as the phase difference becomes exactly equal to the total time period of the reference clock, the DLL gets locked and the closed condition breaks. At this time the output of the counter becomes all 1s. Corresponding value is stored in the register. All the select (SEL) lines of the multiplexers (MUX) are driven by the output of the comparator of the PEC block. The inputs A n and B n are the outputs of the counter and the register respectively. Until the DLL is locked, the output of the comparator is HIGH, which makes the output of the counter to be selected. When the DLL is locked, the comparator output becomes all LOW, which selects the register outputs. The outputs of the MUX network are fed as the select line for the Delay Control Unit. 3.3 Digitally Controllable Delay Line (DCDL) The controllable delay line consists of series of delay cells. Each of the delay cells comprises of two successive inverters and a two input multiplexer. The select lines are driven by the output of the MUX network. One of the input of the multiplexer is the output from the inverter series. Another input is a bypass line directly from the input of the first inverter. Since each of the inverters introduces some fixed delay to the circuit, hence when the reference clock passes through the inverter series, the delay line introduces delay to the reference clock. The MUX selects output of the inverter series/bypass line when the select line is HIGH/LOW respectively. So when all the MUXs have SEL = HIGH, the delay line introduces the maximum delay and when all the SEL = LOW, it generates the minimum delay. Thus the DCDL, with single inverter delay (with t r = t f = 3 ns) = 0.3 ns introduces delay as follows. Delay through the bypass line and single MUX = 16.2 ps (minimum) Delay through the double inverters and single MUX = 35.3 ns (maximum) 3.4 Phase Error Compensator (PEC) The PEC block consists of an additional phase detector (PD) followed by a low pass filter and a comparator. The PD detects the phase difference whereas the LPF averages the output of the PD. The comparator compares the average value with respect to a reference voltage (56 mv) (V ref = V dd /2 n ) and generates a binary signal for the LCU. When the phase difference is small, the average at the LPF is closed to zero and the DLL gets open. If any mismatch is introduced in the phases, the average value starts to increase. When it is more than the reference voltage, the LCU forces the DLL to enter into close loop mode to compensate for the phase error, the average voltage decreases and the open loop mode is reactivated. If a first-order RC filter is being utilized in the implementation of the PEC block then
A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator 7 Figure 3 Digitally Controllable Delay Cell Figure 4 Phase Error Compensator the satisfaction of the constraints gives us the following range for RC product in the low-pass filter 0.4/f ref < RC < 1/f ref (2) By utilizing this range, we can determine the parameters required to design the low-pass filter for the PEC block. So by calculation for f ref = 2MHz, RC is chosen to be 200 ns, where, R = 40KΩ and C = 5pF. 3.4.1 Level Shifter As already calculated V ref = 56mV. But the comparator so designed can t give satisfactory result at such a low voltage. Instead the result is quite satisfactory at V ref = 700mV. So to achieve proper functionality and also to keep proper reference voltage, the reference voltage level needs to be shifted up. Hence the use of a level shifter was necessary. Therefore, a level shifter is used which can shift up the DC voltage of the o/p of the Low pass filter to (700 56 = 644)mV. So the comparator can now work with V ref = 700mV. The level shifter is formed using two p-mos transistors. The transistors are specially sized to obtain the desired result. The sizes of the driver and the diode connected load transistors are W/N = 8.5u/200n and W/L = 300n/4u respectively. Though level shifting of 644 mv is required but this level shifter provides a level shift of about 610 mv (shown in Figure 17). This reduction in the shifted level does not significantly hamper the desired functionality of the entire PEC block. Hence the provided shifted value was accepted. Figure 5 Timing Diagram of the Phase Error Compensator Block 3.5 Power Optimization The PEC block was an essential block in the circuit to track the phase error. From the expression of RC time constant (Equation 2) it is clear that if f ref is very high, RC becomes very low and vice versa. Hence f ref is selected to be 2 MHz instead 250 KHz. Had the frequency divider been used at the input of the DLL block, the input f ref would become 250 KHz, i.e. RC > Figure 6 Level Shifter
8 P. Ghosal et al. 4ms. So the passive components would be so high that it would result in significant heating effect and considerable power dissipation. So instead of placing the frequency divider at the input of the DLL, it is placed at the output of the DLL so that RC > 0.8ps only and the power dissipation can be significantly reduced. The 2 MHz f ref then can be only 1/8 times divided to obtain the required 250 KHz. The f ref could have been higher. But then due to the number of additional blocks in the frequency divider would have caused more area and higher power dissipation. Thus by choosing f ref = 2MHz, with RC = 200 ns and frequency divider (by 8) circuit, the power dissipation obtained at the post layout simulation is as low as 3.92 mw only. Also, Fingering technique was used to break the large size transistors into small functional units. This fingering technique also helps in lowering the overall power dissipation since then the power is to be distributed over small sized gates. Similar fingering technique was also used to the large size transistors of the comparator and the level shifter to reduce the power dissipation. 3.6 Jitter Optimization Figure 7 RCX view of an inverter shows the position of the parasitic effects Jitter introduced in clock signal results into variation of the clock time period over cycles. Thus the jitter may increase in a feedback process. This effect might be predominant in PLL based approach as it incorporates Voltage Controlled Oscillator (VCO) as a component. VCO accumulates jitter over oscillation cycles. So the basic jitter reduction technique was taken at the very first step of the design by not choosing the PLL based design. Moreover in the proposed design Digitally Controllable Delay Line (DCDL) was chosen instead of the Voltage Controllable Delay Line(VCDL), as DCDL have a higher ability to reduce the noise induced jitter in the clock. On the other hand, VCDL is prone to jitter effect caused by phase detection noise, internal noise in substrate, VCDL Control voltage noise etc. Figure 8 Integrated On-chip Clock Generator 4 Layout Implementation The Layout implementation of the design was done in Virtuso editor window in Cadence Tool Suite. After doing the individual layout designs, physical verifications like Design Rule Checking (DRC), Layout vs Schematic (LVS), and Parasitic Extraction (RCX) were done in Assura window. The RCX checking can only show the positions where the parasitic effects have generated. But there is no option to eliminate the effect, other than redesigning. Individual blocks were then finally integrated. The final circuit layout is surrounded by Power supply rails to have the access to them through the shortest path. The dummy fillers were placed in every vacant position to avoid capacitive effect variation. The RCX view (after parasitic extraction) of an inverter is shown in Figure?? and the final av-extracted view of the integrated clock generator with supply rail is shown in Figure 10. 5 Experimental Results and Observations After post layout simulation it is found that the normal threshold voltage of the inverter has shifted from 900 mv (pre layout simulation) to 791.2 mv at the rising edge, and 879.1 mv at the falling edge respectively. This variation of the threshold voltage has an obvious effect on the switching activity of the inverter and hence on the entire circuit performance. When the pre-layout simulation was done without adding a buffer at the output, the final clock generator shows a glitch of 67 mv. By putting a strong buffer at the output of the frequency divider circuit, the glitch
A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator 9 Figure 12 Falling edge of the inverter after post layout simulation Figure 9 Clock Generator with Supply Rail and Dummy Fillers Figure 13 Comparator output after post layout simulation Figure 10 AV Extracted view of the Clock Generator with Supply Rail Figure 14 Shift of Comparator output at the point of crossing the reference voltage Figure 11 Rising edge of the inverter after post layout simulation could be minimized to a value of only 15 mv (Figure 16). At the post-layout simulation with the buffer, the circuit generates a clock with glitch reduced to a value of only 6 mv. The comparator output doesn t follow the rising and falling edges of the input at the zero crossing. There is a little delay at the zero crossing points. For both the rising and falling edges, this delay is about 0.02 ns. Final clock output is shown in Figure 18.
10 P. Ghosal et al. Figure 18 Final clock after frequency division and buffering Figure 15 Glitch of the final clock without buffer Table 4 Final Specification of the integrated On-chip Clock Parameters Value Transistor Count 359 Total area 353/198 um 2 Pin Counts 5 Total Power Dissipation 3.92 mw Rise Time 164.39 ps Fall Time 123.7 ps Jitter 11.3ns Duty Cycle 50% Glitch 6 mv Figure 16 Reduced glitch of final clock with buffer 5.1 Process Corner Analysis Process Corner Analysis is concerned about the circuit functionality according to the variation of the threshold voltage (V th ). Threshold voltage variation is strongly dependent on the temperature variation, and the supply voltage variation. When the device has lower V th, the device operates faster, for higher value of V th, circuit operation becomes slower. According to the speed of operation the circuit can operate in five different modes: Typical-Typical(tt), Fast nmos-fast pmos(ff), Slow nmos-slow pmos(ss), Slow nmos-fast pmos(snfp), and Fast nmos-slow pmos(fnsp). Following tables summarize different pre-layout and the post layout simulated results of individual subcircuits. Snapshot of the fabricated chip has been presented in Figure 19. 6 Conclusions Figure 17 Output of level shifter (level shifting by 610 mv) The entire clock so generated, since has a very low frequency, and since the jitter was to be minimized significantly to a very low value (80 ns), the resistor and the capacitor value hence taken was very high. Accordingly the size of the entire chip became quite
A Low Power, Low Jitter DLL Based Low Frequency (250 KHz) Clock Generator 11 Table 1 Process Corner Analysis (Pre-layout simulation) [With load (R = 50Ω, C = 10pF )] Process Jitter Rise Fall Power Corner (ns) time(ns) time(ns) dissipation(mw) tt 7.3 38.5 59.5 1.684 ff 5.14 31.91 45.61 1.174 ss 3.43 29.833 75.35 1.315 snfp 14 39.43 49 0.0942 fnsp 8.875 38.5 36.622 3.605 Table 2 Process Corner Analysis (Post-layout simulation) Without load Process Power Jitter Rise Fall Glitch Corner Dissipn(mW) (ns) time(ps) time(ps) (mv) tt 3.929 8 71.07 91.91 6 ss 0.092 11.3 104.77 47.44 4 snfp 0.433 6.5 164.39 123.76 8 fnsp 0.609 4.1 7.37 8.23 7 ff 0.212 5 33.114 43.44 10 Table 3 Comparison Table for Pre-layout and Post-layout Simulated Results Observation tt ss snfp fnsp ff Power Pre 3.48 1.61 0.62 0.86 1.68 dissipation(mw) Post 3.92 0.092 0.433 0.609 0.212 Jitter Pre 9.75 8.75 5.56 12 13 (ns) Post 8 11.3 6.5 4.1 5 Glitch Pre 65.7 43.2 78.9 62.0 97.3 (mv) Post 6 4 8 7 10 Rise Pre 27.89 12.09 4.61 12.06 12.73 time(ps) Post 71.07 104.7 164.39 7.37 33.14 Fall Pre 7.74 9.002 5.511 17.63 14.87 time(ps) Post 91.91 47.44 123.7 8.23 43.44
12 P. Ghosal et al. References Figure 19 Snapshot of the fabricated chip large. In many parts of the circuit, a number of buffers of various transistor sizes were implemented to have a very sharp time response of the corresponding output lines. The final 250 khz clock at the output of the frequency divider circuit had a pulse with frequent glitches of 65.7 mv at the high clock edges. These glitches at the final output could significantly be reduced to a value of only 6 to 7 mv by putting a very strong buffer at the output of the frequency divider circuit. Due to this addition of the buffer, the final output can have an almost ideally sharp Rise time-fall time property. These buffers are designed using strong pmos and weak nmos. Fingering technique was used in different design units to reduce the overall power dissipation. The entire clock generator was tested to observe the result when worst case condition for the externally applied reference clock was considered. The entire circuit was again tested putting an external load of C = 10pF and R = 50Ω. Putting the load at the output leads to a significantly high power dissipation in the range of mw. The circuit was also tested under variable V dd, and temperature. Supply voltage variation has a significant effect on the Rise time and Fall time. Performance of the designed clock in terms of power, jitter, delay etc. cannot be compared with other existing clocks as the there is no other clocks in the market with such a low frequency to the best of our knowledge. Kurita, K., Hotta, T., Nakano, T., Kitamura, N., PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor, IEEE Journals of Solid-State Circuits, Vol. 26, Issue 4, 585-589, Apr 1991. Ching-Yuan Yang, Chih-Hsiang Chang, Wen-Ger Wong, A Σ PLL-based spread-spectrum clock generator with a ditherless fractional topology, IEEE Transactions on Circuits and Systems, Vol. 56, Issue 1, 51-59, Jan 2009. Moorthi, S., Meganathan, D., Janarthanan, D., Praveen Kumar, P., J., Raja paul perinbam, Low Jitter ADPLL based Clock Generator for High Speed SoC Applications, Journal of World Academy of Science, Engineering and Technology, Vol. 42, 632-636, 2008. Arto Rantala, David Gomes Martins, Markku berg, A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 m CMOS, Journal of Analog Integrated Circuits and Signal Processing, Vol. 50, Issue 1, 69-79, Jan 2007. Mesgarzadeh, B., Alvandpour, A., A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode, IEEE Journal of Solid State Circuits, Vol. 44, Issue 7, 1907-1913, Jul 2009. Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang, A lowpower small-area 7.28-ps-jitter 1-GHz DLL-based clock generator, IEEE Journal of Solid State Circuits, Vol. 37, Issue 11, 1414-1420, Nov 2002. Acknowledgement This work was partially supported by the grants from Ministry of IT, Govt of India, under the project SMDP- II (Special Manpower Development Project, Phase II) at BESU, Shibpur. Authors are also thankful to Pranab Roy, Sudip Ghosh, and Somsubhra Talapatra for their help during the work.