Integrated Circuit Design with Nano-Electro-Mechanical Switches Elad Alon 1, Tsu-Jae King Liu 1, Vladimir Stojanovic 2, Dejan Markovic 3 1 University of California, Berkeley 2 Massachusetts Institute of Technology 3 University of California, Los Angeles 3
CMOS is Scaling, Power Density is Not Power Density (W/cm2) 10000 1000 100 Power Density Prediction circa 2000 Sun s Surface Rocket Nozzle Nuclear Reactor 8086 10 4004 Hot Plate P6 80088085 8080 286 386 Pentium proc 486 1 1970 1980 1990 2000 2010 Year S. Borkar Normalized Energy/op 100 80 60 40 20 0 10 0 10 1 10 2 10 3 10 4 1/throughput (ps/op) V dd and V t not scaling well power/area not scaling 2
CMOS is Scaling, Power Density is Not Power Density (W/cm2) 10000 1000 100 Power Density Prediction circa 2000 Sun s Surface Rocket Nozzle Nuclear Reactor 8086 Core 2 10 4004 Hot Plate P6 80088085 8080 286 386 Pentium proc 486 1 1970 1980 1990 2000 2010 Year S. Borkar Normalized Energy/op 100 80 60 40 20 Operate at a lower energy point Run in parallel to recoup performance 0 10 0 10 1 10 2 10 3 10 4 1/throughput (ps/op) V dd and V t not scaling well power/area not scaling Parallelism to improve throughput within power budget 3
Where Parallelism Doesn t Help 25 Energy/op vs. Vdd Energy/op vs. 1/Throughput Normalized Energy/cycle 20 15 10 5 E tot E total E dynamic E leak E dyn E leak Parallelism lowers E/op Parallelism doesn t help 0.1 0.2 0.3 0.4 0.5 Vdd (V) CMOS circuits have well-defined minimum energy Caused by leakage and finite sub-threshold swing Need to balance leakage and active energy Limits energy-efficiency, no matter how slowly the circuit runs 1/ 4
What if There Was No Leakage? 25 Energy/op vs. Vdd Measured MEM Switch IV* Normalized Energy/cycle 20 15 10 5 E tot = E dyn E total E dynamic 0.1 0.2 0.3 0.4 0.5 Vdd (V) Vdd decreases energy decreases Mechanical switch offers near infinite subthreshold slope and no leakage current *R. Nathanael et al., 4-Terminal Relay Technology for Complementary Logic, IEDM 2009 5
Outline Digital Circuit Design with NEM Relays Relay device/circuit basics Comparisons to CMOS Device implications Analog/Mixed-Signal Design with Relays Looking Forward and Conclusions F. Chen et al., Integrated Circuit Design with NEM Relays, ICCAD 2008 6
Switch Structure & Operation Tungsten Channel Tungsten Body Poly-SiGe Gate Poly-SiGe Anchor Poly-SiGe Beam/Flexure Tungsten Source/Drain Open Switch ( OFF ): V gb < V po (pull-out voltage) Closed Switch ( ON ): V gb > V pi (pull-in voltage) R. Nathanael et al., 4-Terminal Relay Technology for Complementary Logic, IEDM 2009 7
NEM Relay as a Logic Element Gate Source Body Drain 4-terminal design mimics MOSFET operation Electrostatic actuation is ambipolar Non-inverting logic is possible Actuation independent of source/drain voltages 8
NEM Relay Model Lumped Verilog-A model for circuit sims: Mechanical dynamics: spring (k), damper (b), mass (m) Electrical parasitics: non-linear gate-body (C gb ), gate-channel (C gc ), and source/drain-body cap (C s,db ), contact (R cs,d ) 9
Relay Characteristics t PI [s] Model 1.E-06 1.E-07 Model Experiment L=50µm 40µm 14µm 0 5 10 15 V DD [V] Lumped model matches measurements Use calibrated models for circuit design 10
Relay Scaling Constant E-field: mechanical delay and V PI scale linearly* Assuming surface forces scale more later For a 90nm device: V PI ~200mV, t PI ~10ns @ V dd = 1V (cantilever beam with W = 90nm, H = 90nm, t gap = 10nm, L = 2.3um) Seems large and slow vs. CMOS, but *H. Kam et al., Design and Reliability of a Micro-Relay Technology, IEDM 2009 11
Digital Circuit Design with Relays CMOS: delay set by electrical time constant Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages Relays: delay dominated by mechanical movement Can stack ~100-200 devices before t d,elec t d,mech So, want all relays to switch simultaneously Implement logic as a single complex gate 12
Digital Circuit Design with Relays 4 gate delays 1 mechanical delay Delay Comparison vs. CMOS Single mechanical delay vs. several electrical gate delays For reasonable load, relay delay unaffected by fan-out/fan-in Area Comparison vs. CMOS Larger individual devices Fewer devices needed to implement the same logic function 13
CMOS vs. Relays: Digital Logic 100 Normalized Energy/op 80 60 40 20 0 10 1 10 2 10 3 10 4 10 5 1/throughput (ps/op) Most processor components exhibit the energy vs. performance tradeoff of static CMOS Control, Datapath, Clock Adder energy performance tradeoff is representative 14
Relay-Based Adder Full adder cell: 12 relays vs. 24 transistors XOR free Complementary signals avoid extra mechanical delay (to invert) Relays all sized minimally 15
N-bit Relay-Based Adder Ripple carry configuration Cascade full adder cells to create larger complex gate Stack of N relays, but still single mechanical delay 16
Simulated Energy-Delay vs. CMOS Energy/op vs. Delay/op across V dd Vdd: 1V 0.5V Compare vs. Sklansky CMOS adder * 9x Vdd: 0.9V 0.32V 30x less capacitance 10x Lower device C g, C d Fewer devices 2.4x lower V dd No leakage energy For similar area: >9x lower E/op, >10x greater delay * D. Patil et. al., Robust Energy-Efficient Adder Topologies, in Proc. 18th IEEE Symp. on Computer Arithmetic (ARITH'07). 17
Parallelism Energy/op vs. Delay/op across V dd & C L Can extend energy benefit up to GOP/s throughput As long as parallelism is available Area overhead bounded Need to parallelize CMOS at some point too 18
Contact Resistance Energy/op vs. Delay/op across V dd & C L Low contact R not critical Enables low force, hard contact material Good news for reliability 19
I DS (A) 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 Fabricated Device Revisited Improve reliability: intentionally increase contact R Coat W electrodes with TiO 2-8.5V -4V 10-14 0 2 4 6 8 10 V G (V) 0V V B =+4V V D =1V V S =0V *H. Kam et al., Design and Reliability of a Micro- Relay Technology, IEDM 2009 Contact resistance [Ω] 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 Gate Drain Body Body 100kΩ specification L=25µm Source Gate Measured in ambient 1.E+0 1.E+3 1.E+6 1.E+9 No. of on/off cycles 20
Relay Energy Limit Spring force must be able to overcome surface adhesion force F A For large contacts, F A scales with area: Extracted surface energy ~5µJ/m 2 Relay energy limit set by required R on *H. Kam et al., Design and Reliability of a Micro-Relay Technology, IEDM 2009 21
Outline Digital Circuit Design with NEM Relays Relay device/circuit basics Comparisons to CMOS Analog/Mixed-Signal Design with Relays Looking Forward and Conclusions 22
CMOS vs. Relays: Mixed Signal I/O energy dominant if core is ~30x more efficient See if I/O circuits can benefit as well Representative examples: DAC & ADC How to process/generate analog signals? No or limited linear gain in relays rely on switching 23
NEM Relay Based DAC DAC Architecture Voltage Output AC Impedance E π V C 2 2 = BIT IO L Same topology as CMOS, except: Add passive R to set impedance Relays gate voltage independent of I/O voltage Energy dominated by actual I/O energy: @V IO =200mV, C L =1pF: 62.8fJ/bit vs. ~780fJ/bit for CMOS 24
NEM Relay Based Flash ADC Topologically identical to CMOS Sample/Hold input Flash Converter bank of comparators Key difference: behavior of comparators 25
Relay Based Comparators Body terminal used to set threshold V T Hysteretic switching: Comparator threshold varies with previous state Need to reset all comparators to the same initial state 26
Relay Based Comparators 60 50 Output Code 40 30 20 Max Min V T 10 0-0.2 0 0.2 0.4 0.6 0.8 1 Input Voltage (V) Ambipolar actuation: Comparators above & below input will evaluate Use a different decoder Each comparator has a dead-zone where it stays off Can use Max or Min of this range to determine code 27
ADC Results V core = 0.3V C = 500fF R = 4kΩ V REF = 1V f samp = 10 MS/s 6-bit res: 5.5fJ/conv Energy dominated by resistor string (320fJ out of 350fJ) Power set by input dynamic range (V REF ), not core voltage FOM improves with more resolution (up to thermal noise limit) Advantages stem from R on C g product 28
Outline Digital Circuit Design with NEM Relays Relay device/circuit basics Comparisons to CMOS Analog/Mixed-Signal Design with Relays Looking Forward and Conclusions 29
Experimental Relay Circuits: Inverter Circuit Diagram Voltage Transfer Char. Voltage Waveforms 30
Circuit Demonstration Test-Chip Test devices Adders Flip-flops/Latches 7:3 Compressor SRAM, DRAM DAC ADC Oscillators F. Chen et al., Demonstration of Integrated Micro-Electro-Mechanical Switch Circuits for VLSI Applications, to be presented at ISSCC 2010. 31
Near-Term Driver: Power Gating Pitch scaling enables high current density Even with high individual device R on TI micro-mirror pitch (~7.5µm): Imax ~ 100mA/mm 2 32
Roadmap 33
Conclusions NEM relays offer unique characteristics Nearly ideal I on /I off Significantly lower C g than CMOS Switching delay largely independent of electrical τ Relay circuits show potential for order of magnitude better energy efficiency Key challenges are scaling & reliability Circuit-level insights have proven critical (contact R) 34
Acknowledgements Students: Fred Chen, Hossein Fariborzi, Abhinav Gupta, Jaeseok Jeon, Hei Kam, Rhesa Nathanael, Vincent Pott, Matthew Spencer, Cheng Wang DARPA NEMS program FCRP (C2S2, MSD) Berkeley Wireless Research Center NSF 35