19-1477; Rev ; 4/99 Low-Power, Serial, 12-Bit DACs with Force/See oltage Output General Description The / low-power, serial, voltage-output, 12-bit digital-to-analog converters (DACs) feature a precision output amplifier in a space-saving 16-pin QSOP package. The operates from a single +5 supply, and the operates from a single +3 supply. The output amplifier s inverting input is available to allow specific gain configuratio, remote seing, and high output current capability. This makes the / ideal for a wide range of applicatio, including industrial process control. Both devices draw only 26µA of supply current, which reduces to 1µA in shutdown mode. In addition, the programmable power-up reset feature allows for a userselectable output voltage state of either or midscale. The 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE standards. An input register followed by a DAC register provides a double-buffered input, allowing the registers to be updated independently or simultaneously with a 16-bit serial word. Additional features include software and hardware shutdown, shutdown lockout, a hardware reset pin, and a reference input capable of accepting DC and offset AC signals. These devices provide a programmable digital output pin for added functionality and a serial-data output pin for daisy-chaining. All logic inputs are TTL/CMOS compatible and are internally buffered with Schmitt triggers to allow direct interfacing to optocouplers. The / incorporate a proprietary on-chip circuit that keeps the output voltage virtually glitch free, limiting the glitches to a few millivolts during power-up. Both devices come in 16-pin QSOP packages and are specified for the extended (-4 C to +85 C) temperature range. The MAX5171/MAX5173 are 14-bit pin-compatible upgrades to the /. For pin-compatible DACs with an internal reference, see the 13-bit MAX5132/MAX5133 and 12-bit MAX5122/MAX5123. Applicatio Digitally Programmable 4 2mA Current Loops Industrial Process Controls Digital Offset and Gain Adjustment Motion Control Automatic Test Equipment (ATE) Remote Industrial Controls µp-controlled Systems Features ±1 INL 1µA Shutdown Current Glitch Free Output oltage at Power-Up Single-Supply Operation +5 () +3 () Full-Scale Output Range +2.48 (, REF = +1.25) +4.96 (, REF = +2.5) Rail-to-Rail Output Amplifier Adjustable Output Offset Low THD (-8dB) in Multiplying Operation SPI/QSPI/MICROWIRE-Compatible 3-Wire Serial Interface Programmable Shutdown Mode and Power-Up Reset ( or midscale) Buffered Output Capable of Driving 4 2mA or 5kΩ 1pF Loads User-Programmable Digital Output Pin Allows Serial Control of External Components 14-Bit Upgrades Available (MAX5171/MAX5173) PART TOP IEW FB RS PDL CLR 1 2 3 4 5 6 Ordering Information TEMP. RANGE PIN-PACKAGE AEEE BEEE AEEE -4 C to +85 C -4 C to +85 C -4 C to +85 C 16 QSOP 16 QSOP 16 QSOP BEEE -4 C to +85 C 16 QSOP 16 11 15 N.C. 14 REF 13 AGND 12 SHDN UPO INL () ±1 ±2 ±2 ±4 Pin Configuration / Functional Diagram appears at end of data sheet. 7 1 D SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. 8 QSOP 9 DGND Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-8-998-88. For small orders, phone 1-8-835-8769.
Force/See oltage Output / ABSOLUTE MAXIMUM RATINGS to AGND, DGND...-.3 to +6 AGND to DGND...-.3 to +.3 Digital Inputs to DGND...-.3 to +6 D, UPO to DGND...-.3 to ( +.3) FB, REF to AGND...-.3 to ( +.3) Maximum Current into Any Pin...5mA Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of the specificatio is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI Continuous Power Dissipation (T A = +7 C) 16-Pin QSOP (derate 8mW/ C above +7 C)...667mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range...-65 C to +15 C Lead Temperature (soldering, 1sec)...+3 C ( = +5 ±1%, REF = 2.5, AGND = DGND, FB =, R L = 5kΩ, C L = 1pF referenced to ground, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise oltage Output Thermal Noise Deity REFERENCE INPUT SYMBOL INL DNL OS GE PSRR Reference Input Range REF Reference Input Resistance R REF MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUTS Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL PUTS Output High oltage Output Low oltage SINAD IH IL HYS I IN C IN OH OL CONDITIONS MIN TYP MAX 12 A ±1 B ±2 ±1 ±1 R L = -.6 ±4 R L = 5kΩ f = 1kHz REF =.5p-p + 2.5 DC, slew-rate limited REF = 3.6p-p + 1.8 DC, f = 1kHz, code = all s REF = 1.4p-p + 2.5 DC, f = 1kHz, code = FFF hex -1.6 ±8 1 12 1 5-1.4 18 35 84 UNITS Bits m µ/ p-p n/ Hz 3.8 2 m IN = or.1 ±1 µa 8 pf I SOURCE = 2mA I SINK = 2mA -.5-84.13.4 kω khz db db 2
Force/See oltage Output ELECTRICAL CHARACTERISTI (continued) ( = +5 ±1%, REF = 2.5, AGND = DGND, FB =, R L = 5kΩ, C L = 1pF referenced to ground, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER DYNAMIC PERFORMANCE oltage Output Slew Rate Output Settling Time Output oltage Swing (Note 3) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply oltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTI Clock Period Pulse Width High Pulse Width Low SYMBOL SR I DD t CP t CH t CL CONDITIONS MIN TYP MAX UNITS.6 /µs To ±.5, from 1m to full-scale 12 µs -.1.1 µa 4 µs = ; f = 1kHz, = 5p-p 1 n-s 4.5 5.5 1 4 4.26.35 1 1 ma µa / Fall to Rise Setup Time t S 4 Rise to Rise Hold Time t H SDI Setup Time t DS 4 SDI Hold Time t DH Rise to D alid Propagation Delay t DO1 C LOAD = 2pF 8 Fall to D alid Propagation Delay t DO2 C LOAD = 2pF 8 Rise to Fall Delay t 1 Rise to Rise Hold Time t 1 4 Pulse Width High t W 1 3
Force/See oltage Output / ELECTRICAL CHARACTERISTI ( = +2.7 to +3.6, REF = 1.25, AGND = DGND, FB =, R L = 5kΩ, C L = 1pF referenced to ground, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity (Note 5) Differential Nonlinearity Offset Error (Note 2) Gain Error Power-Supply Rejection Ratio Output Noise oltage Output Thermal Noise Deity REFERENCE INL DNL OS GE PSRR Reference Input Range REF Reference Input Resistance R REF MULTIPLYING-MODE PERFORMANCE Reference -3dB Bandwidth Reference Feedthrough Signal-to-Noise Plus Distortion Ratio DIGITAL INPUTS Input High oltage Input Low oltage Input Hysteresis Input Leakage Current Input Capacitance DIGITAL PUTS Output High oltage Output Low oltage SYMBOL SINAD IH IL HYS I IN C IN OH OL CONDITIONS 12 A ±2 B ±4 ±1 ±1 R L = -.6 ±4 R L = 5kΩ f = 1kHz REF =.5p-p + 1.25 DC, slew-rate limited REF = 1.6p-p +.8 DC, f = 1kHz, code = all s REF =.9p-p + 1.25 DC, f = 1kHz, code = FFF hex MIN TYP MAX -1.6 ±8 1 12 2 5-1.4 18 35-84 78 UNITS Bits m µ/ p-p n/ Hz 2.2.8 2 m IN = or.1 ±1 µa 8 pf I SOURCE = 2mA I SINK = 2mA -.5.13.4 kω khz db db 4
Force/See oltage Output ELECTRICAL CHARACTERISTI (continued) ( = +2.7 to +3.6, REF = 1.25, AGND = DGND, FB =, R L = 5kΩ, C L = 1pF referenced to ground, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER DYNAMIC PERFORMANCE oltage Output Slew Rate Output Settling Time Output oltage Swing (Note 3) Current into FB Time Required to Exit Shutdown Digital Feedthrough POWER SUPPLIES Positive Supply oltage Power-Supply Current (Note 4) Shutdown Current (Note 4) TIMING CHARACTERISTI Clock Period Pulse Width High Pulse Width Low SYMBOL SR I DD t CP t CH t CL CONDITIONS.6 /µs To ±.5, from 1m to full-scale 12 µs =, = 5kHz, f = 1kHz, = 3p-p MIN TYP MAX -.1.1 2.7 3.6.26.35 1 1 15 75 75 4 1 UNITS µa µs n-s ma µa / Fall to Rise Setup Time t S 6 Rise to Rise Hold Time t H SDI Setup Time t DS 6 SDI Hold Time t DH Rise to D alid Propagation Delay t DO1 C LOAD = 2pF 2 Fall to D alid Propagation Delay t DO2 C LOAD = 2pF 2 Rise to Fall Delay t 1 Rise to Rise Hold Time t 1 75 Pulse Width High t W 15 Note 1: INL guaranteed between codes 16 and 495. Note 2: Offset is measured at the code that comes closest to 1m. Note 3: Accuracy is better than 1 for = 1m to - 18m. Guaranteed by PSR test on end points. Note 4: R L = open and digital inputs are either or DGND. Note 5: INL guaranteed between codes 32 and 495. 5
Force/See oltage Output / NO-LOAD SUPPLY CURRENT (µa) Typical Operating Characteristics (: = +5, REF = 2.5; : = +3, REF = 1.25; C L = 1pF, FB =, code = FFF hex, T A = +25 C, unless otherwise noted.) 31 3 29 28 27 26 25 24 23 22 21 NO-LOAD SUPPLY CURRENT vs. SUPPLY OLTAGE 4.4 4.6 4.8 5. 5.2 5.4 5.6 SUPPLY OLTAGE () -1 NO-LOAD SUPPLY CURRENT (µa) 266 264 262 26 258 256 254 252 25 248 NO-LOAD SUPPLY CURRENT vs. TEMPERATURE -5-3 -1 1 3 5 7 9 TEMPERATURE ( C) -2 SHUTDOWN SUPPLY CURRENT (µa) 1.4 1.3 1.2 1.1 1..9.8 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE -5-3 -1 1 3 5 7 9 TEMPERATURE ( C) -3 PUT OLTAGE () PUT OLTAGE vs. TEMPERATURE 2.4995 2.49946 2.49942 2.49938-4 PUT OLTAGE () PUT OLTAGE vs. LOAD RESISTANCE 3. 2.5 2. 1.5 1. -5 (5/div) (1/div) DYNAMIC RESPONSE -6 5 2.5 2.49934.5 1m 2.4993-5 -3-1 1 3 5 7 9 TEMPERATURE ( C) 1 1 1k R L (Ω) 1k 1k 2µs/div (5/div) (1/div) DYNAMIC RESPONSE -7 5 2.5 THD + NOISE (db) -78-8 -82-84 -86-88 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -8 / REF (12.5dB/div) REFERENCE FEEDTHROUGH REF = 1.8 DC + 3.6p-p at f = 1kHz toc9 1m -9 2µs/div -92 1 1 1k FREQUENCY (Hz) 1k 1k 2 FREQUENCY (Hz) 1k 6
Force/See oltage Output Typical Operating Characteristics (continued) (: = +5, REF = 2.5; : = +3, REF = 1.25; C L = 1pF, FB =, code = FFF hex, T A = +25 C, unless otherwise noted.) / REF (12.5dB/div) 2 FFT PLOT REF = 2.5 DC + 1.414p-p at f = 1kHz FREQUENCY (Hz) toc1 1k (2/div) (1m/div) MAJOR-CARRY TRANSITION -11 (2m/div) / (5/div) AC-COUPLED DIGITAL FEEDTHROUGH 4/div -12 / NO-LOAD SUPPLY CURRENT (µa) 28 275 27 265 26 255 25 245 24 235 23 GAIN (db) -5-1 -15-2 -25 REFERENCE INPUT FREQUENCY RESPONSE REF =.67p-p + 1.25 DC 5 1 15 2 25 3 NO-LOAD SUPPLY CURRENT vs. SUPPLY OLTAGE FREQUENCY (khz) 2.5 2.6 2.7 2.8 2.9 3. 3.1 3.2 3.3 3.4 3.5 SUPPLY OLTAGE () -15 NO-LOAD SUPPLY CURRENT (µa) 268 266 264 262 26 258 256 254 252-13 (1/div) (1m/div) NO-LOAD SUPPLY CURRENT vs. TEMPERATURE AC-COUPLED -5-3 -1 1 3 5 7 9 TEMPERATURE ( C) 7-16 START-UP GLITCH 5ms/div SHUTDOWN SUPPLY CURRENT (µa).6.58.56.54.52.5.48.46.44-14 SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE -5-3 -1 1 3 5 7 9 TEMPERATURE ( C) -17
Force/See oltage Output / PUT OLTAGE () Typical Operating Characteristics (continued) (: = +5, REF = 2.5; : = +3, REF = 1.25; C L = 1pF, FB =, code = FFF hex, T A = +25 C, unless otherwise noted.) 1.2498 1.2497 1.2496 1.2495 1.2494 1.2493 PUT OLTAGE vs. TEMPERATURE -5-3 -1 1 3 5 7 9 TEMPERATURE ( C) -18 PUT OLTAGE () PUT OLTAGE vs. RESISTANCE LOAD 1.4 1.2 1..8.6.4.2 1 1 1k R L (Ω) 1k -19 1k (3/div) (5m/div) DYNAMIC RESPONSE 2µs/div -2 3 1.25 1m (3/div) DYNAMIC RESPONSE -21 3-72 -74-76 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -22 / REF (12.5dB/div) REFERENCE FEEDTHROUGH REF =.8 DC + 1.6p-p at f = 1kHz toc23 (5m/div) 1.25 THD + NOISE (db) -78-8 -82-84 1m -86 2µs/div -88 1 1 1k FREQUENCY (Hz) 1k 1k 2 FREQUENCY (Hz) 1k FFT PLOT REF = 1.5 DC +.848 p-p at f = 1kHz toc24 (2/div) MAJOR-CARRY TRANSITION /77 toc25 (2/div) DIGITAL FEEDTHROUGH (, ) /77 toc26 / REF (12.5dB/div) (1m/div) (5µ/div) 2 FREQUENCY (Hz) 1k AC-COUPLED 5µs/div AC-COUPLED 2µs/div 8
Force/See oltage Output Typical Operating Characteristics (continued) (: = +5, REF = 2.5; : = +3, REF = 1.25; C L = 1pF, FB =, code = FFF hex, T A = +25 C, unless otherwise noted.) GAIN (db) -5-1 -15-2 -25 REFERENCE INPUT FREQUENCY RESPONSE REF =.67p-p + 1.25 DC 5 1 15 2 25 3 FREQUENCY (khz) -27 (1/div) (1m/div) AC-COUPLED START-UP GLITCH 5ms/div -28 / PIN 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 NAME FB RS PDL CLR DGND D UPO SHDN AGND REF N.C. Feedback Input FUNCTION oltage Output. High impedance in shutdown. Output voltage is limited to. Pin Description Reset Mode Select (digital input). Connect to to select midscale reset output value. Connect to DGND to select reset output value. Power-Down Lockout (digital input). Connect to to allow shutdown. Connect to DGND to disable shutdown. Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS. Chip-Select Input (digital input). is ignored when is high. Serial-Data Input (digital input). Data is clocked in on the rising edge of. Serial Clock Input (digital input) Digital Ground Serial-Data Output User-Programmable Output. State is set by the serial input. Shutdown (digital input). Pulling SHDN high when PDL = places the chip in shutdown with a maximum shutdown current of 1µA. Analog Ground Reference Input. Maximum REF is - 1.4. No Connect Positive Supply. Bypass to AGND with a 4.7µF capacitor in parallel with a.1µf capacitor. 9
Force/See oltage Output / Detailed Description The / 12-bit, serial, voltage-output DACs operate with a 3-wire serial interface. These devices include a 16-bit shift register and a doublebuffered input composed of an input register and a DAC register (see Functional Diagram). In addition, the negative terminal of the output amplifier is available. The DACs are designed with an inverted R-2R ladder network (Figure 1) that produces a weighted voltage proportional to the reference voltage. Reference Inputs The reference input accepts both AC and DC values with a voltage range extending from to DD - 1.4. The following equation represents the resulting output voltage: = REF N GAIN 496 where N is the numeric value of the DAC s binary input code ( to 495), REF is the reference voltage, and Gain is the externally set voltage gain. The maximum output voltage is DD. The reference pin has a minimum impedance of 18kΩ and is code dependent. Output Amplifier The / s DAC output is internally buffered by a precision amplifier with a typical slew rate of.6/µs. Access to the output amplifier s inverting input provides flexibility in output gain setting and signal conditioning (see Applicatio Information). The output amplifier settles to ±.5 from a full-scale traition within 12µs, when loaded with 5kΩ in parallel with 1pF. Loads less than 2kΩ degrade performance. Shutdown Mode The / feature a software- and hardware-programmable shutdown mode that reduces the typical supply current to 1µA. Enter shutdown by writing the appropriate input-control word as shown in Table 1 or by using the hardware shutdown function. In shutdown mode, the reference input and the amplifier output become high impedance and the serial interface remai active. Data in the input register is saved, allowing the / to recall the prior output state when returning to normal operation. Exit shutdown by reloading the DAC register from the shift register, by simultaneously loading the input and DAC registers, or by toggling PDL. When returning from shutdown, wait 4µs for the output to settle. REF AGND SHOWN FOR ALL 1s ON DAC R R R 2R 2R 2R 2R 2R Figure 1. Simplified DAC Circuit Diagram Power-Down Lockout Power-down lockout disables the software/hardware shutdown mode. A high-to-low traition on PDL brings the device out of shutdown, returning the output to its previous state. Shutdown Pulling SHDN high while PDL is high places the / in shutdown. Pulling SHDN low does not take the device out of shutdown. A high-to-low traition on PDL or an appropriate command from the serial data line (see Table 1 for commands) is required to exit shutdown. Serial Interface The 3-wire serial interface is compatible with SPI, QSPI (Figure 2), and MICROWIRE (Figure 3) interface standards. The 16-bit serial input word coists of two control bits, 12 bits of data (MSB to ), and two sub-bits. The control bits determine the / s respoe as outlined in Table 1. The digital inputs are double buffered, which allows any of the following: Loading the input register without updating the DAC register Updating the DAC register from the input register Updating the input and DAC registers simultaneously. MSB FB 1
Force/See oltage Output The / accept one 16-bit packet or two 8-bit packets sent while remai low. The devices allow the following to be configured: Clock edge on which serial data output (D) is clocked out State of the user-programmable logic output Reset state. Specific commands for setting these are shown in Table 1. Table 1. Serial-Interface Programming Commands C1 1 C 1 16-BIT SERIAL WORD D11...D 12-bit DAC data 12-bit DAC data xxxx xxxx xxxx 1 1 x x xxxx xxxx 1 1 1 x x xxxx xxxx 1 1 1 x xxxx xxxx 1 1 1 1 x xxxx xxxx 1 1 1 1 x xxxx xxxx S1, S xx xx xx xx xx xx 1 1 1 1 1 x xxxx xxxx xx The general timing diagram in Figure 4 illustrates how the / acquire data. must go low at least ts before the rising edge of the serial clock (). With low, data is clocked into the register on the rising edge of. The maximum serial clock frequency guaranteed for proper operation is 1MHz for the and 6MHz for the. See Figure 5 for a detailed timing diagram of the serial interface. FUNCTION Load input register; DAC registers are unchanged. Load input register; DAC registers are updated (start up DAC with new data). Update DAC register from input register (start up DAC with data previously stored in the input registers). No operation (NOP). Shut down DAC (provided PDL = 1). UPO goes low (default). UPO goes high. Mode 1, D clocked out on s rising edge. Mode, D clocked out on s falling edge (default). / +5 SS MOSI SK SCK MICROWIRE PORT SO SPI/QSPI PORT I/O I/O CPOL =, CPHA = CPOL =, CPHA = Figure 2. Connectio for SPI/QSPI Standards Figure 3. Connectio for MICROWIRE 11
Force/See oltage Output / Figure 4. Serial-Interface Timing Diagram C2 1 C1 8 9 16 C D9 D8 D7 D6 D5 D4 D3 D2 D1 D S2 S1 t W S COMMAND EXECUTED t O t S t H t 1 t CH t CL t CP t DS t D1 t D2 t DH D Figure 5. Detailed Serial-Interface Timing Diagram Serial-Data Output (D) The serial-data output (D) is the internal shift register s output and allows for daisy-chaining of multiple devices as well as data readback (see Applicatio Information). By default upon start-up, data shifts out of D on the serial clock s rising edge (Mode ) and provides a lag of 16 clock cycles, thus maintaining SPI, QSPI, and MICROWIRE compatibility. However, if the device is programmed for Mode 1, then the output data lags by 16.5 clock cycles and is clocked out on the serial clock s rising edge. During shutdown, D retai its last digital state prior to shutdown. When CLR is pulled low, UPO will reset to its programmed default state. See Table 1 for specific commands to control the UPO. Reset (RS) and Clear (CLR) The / offers a clear pin (CLR) which resets the output voltage. If RST = DGND, then CLR resets the output voltage to the minimum voltage ( if no offset is introduced). If RST =, then CLR resets the output voltage to midscale. In either case, CLR will reset UPO to its programmed default state. User-Programmable Logic Output (UPO) The UPO allows control of an external device through the serial interface, thereby reducing the number of microcontroller I/O pi required. During power-down, this output will retain its digital state prior to shutdown. 12
Force/See oltage Output Applicatio Information Unipolar Output Figure 6 shows the / configured for unipolar, rail-to-rail operation with a gain of +2/. Table 2 lists the codes for unipolar output voltages. The output voltage is limited to DD. Bipolar Output Figure 7 shows the / configured for bipolar output operation. The output voltage is given by the following equation (FB = ): 2N = REF 1 496 where N represents the numeric value of the DAC s binary input code and REF is the voltage of the external reference. Table 3 shows digital codes and the corresponding output voltage for Figure 7 s circuit. Daisy-Chaining Devices The serial data output pin (D) allows multiple /s to be daisy-chained together as shown in Figure 8. The advantage of this is that only two lines are needed to control all of the DACs on the line. The disadvantage is that it takes n commands to program the DACs. Figure 9 shows several / s sharing one common signal line. In this configuration the data bus is common to all devices; however, more I/O lines are required because each device needs a dedicated line. The advantage of this configuration is that only one command is needed to program any DAC. / REF +5/+3.3 FB 1k REF 1k +5/+3.3 FB + 1k DAC 1k DAC - GND GND R1 = R2 = 1kΩ ±.1% Figure 6. Unipolar Output Circuit (Rail-to-Rail) Figure 7. Bipolar Output Circuit Table 2. Unipolar Code Table (Circuit of Figure 6) DAC CONTENTS MSB 11 1111 1111 11 () 2 REF (495/496) 1 1 () 2 REF (249/496) 1 () 1 1111 1111 11 () 1 () () ANALOG PUT 2 REF (248/496) 2 REF (247/496) 2 REF (1/496) Table 3. Bipolar Code Table (Circuit of Figure 7) DAC CONTENTS MSB 11 1111 1111 11 () ANALOG PUT + REF [(2 495/496) - 1] 1 1 () + REF [(2 249/496) - 1] 1 () 1 1111 1111 11 () 1 () () + REF [(2 248/496) - 1] + REF [(2 247/496) - 1] + REF [(2 1/496) - 1] - REF 13
Force/See oltage Output / D D D TO OTHER SERIAL DEICES Figure 8. Daisy-Chaining /s 1 2 3 TO OTHER SERIAL DEICES Figure 9. Multiple /s Sharing Common and Lines 14
Force/See oltage Output Using an AC Reference The / accept reference voltages containing AC components, as long as the reference voltage remai between and DD - 1.4. Figure 1 shows a technique for applying a sine-wave signal to REF. The reference voltage must remain above AGND. Digitally Programmable Current Source The circuit of Figure 11 places an NPN traistor (2N394 or similar) within the op amp feedback loop to implement a digitally programmable, unidirectional current source. The output current is calculated with the following equation: I = REF N R 496 where N is the numeric value of the DAC s binary input code and R is the see resistor shown in Figure 11. Power-Supply and Layout Coideratio Wire-wrap boards are not recommended. For optimum system performance, use printed circuit boards with separate analog and digital ground planes. Connect the two ground planes together at the low-impedance power-supply source. Connect DGND and AGND pi together at the IC. The best ground connection is achieved by connecting the DAC s DGND and AGND pi together and connecting that point to the system analog ground plane. If the DAC s DGND is connected to the system digital ground, digital noise may infiltrate the DAC s analog portion. Bypass the power supply with a 4.7µF capacitor in parallel with a.1µf capacitor to AGND. Minimize capacitor lead lengths to reduce inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. In order to maintain INL and DNL performance, as well as gain drift, it is extremely important to provide the lowest possible reference output impedance at the DAC reference input pin. INL degrades if the series resistance on the REF pin exceeds.1ω. The same coideration must be made for the AGND pin. / +5/ +3.3 AC REFERENCE INPUT 5mp-p R 1 +5/+3.3 MAX495 +5/+3.3 REF DAC L I R 1 REF 2N394 DAC GND FB R GND Figure 1. AC Reference Input Circuit Figure 11. Digitally Programmable Current Source 15
Force/See oltage Output / PDL SHDN RS CLR SERIAL CONTROL INPUT REGISTER 16-BIT SHIFT REGISTER DECODE CONTROL Functional Diagram DAC REGISTER AGND DGND DAC REF LOGIC PUT D UPO FB TRANSISTOR COUNT: 3457 Chip Information Package Information QSOP.EPS Maxim cannot assume respoibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licees are implied. Maxim reserves the right to change the circuitry and specificatio without notice at any time. 16 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.