CMOS Micro-Power Comparator plus Voltage Follower

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Freescale Semiconductor Technical Data Rev 2, 05/2005 CMOS Micro-Power Comparator plus Voltage Follower The is an analog building block consisting of a very-high input impedance comparator. The voltage follower allows monitoring the noninverting input of the comparator without loading. Four enhancement-mode MOSFETs are also included on chip. These FETs can be externally configured as open-drain or totem-pole outputs. The drains have on-chip static-protecting diodes. Therefore, the output voltage must be maintained between V SS and V DD. The chip requires one external component. A 3.9 MΩ ±10% resistor must be connected from the R bias pin to V DD. This circuit is designed to operate in smoke detector systems that comply with UL217 and UL268 specifications. Features Applications: Pulse Shapers Line-Powered Smoke Detectors Threshold Detectors Liquid/Moisture Low-Battery Detectors CO Detector and Micro Interface Operating Voltage Range: 3.5 to 14 V Operating Temperature Range: -30 to 70 C Input Current (IN + Pin): ±1 pa @ 25 C (DIP Only) Quiescent Current: 10 μa @ 25 C Electrostatic Discharge (ESD) Protection Circuitry on All Pins Device ORDERING INFORMATION Temperature Range Case No. Package P -30 to 70 C 648-08 Plastic Dip CMOS MICRO-POWER COMPARATOR PLUS VOLTAGE FOLLOWER V DD Comp OUT IN A IN B OUT A OUT B IN C OUT C1 P SUFFIX PLASTIC DIP CASE 648-08 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC IN + NC Buff OUT IN R bias V SS OUT C2 Figure 1. Pin Connections Freescale Semiconductor, Inc., 2005. All rights reserved.

IN + IN R bias 15 12 11 + Comp Bias Ckt 2 Comp OUT IN A 3 5 6 OUT A OUT B IN C 7 9 8 OUT C2 OUT C1 + Buff Table 1. Maximum Ratings (1) (Voltages Referenced to V SS ) 13 Buff OUT IN B 4 Figure 2. Block Diagram Pin 1 = V DD Pin 10 = V SS Pin 14, 16 = No Connection Rating Symbol Value Unit DC Supply Voltage V DD -0.5 to +14 V DC Input Voltage V in -0.5 to V DD +0.5 V DC Output Voltage V out -0.5 to V DD +0.5 V DC Input Current, Except IN + I in ±10 ma DC Output Current, IN + I in ±1.0 ma DC Output Current, per Pin I out ±25 ma DC Supply Current, V DD and V SS Pins I DD ±50 ma Power Dissipation, per Package P D 500 mw Storage Temperature T stg -65 to + 150 C Lead Temperature (10-Second Soldering) T L 260 C 1. Maximum Ratings are those values beyond which damage to the device may occur. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. 2 Freescale Semiconductor

Table 2. Electrical Characteristics (Voltages Referenced to V SS, R bias = 3.9 MΩ to V DD, T A = -30 to 70 C Unless Otherwise Indicated) Characteristic Symbol Test Condition V DD V DC Guaranteed Limit Unit Power Supply Voltage Range V DD 3.5 to 14.0 V Maximum Low-Level Input Voltage, MOSFETs Wired as Inverters; i.e., IN A tied to IN B, OUT A to OUT B, OUT C1 to OUT C2 Minimum High-Level Input voltage, MOSFETs Wired as Inverters; i.e., IN A tied to IN B, OUT A to OUT B, OUT C1 to OUT C2 V IL V out = 9.0 V, II out I <1 μa 10.0 2.0 V V IH V out = 1.0 V, II out I <1 μa 10.0 8.0 V Comparator Input Offset Voltage V IO T A = 25 C, Over Common Mode Range 10.0 ±50 mv T A = 0 to 50 C, Over Common Mode Range Comparator Common Mode Voltage Range V CM 3.5 to 14.0 Maximum Low-Level Comparator Output Voltage V OL IN +: V in = V SS, IN : V in = V DD, I out = 30 μa Minimum High-Level Comparator Output Voltage V OH IN +: V in = V DD, IN : V in = V SS, I out = -30 μa Buffer Amp Output Offset Voltage V OO R load = 10 MΩ to V DD or V SS, Over Common Mode Range Maximum Low-Level Input Voltage, MOSFETs Wired as Inverters; i.e., IN A tied to IN B, OUT A to OUT B, OUT C1 to OUT C2 Minimum High-Level Input Voltage, MOSFETs Wired as Inverters; i.e., IN A tied to IN B, OUT A to OUT B, OUT C1 to OUT C2 Maximum Input Leakage Current IN + (DIP Only) IN + (DIP Only) 3.5 to 14.0 ±75 0.7 to V DD 1.5 V 10.0 0.5 V 10.0 9.5 V ±100 mv V OL OUT C1, OUT C2, I out = 1.1 ma 10.0 0.5 V OUT A, OUT B, I out = 270 μa 10.0 0.5 V V OH OUT C1, OUT C2, I out = -1.1 ma 10.0 9.5 V I in OUT A, OUT B, I out = 270 μa 10.0 9.5 V T A = 25 C, 40% R.H., 10.0 ±1.0 pa V in = V SS or V DD T A = 50 C, 10.0 ±6.0 V in = V SS or V DD IN + (SOG), IN A, IN B, IN C, IN V in = V SS or V DD 10.0 ±40 na Maximum Off-State MOSFET Leakage Current I OZ IN A, IN C: V in = V DD, OUT A, OUT C2: V out = V SS or V DD 10.0 ±100 na IN B, IN C: V in = V SS, 10.0 ±100 OUT B, OUT C1: V out = V SS or V DD Maximum Quiescent Current I DD T A = 25 C IN A, IN B, IN C: V in = V SS or V DD, IV IN + V IN I = 100 mv I out = 0 μa Maximum Input Capacitance IN + Other Inputs C in f = 1 khz 10.0 10 μa 5.0 15 pf Freescale Semiconductor 3

APPLICATIONS INFORMATION V + V + 1 V DD NC 16 R1 2 COMP OUT IN + 15 Low-battery Indicator R5 6.8 k D2 3 4 5 6 7 8 IN A IN B OUT A OUT B IN C OUT C1 NC BUFF OUT IN R BIAS V SS OUT C2 14 13 12 11 10 9 R2 R4 3.9 M V + R3 D1 OUTPUT High = Battery Low Low = Battery Ok NOTE: IN + and IN have very high input impedance. Interconnect to these pins should be as short as possible. Figure 3. Low-Battery Detector EXAMPLE VALUES Near the switchpoint, the comparator output in the circuit of Figure 3. may chatter or oscillate. This oscillation appears on the signal labelled OUTPUT. In some cases, the oscillation in the transition region will not cause problems. For example, an MPU reading OUTPUT could sample the signal two or three times to ensure a solid level is attained. But, in a low battery detector, this probably is not necessary. To eliminate comparator chatter, hysteresis can be added as shown in Figure 4.. The circuit of Figure 4. requires slightly more operating current than the Figure 3. arrangement. R1 R2 R3 Nominal Tip Point 470 kω 1.3 MΩ 20 kω 4.08 V 820 kω 1.2 MΩ 39 kω 5.05 V 1.2 MΩ 1.2 MΩ 62 kω 6.00 V 12 2 R6 15 R7 Figure 4. Adding Hysteresis 4 Freescale Semiconductor

PACKAGE DIMENSIONS 16 1 8 H G F 9 D 16 PL B S C K -A- -T- 0.25 (0.010) M T A SEATING PLANE M STYLE 1: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. CATHODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE 15. ANODE 16. ANODE J L M STYLE 2: PIN 1. COMMON DRAIN 2. COMMON DRAIN 3. COMMON DRAIN 4. COMMON DRAIN 5. COMMON DRAIN 6. COMMON DRAIN 7. COMMON DRAIN 8. COMMON DRAIN 9. GATE 10. SOURCE 11. GATE 12. SOURCE 13. GATE 14. SOURCE 15. GATE 16. SOURCE CASE 648-08 ISSUE R 16-LEAD PLASTIC DIP NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. DIMENSION B DOES NOT INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 Freescale Semiconductor 5

NOTES 6 Freescale Semiconductor

NOTES Freescale Semiconductor 7

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