Analysis of SiC MOSFETs under Hard and Soft- Switching

Analysis of SiC MOSFETs under Hard and Sof- Swiching M. R. Ahmed, R. Todd and A. J. Forsyh School of Elecrical and Elecronic Engineering, Power Conversion Group The Universiy of Mancheser Mancheser, U.K. md.rishad.ahmed@posgrad.mancheser.ac.uk Absrac Analyical models for hard-swiching and sofswiching SiC MOSFETs and heir experimenal validaion are described in his paper. The models include he high frequency parasiic componens in he circui and enable very fas, accurae simulaion of he swiching behaviour of SiC MOSFET using only daashee parameers. The much higher swiching speed of SiC devices over Si counerpars necessiaes a clear deailed analysis. Each swiching ransien was divided ino four disinc sub-periods and heir respecive equivalen circuis were solved o approximae he circui sae variables. Nonlineariies in he juncion capaciances of SiC devices were considered in he model. Analyical modelling resuls were close o he LTspice simulaion resuls wih a hreefold reducion in he simulaion ime. The effec of snubber capaciors on he sof-swiching waveforms is also explained analyically and validaed experimenally, which enables he analyical model o be used o evaluae fuure sofswiching soluions. I was found ha he snubber branch can significanly reduce he urn off ringing of he SiC MOSFET in addiion o he reducion of swiching losses. Keywords SiC MOSFET analyical model; swiching ransiens; snubber capacior; parasiic effec; sof-swiching I. INTRODUCTION Silicon-based power swiching devices are now approaching heir performance limis due o he inheren maerial properies []. Silicon carbide (SiC) is a widebandgap semiconducor, which compared o silicon has superior physical and elecrical properies especially a high emperaure [, 2]. SiC power devices are considered o be one of he enabling echnologies for fuure power dense DC- DC converers, as hey can be operaed a very high swiching frequencies which reduces he size of he magneic componens. The fas swiching ransiions of hese devices do however creae design issues for he converer, including parasiic curren and volage oscillaions, elecromagneic inerference (EMI) effecs and conrol complexiies. To gain he full benefi from a SiC power dense converer requires deailed undersanding of hese devices. To undersand he SiC MOSFET saic and dynamic behaviour, several modelling approaches have been proposed, including semiconducor physics models [3, 4] and behavioural models [5-7]. Mos of he models are complex or poorly incorporae he circui parasiic componens, and so produce inaccurae circui waveforms. Analyical modelling of he swiching ransiens can be a good approach o undersand he swiching behaviour of SiC MOSFETs. The models can hen be exended o incorporae circui parasiics and also sof-swiching of he power devices. For example, [8] showed a simple circui model for he off-sae of a SiC MOSFET o predic he dv/-induced false urn on. However, he modelling of oher swiching ransien saes was no shown. One of he key objecives of his work is o develop an analyical model o evaluae SiC MOSFETs full swiching behaviour. Swiching es resuls of SiC MOSFETs in converer circuis have shown ha heir swiching losses can significanly limi he operaing frequency [9, 0]. Sof swiching echniques can be employed o minimise he swiching losses and a sof-swiched SiC boos converer (2.5 kw, 2 khz) was repored in [] wih an efficiency of around 98 %. However, he impac of he snubber branch on he swiching waveforms needs o be invesigaed o fully evaluae he performance benefis, which is anoher capabiliy of his analyical model. II. OVERVIEW OF SIC MOSFET SWITCHING A. Hard-swiching To invesigae he hard-swiching of a SiC MOSFET, he double-pulse es (DPT) circui shown in Fig. (a) is used. Fig. (b) shows he ideal circui waveforms. Two pulses wih variable wihs are provided a he gae driver inpu as shown in Fig. (a). The firs pulse has a larger wih which deermines he curren rise in he inducor, L shown in Fig. (b). When he curren reaches he desired level, he MOSFET (device under es, ) is urned off and he urn off ransien waveforms can be observed. A his ransien, he load curren commuaes o he Schoky diode from he MOSFET channel. During he off sae of he MOSFET, he inducor curren remains virually consan. Then he smaller wih pulse is applied o he gae driver and he urn on ransien waveforms can be observed a he same curren and volage level of he urn off ransien. Finally, when he smaller pulse finishes, he inducor curren slowly decays in he closed loop i forms wih he Schoky diode. The auhors hank he UK Engineering and Physical Sciences Research Council (EPSRC) for he funding of his projec as par of he Cenre for Power Elecronics. 978--4673-75-3/5/$3.00 205 IEEE

Gae Driver (a) D D2 hun L Turn off (b) Turn on Fig.. (a) Double-pulse es (DPT) circui, (b) eal circui waveforms Fig. 2(a) shows he equivalen DPT circui for he acive region of he MOSFET, when he main volage and curren ransiions occur during urn on. Fig. 2(a) includes all he parasiic componens associaed wih boh he SiC MOSFET and oher circui componens, such as he MOSFET common source inducance, L s, drain lead inducance, L d, gae lead inducance, L g, parasiic capaciances of he MOSFET, diode and load inducor lumped parasiic capaciance, C ak, and he equivalen series resisance of he power loop, R s. Fig. 2(b) shows simplified ransien waveforms for he MOSFET drain o source volage, V ds, drain curren, I d, gae o source volage, V gs, Schoky diode volage, V ak, and he diode curren, I f. Vgg Lg Ls (a) If f() Vgg Vh 0 Vls 2 3 4 Fig. 2. (a) Equivalen circui of DPT during he acive region of SiC MOSFET, (b) DPT waveforms during urn on The V gs increases during 0 - in an exponenial manner as he gae curren charges he MOSFET inpu capaciances, C gs and C gd. V gs reaches he hreshold level, V h a and I d sars o increase. A he same ime, diode curren, I f also sars o fall from he load curren, I dd level and a ime 2, he curren commuaion beween he diode and MOSFET finishes. During his sub-period, - 2, an almos consan volage drop, V ls, happens across, L d and L s, which reduces V ds by V ls from he inpu DC link volage, V dd. A ime 2, I d reaches he load curren level (I dd ), V ds sars o fall as he volage sars o build up across he diode parasiic capacior, C ak. The charging curren of he parasiic capacior increases I d almos linearly unil he diode volage, V ak reaches he level V dd V ls a ime 3. A his poin, V ds reaches is on-sae volage level, V ds(on). Afer 3, I d sars o reduce as he energy in he sray inducance, L d & L s ransfers o he diode capacior. The resonance beween he diode parasiic capacior, C ak and circui sray inducance, L d & L s coninues unil all he resonaing energy is dissipaed by he sray resisance, R s, of (b) If he circui. Finally, once he resonance period is complee, he drain curren is equal o he load curren, I dd, he diode volage, V ak becomes equal o he DC link volage, V dd, and he V gs is equal o he gae supply volage, V gg. The swiching ransien a urn off follows a reverse process o ha seen a urn on. The sub-inervals for urn off are he same as hose a urn on bu occur in he reverse order. B. Sof-swiching To faciliae he sof-swiching es, a differen arrangemen of he DPT circui shown in Fig. 3(a) was used. Firs, a single gae pulse is given o he upper device, Q, so ha he load curren, I L increases in he inducor, L, o he desired level, I dd (Fig. 3(b)). Turning off Q will urn on he body diode of Q2 and I L will sar o decrease because of he reverse volage across he inducor, L. Afer a deaime, a second gae pulse, approximaely double he wih of he firs pulse is applied o he lower device, Q2. This forces he load curren o change direcion and reach I dd. In boh urn on and urn off ransiens he wo snubber capaciors, and C s2, charge and discharge in a lossless manner o enable zero-volage swiching of boh devices. Gae Driver Gae Driver R g R g2 (a) Q2 V gs2 Q V gs V dd I L D D2 R shun I d+i c C s2 L V ds2 V gs V gs2 I L I dd -I dd V ds2 V dd V dd /2 urn on (b) urn off Fig. 3. (a) DPT for sof-swiching operaion (b) eal circui waveforms Fig. 4(a) shows he equivalen sof-swiching DPT circui a he acive region of he MOSFET during urn off. Here and C s2 are he wo snubber capaciors and I c and I c2 are he currens flowing hrough hese capaciors respecively. L s2 is he parasiic inducance of C s2. The parasiic inducance of is negleced o simplify he analysis as explained laer in Secion III.B. Deailed urn off ransien waveforms are shown in Fig 4 (b). Vs Ic Cs _ f() Ls (a) M Ls2 Vgg Vmil Vh 0ʼ _ Ic ʼ 2ʼ 3ʼ 4ʼ Fig. 4. (a) Equivalen circui of sof-swiching DPT during he acive region of SiC MOSFET, (b) DPT waveforms during urn off The gae o source volage, V gs decreases during 0 - in an exponenial manner as he gae curren discharges he _up (b)

MOSFET inpu capaciances, C gs and C gd. V gs reaches he miller level, V mil a and V ds sars o increase and I d sars o decrease. Due o he snubber capacior, C s2, V ds increases very slowly while I d falls o zero a 2 and V gs reaches is hreshold level, V h. In his sub-period I dd commuaes o he wo snubber capaciors. During he sub-period 2-3 I dd is shared equally by he wo snubber branches. Due o he parasiic inducance in he curren pahs, boh I c and I c2 will be oscillaory. Towards he end of he 2-3 sub-period V ds will reach V dd and he upper device will sar o conduc (I d_up ) erminaing he snubber branch currens. Afer 3, he circui capaciance and inducances will coninue o resonae unil a seady sae is reached when he upper device curren, I d_up equals he load curren, I dd, I c and I c2 becomes zero, and V gs equals V ggl. III. MODELLING OF SIC MOSFET SWITCHING TRANSIENTS Analyical modelling of SiC MOSFET urn on and urn off ransiens requires he soluion of four equivalen circuis corresponding o he four disinc sages of boh ransiens. The modelling approach is similar o he published Si- MOSFET analyical models [2, 3], bu he difference is he incorporaion of he major circui parasiic componens in all of he ransien sages. Also no assumpions are used in he model o predic volage ransiions in he equivalen circuis. ode45 differenial equaion solver was used in MATLAB o solve he sae equaions of each sub-period of he analyical models. For each sub-period, he sae variables were solved, and he final values were he iniial condiion for he nex sub-period. A. Hard swiching The equivalen circuis for urn on and urn off ransien saes are shown in Fig. 5 (derived from he DPT circui in Fig. (a)). Here, L d is he sum of inducances of he MOSFET drain lead, L drain, PCB curren pahs, L pcb, diode leads, L lead, and curren shun resisor, L shun. Four sae variables, V gs, V ds, I d and İ d (rae of change of drain curren), were considered and are solved using four sae space equaions. A sep gae pulse from V ggl o V gg is used o iniiae he urn on ransien. The oher wo inpus are supply volage, V dd and load curren, I dd. The four sub-periods during he urn on ransien correspond o (i) urn on delay, (ii) drain curren rise, (iii) drain o source volage fall and (iv) ringing sages. The gae inducance, L g was negleced in he proposed model assuming gae curren, I g, is much smaller han he drain curren, I d, and he validiy of his assumpion was confirmed by he experimenal measuremens in Secion IV. Turn on ransien model A sep gae pulse from V ggl o V gg iniiaes urn on which drives he soluion of he urn on ransien model (V ggl <0). Sub-period : ( 0 - ) (urn on delay, d(on) ) Afer he gae pulse is applied, he gae curren charges he MOSFET inpu capaciors C gs and C gd. The MOSFET says off unil V gs reaches V h and he load curren, I dd circulaes hrough he Schoky diode. The drain curren is zero and he drain o source volage is equal o he DC link volage, V dd in his sub-period. Therefore, he only sae variable o be solved in his sub-period is V gs. Afer solving equaions ()-(3) using V g_in = V gg and he iniial condiion, V gs (0) = V ggl, an expression for gae o source volage, V gs can be found (4). R g I g () = V g_in V gs () L s di d() I g () = C gs dv gs () + C gd dv gd () () (2) V gs () = V gd () + V ds () (3) V gs () = V gg + (V ggl V gg ) [exp ( )] (4) where, I d () = I DD and C iss = C gs + C gd. The urn on delay, 0, (5), is he ime required for V gs o reach V h from V ggl. 0 = ln( V gg V h V gg V ggl ) (5) Sub-period 2: ( - 2 ) (curren rise ime, ir ) Curren commuaion beween he diode and MOSFET happens in his sage. As he MOSFET works in he sauraion region is channel curren will be direcly proporional o V gs. V ds decreases in his sage because of he di/ induced volages across L s and L d as shown in (6). If If If If D D C C C C f() f() Rds(on) (on) Gae driver pulse Gae driver pulse Gae driver pulse Gae driver pulse Ls Ls Ls Ls 0-2 2 3 Turn on sub-period 2 Turn off sub-period 3 Turn on sub-period Turn off sub-period 4 Turn on sub-period 3 Turn off sub-period 2 3 4 Turn on sub-period 4 Turn off sub-period Fig. 5. Equivalen circuis for urn on and urn off sub-periods corresponding o he hard-swiching DPT circui

V ds () = V dd (L s + L d ) di d () R s I d () (6) The drain curren can be found by adding he channel curren o he MOSFET oupu capacior discharge curren as shown in (7) where = C ds + C gd. I d () = g m [V gs () V h ] + dv ds () The sae equaions (A) for his sub-period are derived using ()-(3) and (6)-(7) and are shown in he Appendix. The curren rise ime, 2 is he ime required for V gs o reach V mil from V h, where, V mil = I dd g m + V h and g m is he ransconducance of he MOSFET. The drain curren will reach he load curren level by he end of his sub-period. Sub-period 3: ( 2-3 ) (Volage fall ime, vf ) The volage across he Schoky diode capacior, V ak is expressed as (8) and V ds can be expressed as (9) for his subperiod. The sae equaions (A2) for his sub-period are derived using ()-(3), (7) and (8)-(9) and are shown in he Appendix. dv ak () (7) = C ak (I d () I dd ) (8) V ds () = V dd (L s + L d ) di d () V ak () R s I d () (9) The volage fall ime, 3 2 is he ime required for V ds o reach V ds(on) from V ds ( 2 ). Sub-period 4: ( 3-4 ) (Ringing period) As he MOSFET says in he ohmic region, V ds can be considered consan, V ds(on). The sae equaions (A3) for his sub-period are derived using ()-(3), (8) and (9) and are shown in he Appendix. The ime for his sub-period, 4 3 is approximaed by he ime required for V gs o reach V gg from V gs ( 3 ). Model implemenaion Fig. 6 shows a summary of he urn on ransien model implemenaion process in MATLAB. The sae equaions are solved using he parameers and parasiic values of he DPT circui shown in Table I (Secion III.C). When solving (A2) for sub-period 3, he nonlineariies in juncion capaciances were considered. These nonlinear volage dependen parasiic capaciances of he MOSFET (C gd, C iss and ) and he Schoky diodes (C ak ) were modelled by fiing heir daashee curves o (0) which is based on he equaion for low volage silicon MOSFETs [2]. C 0v and C hv are he low volage and high volage capaciance values used o calculae he curve fiing coefficiens x and C j. The C hv erm has o be included o he equaion o fi he variable capaciance curve for he wider volage range of he 200V raed SiC MOSFETs. C = C0v +Vx C j + c hv (0) The linear sae equaions (A2) were solved in a loop wih differen juncion capaciance values updaing afer every en ime seps unil V ds reaches V ds(on). Then, (A3) is solved for sub-period 4, using low volage juncion capaciance values, unil V gs reaches V gg when he simulaion finally ends. Take inpus from Table I. Fix ime sep. Solve V gs using (4). V ds, I d and İ d fixed 2. Solve (A) using fixed high volage capaciance values 3. Solve (A2) using variable juncion capaciances (0), which updae every 0 ime seps 4. Solve (A3) using low volage capaciance values and R L. V ds fixed V gs, V ds, I d, İ d V gs2, V ds2, I d2, İ d2 V gs3, V ds3, I d3, İ d3 V gs4, V ds4, I d4, İ d4 Fig. 6. Flow char of urn on ransien implemenaion Turn off ransien model V gs V ds I d İ d A sep gae pulse from V gg o V ggl iniiaes urn off which drives he soluion of he urn off ransien model. The four urn-off ransien sub-periods in Fig. 5 are essenially a mirror image of he urn-on ransien sub-periods, and so, he sae equaions can be derived in a similar manner. Sub-period : ( 4-5 ) (urn off delay, d(off) ) Afer he negaive gae pulse is applied, he MOSFET inpu capaciors C gs and C gd begin o discharge. The MOSFET says in he ohmic region unil V gs reaches V mil. The load curren, I dd goes hrough he MOSFET channel, so, V ds can be considered consan, V ds(on). Afer solving ()-(3) using V g_in = V ggl and he iniial condiion, V gs (0) = V gg, he gae o source volage can be found (). V gs () = V ggl + (V gg V ggl ) [exp ( )] () Turn off delay, 5 4 is he ime required for V gs o reach V mil from V gg which can be found by solving () giving (2). 5 4 = ln( V mil V ggl V gg V ggl ) (2) Sub-period 2: ( 5-6 ) (volage rise ime, vr ) The sae equaions for his sub-period will be exacly he same as (A2). 6 5 is he ime required for V ak o reach zero from V dd. Sub-period 3: ( 6-7 ) (Curren fall ime, if ) The sae equaions for his sub-period will be exacly he same as (A). 7 6 is he ime required for V gs o reach V h from V gs ( 6 ). Sub-period 4: ( 7-8 ) (Ringing period) In his sub-period he MOSFET is in he cu-off region and he MOSFET oupu capacior, resonaes wih he sray inducances of he circui. So, he drain curren can be expressed as (3). The sae equaions (A4) for his sub-

Ic Ic Ic Ic Vs Cs Vs Cs Vs Cs Vs Cs Rd Rds(on) (on) f() Ls Ls2 Ls M M M Ls2 Ls Ls2 Ls Ls2 Turn off sub-period ʼ Turn off sub-period 2ʼ Turn off sub-period 3ʼ Fig. 7. Equivalen circuis for ZVS urn off sages of he lower device () Turn off sub-period 4ʼ period are derived using ()-(3), (6) and (3) and are shown in he Appendix. I d () = dv ds () (3) The ime for his sub-period, 8 7 is approximaed by he ime required for V gs o reach V ggl from V h. B. Sof-swiching To model he sof-swiching ransien for he SiC MOSFET only he urn off ransien of he lower device () in Fig. 2(a) was modelled analyically because his ransien also corresponds o urn on of he upper device. Parasiic componens relaed o he upper device are negleced in he model o reduce he complexiy. The validiy of his assumpion was confirmed by LTspice simulaions. Similar o hard-swiching, he sof-swiching model is based on he soluion of four equivalen circuis shown in Fig. 7, for he four disinc sages of he ransien, (i) urn off delay, (ii) drain curren fall, (iii) drain o source volage rise and (iv) ringing periods. Two addiional sae variables, snubber capacior curren, I c2 and is rae of change, İ c2 were considered in addiion o he oher four sae variables, V gs, V ds, I d and İ d. The resuling sae space equaions are solved and he final value from a sub-period forms he iniial condiion for he nex sub-period. In Fig. 7, L d is he MOSFET drain lead inducance, L drain. L pcb, L lead, and L shun are summed ogeher in L sh. The coupling facor, k beween he snubber parasiic inducance, L s2 and MOSFET common source inducance, L s is approximaed from (4)-(5). In he expression of muual inducance, M (nh) beween wo parallel curren conducing pahs (4), l a is he average lengh of he pahs in mm and d is he disance beween he pahs in mm [4]. M = 0.2l a (ln ( 2l a d ) + d l a ) (4) M k = (5) L s2 L s Sub-period : ( 0 - ) (urn off delay) Exacly same as he urn off delay sub-period of he hardswiching model ()-(2). Sub-period 2 : ( - 2 ) (Curren fall period) The muual inducance, M, beween he snubber circui parasiic inducor, L s2 and he common source inducor, L s is considered here when deriving he sae equaions. The sysem of sae equaions (A5) for his sub-period can be formed from (2)-(3), (7), and (6)-(20). Here, V s and V s2 are he volages across he snubber capaciors. 2 is he ime required for V gs o reach V h from V mil. R g I g () = V g_in V gs () L di d () s M di c2 () V ds () = V dd V s () R s (I d () + I c2 ()) M di c2 () dv s () dv s2 () = (6) (L s + L d ) di d () L d sh (I d () + I c2 ()) (7) (I d () + I c2 () I dd ) (8) d = L 2 I c2 () s2 + I 2 C c2 () + M d2 I d () (9) s2 2 V s () + V s2 () = V dd R s (I d () + I c2 ()) L d sh (I d () + I c2 ()) (20) Sub-period 3 : ( 2-3 ) (Volage rise period) The sae equaions (A6) for his sub-period are derived using (2)-(3), (3), and (6)-(20). 3 2 is he ime required for V s o reach zero from V s ( 2 ). Sub-period 4 : ( 3-4 ) (Ringing period) Because of he diode on sae resisance, R d, one addiional sae variable V s has o be solved in his subperiod. The sae equaions (A7) are derived using (2)-(3), (3), (6)-(7), (9)-(20) and (2). 4 3 is approximaed by he ime required for V gs o reach V ggl from V gs ( 3 ). dv s () = (I C d () + I c2 () V s() I s R dd ) (2) d C. Analyical model implemenaion The analyical models were implemened in MATLAB using daashee informaion of Cree SiC MOSFET, M008020D, and differen SiC Schoky diodes, C4D020D and SCS230KE2. All oher parameers including he power circui parasiic values (measured using

a precision impedance analyser, Agilen 4294A), MOSFET and Schoky diode package parasiic values (aken from respecive daashees and applicaion noes) used for implemening he analyical model are shown in Table I. These values correspond o he experimenal seup of he DPT. TABLE I. PARAMETERS AND PARASITIC VALUES Secion Parameer Value Parameer Value V dd 600 V I dd 8A-25A R shun(dc) 0 mω L pcb 20 nh Power circui R shun(ac) 53 mω Inducor, L 462 µh R pcb(ac) 00 mω C L (AC) 6.5 pf L shun 8 nh R L (AC) 6.8 Ω R leads (AC) 70 mω Gae drive V gg 20 V V ggl 4 V circui R g.27 Ω R ds(on) (25 C) 80 mω g m (25 C) 8. S L SiC MOSFET s 0.5 nh C iss_low volage 500 pf L M008020D drain 7.5 nh C iss_high volage 00 pf C gd_low volage 370 pf _low volage 000 pf C gd_high volage 7.5 pf _high volage 80 pf Cree Diode, L lead 2.5 nh R d (25 C) 55 mω C4D020D ROHM Diode, SCS230KE2 Snubber circui C ak_low volage 390 pf C ak_high volage 20 pf L lead 2.5 nh R d (25 C) 5 mω C ak_low volage 790 pf C ak_high volage 63 pf, C s2 nf L s2 2 nh k 0.95 The sray resisance of he power loop, R s is he sum of he resisances of curren shun resisor, R shun, PCB curren pahs, R PCB, MOSFET and diode resisors (R ds(on), R d and R leads ). The iner-winding parasiic capaciance of he load inducor, C L and is high frequency AC resisance, R L are also included in he model in he appropriae sub-periods. IV. SIMULATION AND EXPERIMENTAL RESULTS OF HARD- SWITCHING A 600V, 25A double-pulse es (DPT) circui shown in Fig. 8 was designed o examine he swiching characerisics of second generaion Cree M008020D SiC MOSFETs. Cree SiC MOSFET gae driver circui, CRD-00 was used o drive he MOSFETs. T&M Research s high-bandwih curren shun resisor, SDN-44-0 was used o accuraely measure he drain / source curren. The connecion of he load inducor can be changed o enable boh hard-swiching and sof-swiching ess o be performed using he same circui for fair comparison. The DPT circuis were also simulaed in LTspice using he SPICE models of he SiC MOSFET and Schoky diodes. A ime sep of 0.0ns was seleced for boh he analyical model implemenaion and he LTspice simulaion as SiC MOSFET swiching ransien imes are of ens of ns. Experimenal, analyical and LTspice simulaion hardswiching ransiens for 600V 20A and 600V 3A DPT operaion are shown in Fig. 9-2 for wo differen Schoky diodes. The V ds and V gs waveforms include he volages across he device package inducances. Swiching losses from differen experimens are summarised in Table II. I is eviden ha compared o he LTspice models he analyical models gave a beer swiching loss esimaion. The maximum error from analyical models was around 6% wih respec o he experimenal resuls (experimens wih he ROHM diode). However, he individual urn on and urn off loss esimaion for he 20A experimens was worse in analyical modelling han LTspice. The reason may be he beer incorporaion of he nonlineariy in device juncion capaciances in he LTspice model which enabled beer approximaion of volage and curren ransiions in 20A experimens shown in Fig. 9-0. Load inducor Gae driver for he upper leg MOSFET Inpu power supply DC link capacior Curren shun resisor Fig. 8. Experimenal seup for DPT ess Also he Cree diode SPICE model gives beer simulaion resuls han he ROHM diode SPICE model. The maximum error in swiching loss esimaion was around 6% and 29% from simulaions wih Cree diode and ROHM diode SPICE models, respecively. However, boh experimenal and LTspice urn off losses include he energy sored in he device oupu capaciance and oher circui sray capaciances, which evenually is dissipaed during he urn on ransien. The analyical model gives a way for calculaing he acual urn on and urn off losses from he modelled channel curren of he MOSFET and V ds. The advanage of he proposed analyical model over he LTspice model is a 3 imes reducion in simulaion ime, a single urn on ransien akes 0.6s o complee on an Inel Core i7 3.4 GHz compuer, and beer incorporaion of he high frequency parasiic componens such as incorporaion of he AC resisance of he load inducor during he urn on ringing sage, sub-period 4. Also he effec of emperaure on he swiching ransiens can be evaluaed easily by changing he emperaure dependen parameers in Table I. However, he modelling of ringing in he differen waveforms is sill limied in boh he analyical and LTspice models. Addiional parasiic elemens such as drain o gae exernal parasiic capaciance may need o be considered for beer modelling of ringing. Condiions 600V 20A wih Cree C4D020D 600V 20A wih ROHM SCS230KE2 600V 3A wih Cree C4D020D 600V 3A wih ROHM SCS230KE2 TABLE II. SWITCHING LOSS COMPARISON Sae Loss (µj) Analyical Experimen LTspice Turn on 7 235 228 Turn off 49 74 29 Toal 320 309 357 Turn on 207 263 302 Turn off 50 75 04 Toal 357 338 406 Turn on 92 28 Turn off 69 54 59 Toal 6 65 87 Turn on 8 8 99 Turn off 64 75 49 Toal 82 93 248

(a) Turn on (b) Turn off 4 show experimenal, analyical and simulaion resuls of sof-swiching a 600V, 25A and 3A. Comparing Fig. 4 (a) wih Fig. (b), he snubber circui has reduced boh he dv/ by a facor of eigh and he frequency of oscillaions by a facor of hree. The effec of muual coupling beween he snubber branch and MOSFET common source inducance is also eviden in he V gs waveforms in Fig. 3 and Fig. 4. Boh snubber curren and V gs have he same oscillaion frequency and he oscillaion in V gs is dependen on he coupling facor beween he wo parasiic inducances. Fig. 9. 600V, 20A resuls wih Cree C4D020D diode (a) Parallel C s (b) Perpendicular C s (a) Turn on (b) Turn off Fig. 3. 600V, 25A DPT resuls for ZVS a urn off Fig. 0. 600V, 20A resuls wih ROHM SCS230KE2 diode (a) Parallel C s (b) Perpendicular C s (a) Turn on (b) Turn off Fig.. 600V, 3A resuls wih Cree C4D020D diode (a) Turn on (b) Turn off Fig. 2. 600V, 3A resuls wih ROHM SCS230KE2 diode V. SIMULATION AND EXPERIMENTAL RESULTS OF SOFT- SWITCHING The DPT circui was esed in he sof-swiching configuraion for differen curren and volage levels using he same Cree MOSFET as used in he hard-swiching ess as he upper and lower leg devices. To change he coupling beween he snubber branch and MOSFET common source inducance, snubber capaciors were place in parallel (close o ) or perpendicular (away from ) o he device curren pah. Wih he perpendicular arrangemen he coupling facor, k was assumed o be zero. Fig. 3 and Fig. Fig. 4. 600V, 3A DPT resuls for ZVS a urn off The analyical model also enables he calculaion of he small urn off loss of 29 µj and 4 µj for 25A and 3A operaions, respecively by separaing he MOSFET drain curren, I d, from he shun resisor curren, I d +I c2. Turn on losses will be approximaely zero as he MOSFET urns on wih zero volage across i because of is body diode conducion. Therefore, for 3A ZVS operaion around 93% of he hard-swiching energy was saved during urn off making he oal sof-swiching loss reducion 98% compared o he hard-swiching operaion. VI. CONCLUSIONS The analyical model presened in he paper, and validaed experimenally can be used o enable rapid and accurae evaluaion of circui waveforms and device swiching losses. The analyical model uses only daashee parameers, so he impac on circui operaion and swiching losses of SiC MOSFETs or diodes wih differen snubber capacior values and circui parasiics can be evaluaed. The paper also describes he analyical and experimenal evaluaion of he impac of sof-swiching echniques on he MOSFET swiching loss, dv/ and parasiic ringing due o he inroducion of addiional parasiic inducance, which provides an undersanding of he benefis of sof-swiching in

very high speed SiC circuis and idenifies he key parasiic elemens which limi performance. Swiching loss was reduced by 98% in he sof-swiching operaion along wih he reduced oscillaions (33%) in differen circui waveforms compared o hard-swiching operaion. Also he 88% reducion in dv/ during he swiching ransiens can significanly reduce he EMI signaure of he sof-swiching circui. These improvemens sugges he use of sofswiching echniques in high speed SiC MOSFET based converers could offer significan performance benefis. APPENDIX (a + a2) a3 a4 0 V gs u + u2 + u3 = [ b 0 b2 0 V ] ds v + [ ] (A) I d 0 0 0 I d 0 [ I d ] d 0 d2 d3 [ I d ] w (a + a2) 0 a4 a5 V gs u + u2 = [ b 0 b2 0 V ] ds v + [ ] (A2) I d 0 0 0 I d 0 [ I d ] d 0 d4 d3 [ I d ] w2 w V gs a 0 a5 u [ I d ] = [ 0 0 ] [ I d ] + [ 0 ] (A3) 0 d5 d3 I d I d w2 a 0 a4 a5 V gs u 0 0 b2 0 V = [ ] ds 0 + [ ] (A4) I d 0 0 0 I d 0 [ I d ] 0 0 d2 d3 [ I d ] 0 (a+ a2) 0 a4 a5 0 a6 V gs u + u2 b 0 b2 0 0 0 V ds v I d = 0 0 0 0 0 I d 0 + (A5) I d e 0 e2 e3 e4 e5 I d x x2 0 0 0 0 0 I c2 0 I c2 [ f 0 f2 f3 f4 f5 ] [ I c2 ] [ y y2] [ I c2 ] a 0 a4 a5 0 a6 V gs u 0 0 b2 0 0 0 V ds 0 I d 0 0 0 0 0 I d 0 = + 0 0 e2 e3 e4 e5 I d I d x 0 0 0 0 0 I c2 0 I c2 [ 0 0 f2 f3 f4 f5 ] [ I c2 ] [ y] [ I c2 ] I d I d I c2 I c2 [ V s ] a 0 a4 a5 0 a6 0 V gs u 0 0 b2 0 0 0 0 V ds 0 0 0 0 0 0 0 I d 0 = 0 0 e2 e3 e4 e5 e6 I d + x 0 0 0 0 0 0 I c2 0 0 0 f2 f3 f4 f5 f6 y I c2 [ 0 0 g 0 g 0 g2] [ V s ] [ z] a = e = L e3g m L e4 L e3 ( + ) a2 = g mc gd C iss e2 = a3 = L s e3 = R s (L e4 L e3 ) a4 = (L s +L d ) C gd C iss L s e4 = L e4( +C s2 ) L e3 C s2 C s2 (A6) (A7) u = V g_in u2 = g mv h C gd C iss u3 = R sl s V dd L s (L s +L d ) v = g mv h a5 = e5 = R s (L e4 L e3 ) w = g mv h a6 = M b = g m e6 = L e3 L e4 w2 = R d (L s +L d ) I dd C ak (L s +L d ) f = L eg m x = I dd (L e3 L e4 ) b2 = f2 = L e2 L e ( + ) x2 = L e3g m V h g d = m f3 = R s (L e2 L e ) y = I dd (L e L e2 ) d2 = d4 = d3 = d5 = (L s +L d ) f4 = L e2( +C s2 ) L e C s2 y2 = L eg m V h C s2 L s +L d f5 = R s (L e2 L e ) z = I dd (L s +L d ) R s C ak+ C ak (L s +L d ) C ak (L s +L d ) Where, L e = L e2 = L e3 = L e4 = f6 = L e L e2 R d g = g2 = L sh +M M 2 +2L sh M L sh (L s +L d ) L s2 (L s +L d ) L s2 L sh L sh +L s +L d M 2 +2L sh M L sh (L s +L d ) L s2 (L s +L d ) L s2 L sh L sh +L s2 M 2 +2L sh M L sh (L s +L d ) L s2 (L s +L d ) L s2 L sh L sh +M M 2 +2L sh M L sh (L s +L d ) L s2 (L s +L d ) L s2 L sh REFERENCES R d [] T. Kimoo, and J. A. Cooper, Fundamenals of Silicon Carbide Technology: Growh, Characerizaion, Devices and Applicaions: John Wiley & Sons, 204. [2] N. Mohan, and T. M. Undeland, Power elecronics: converers, applicaions, and design: John Wiley & Sons, 2007. [3] M. Mudholkar, S. Ahmed, M. N. Ericson e al., Daashee Driven Silicon Carbide Power MOSFET Model, IEEE Transacions on Power Elecronics, vol. 29, no. 5, pp. 2220-2228, 204. [4] S. Pobhare, N. Goldsman, A. Akurk e al., Energy- and Time- Dependen Dynamics of Trap Occupaion in 4H-SiC MOSFETs, IEEE Transacions on Elecron Devices, vol. 55, no. 8, pp. 206-2070, 2008. [5] C. Zheng, D. Boroyevich, R. Burgos e al., Characerizaion and modeling of.2 kv, 20 A SiC MOSFETs, IEEE Energy Conversion Congress and Exposiion (ECCE), pp. 480-487, 20-24 Sep. 2009. [6] W. Jun, Z. Tiefu, L. Jun e al., Characerizaion, Modeling, and Applicaion of 0-kV SiC MOSFET, IEEE Transacions on Elecron Devices, vol. 55, no. 8, pp. 798-806, 2008. [7] J. Fabre, P. Ladoux, and M. Pion, Characerizaion and Implemenaion of Dual-SiC MOSFET Modules for fuure use in Tracion Converers, IEEE Transacions on Power Elecronics,vol. 30, no. 8, pp. 4079-4090, 205. [8] R. Khanna, A. Amrhein, W. Sanchina e al., An analyical model for evaluaing he influence of device parasiics on Cdv/ induced false urn-on in SiC MOSFETs, Tweny-Eighh Annual IEEE Applied Power Elecronics Conference and Exposiion (APEC) pp. 58-525, 7-2 March 203. [9] C. DiMarino, C. Zheng, M. Danilovic e al., High-emperaure characerizaion and comparison of.2 kv SiC power MOSFETs, IEEE Energy Conversion Congress and Exposiion (ECCE), pp. 3235-3242, 5-9 Sep. 203. [0] G. Calderon-Lopez, and A. J. Forsyh, High power densiy DC-DC converer wih SiC MOSFETs for elecric vehicles, 7h IET Inernaional Conference on Power Elecronics, Machines and Drives (PEMD), pp. -6, 8-0 April 204. [] M. R. Ahmed, G. Calderon-Lopez, F. Bryan e al., Sof-Swiching SiC Inerleaved Boos Converer, IEEE Applied Power Elecronics Conference and Exposiion (APEC), pp. 94-947, 5-9 March 205. [2] R. Yuancheng, X. Ming, J. Zhou e al., Analyical loss model of power MOSFET, IEEE Transacions on Power Elecronics, vol. 2, no. 2, pp. 30-39, 2006. [3] W. Jianjing, H. S. H. Chung, and R. T. H. Li, Characerizaion and Experimenal Assessmen of he Effecs of Parasiic Elemens on he MOSFET Swiching Performance, IEEE Transacions on Power Elecronics, vol. 28, no., pp. 573-590, 203. [4] E. B. Rosa, The Self and Muual Inducances of Linear Conducors, Bullein of he Bureau of Sandards, vol. 4, no. 2, 908.