High Efficient Heat Dissipation on Printed Circuit Boards. Markus Wille, R&D Manager, Schoeller Electronics Systems GmbH

Similar documents
High efficient heat dissipation on printed circuit boards

High Frequency Single & Multi-chip Modules based on LCP Substrates

B. Flip-Chip Technology

What the Designer needs to know

AN5046 Application note

BGA/CSP Re-balling Bob Doetzer Circuit Technology Inc.

Handling and Processing Details for Ceramic LEDs Application Note

Transistor Installation Instructions

Application Note 5026

MHz (FM BAND) 50 Volts Input/output 50 ohms Pout: 1000W minimum 78% 23dB Gain NXP BLF184XR Mosfet

MHz (FM BAND) 50 Volts Input/output 50 ohms Pout: 1250W minimum Up to 85% efficiency 22dB Gain NXP MRF1K50 Mosfet Planar RF Transformers

TOLERANCE FORGOTTEN: IMPACTS OF TODAY S COMPONENT PACKAGING AND COPPER ROUTING ON ELECTRONIC

Reflow Technology Product Overview

SEMITOP Mounting instructions

Bob Willis Process Guides

A review of the challenges and development of. the electronics industry

What Can No Longer Be Ignored In Today s Electronic Designs. Presented By: Dale Lee

REFLOW TECHNOLOGY. Product Overview

AltiumLive 2017: Creating Documentation for Successful PCB Manufacturing

MHz (FM BAND) 50 Volts Input/output 50 ohms Pout: 1000W minimum Up to 85% efficiency 24dB Gain NXP BLF188XR Mosfet Planar RF Transformers

Handling and Processing Details for Ceramic LEDs Application Note

PAGE 1/6 ISSUE Jul SERIES Micro-SPDT PART NUMBER R516 XXX 10X R 516 _ 1 0 _

TC600. Enhanced Thermal Conductivity Ceramic Filled PTFE/Woven Fiberglass Laminate for Microwave Printed Circuit Boards

Printing and Assembly Challenges for QFN Devices

Low-Cost PCB Design 1

BGA (Ball Grid Array)

MICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation

SEMITOP Mounting instructions

PAGE 1/6 ISSUE SERIES Micro-SPDT PART NUMBER R516 XXX 10X. (All dimensions are in mm [inches]) R 516 _ 1 0 _

HOTBAR REFLOW SOLDERING

Custom MMIC Packaging Solutions for High Frequency Thermally Efficient Surface Mount Applications.

SESUB - Its Leadership In Embedded Die Packaging Technology

Assembly Instructions for the FRB FET FM 70 Watt Amp

An Introduction to Electronics Systems Packaging. Prof. G. V. Mahesh. Department of Electronic Systems Engineering

Thermal Cycling and Fatigue

- UMP series : board to wire application

UMS User guide for bare dies GaAs MMIC. storage, pick & place, die attach and wire bonding

Advanced High-Density Interconnection Technology

Applications of Solder Fortification with Preforms

Mounting Approaches for RF Products Using the Package Type

BOARD DESIGN, SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY ASPECTS OF FUSIONQUAD TM PACKAGES

!"#$"%&' ()#*+,-+.&/0(

High Current Voltage Regulator Module (VRM) Uses DirectFET MOSFETs to Achieve Current Densities of 25A/in2 at 1MHz to Power 32-bit Servers

Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design

Frequency Range: MHz. Efficiency: 80% Temperature Range: -20 to 65 C Max VSWR: 3:1. Class: Supply Voltage: 32.0V

Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design

Innovations Push Package-on-Package Into New Markets. Flynn Carson. STATS ChipPAC Inc Kato Rd Fremont, CA 94538

Sectional Design Standard for Flexible/Rigid-Flexible Printed Boards

Features MIN. CATHODE LEAD ± 0.10 Sq Typ ± MAX. EPOXY MENISCUS

Two major features of this text

23. Packaging of Electronic Equipments (2)

Our Top 10 Commonly Asked Soldering Questions This Year

Manufacture and Performance of a Z-interconnect HDI Circuit Card Abstract Introduction

Laminate Based Fan-Out Embedded Die Technologies: The Other Option

Soldering Module Packages Having Large Asymmetric Pads

Assembly/Packagng RF-PCB. Thick Film. Thin Film. Screening/Test. Design Manual

14.8 Designing Boards For BGAs

mcube LGA Package Application Note

AN1703 APPLICATION NOTE GUIDELINES FOR USING ST S MOSFET SMD PACKAGES

Fill the Void IV: Elimination of Inter-Via Voiding

APPLICATION NOTE 6381 ORGANIC LAND GRID ARRAY (OLGA) AND ITS APPLICATIONS

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative

Efficiency: 68% Temperature Range: +0 to 60 C Max VSWR: 5:1. Class: Supply Voltage:

MLPF-WB55-01E GHz low pass filter matched to STM32WB55Cx/Rx. Datasheet. Features. Applications. Description

10. Mini Coax Connectors

Smart Devices of 2025

10. Mini Coax Connectors

Brief Introduction of Sigurd IC package Assembly

HLMP-EG2E, HLMP-EG3E Data Sheet Description Features Applications Benefits

CF Series AXC5/AXC6. FEATURES 1. Vertical mating type with a 0.8 mm mated height low profile design

TAIPRO Engineering. Speaker: M. Saint-Mard Managing director. TAIlored microsystem improving your PROduct

Surface Mount Header Assembly Employs Capillary Action

Leiterplattenoberflächen im Fokus

Application Notes. Introduction

Getting the FLI Lead Out. Thomas J. De Bonis Assembly & Test Technology Development Technology and Manufacturing Group

Thermal behavior of the new high-current PROFET

Specifications subject to change Packaging

1208 P10-VHF-H-20. Frequency Range: MHz. Efficiency: 10% Temperature Range: 0 to 70 C Max VSWR: 5:1. Class: Supply Voltage: 28.

An Introduction to Electronics Systems Packaging. Prof. G. V. Mahesh. Department of Electronic Systems Engineering

Application Note 5351

SELECTOR GUIDE WIRELESS DATACOM INFRASTRUCTURE

An Investigation into Lead-Free Low Silver Cored Solder Wire for Electronics Manufacturing Applications

CPC3982TTR (SOT-23) N-Channel Depletion-Mode Vertical DMOS FET INTEGRATED CIRCUITS DIVISION

GS61008T Top-side cooled 100 V E-mode GaN transistor Preliminary Datasheet

PLED Unidirectional Series (PLEDxUx)

Power Integration in Circuit Board

WIRE WOUND CHIP INDUCTORS HCI SERIES HCI 0805 F T 1R0 K - Introductions. Features. Part Number Code HCI SERIES

Sophisticated Microelectronics. Design Manual

Application Note AN-1011

CHX2090-QDG RoHS COMPLIANT

I-PEX MHF Micro Coaxial Connector Applicable Cable for O.D. 1.37mm Cable

FPC connectors (0.3mm pitch) Front lock with FPC tabs

Features. Parameter Frequency Min. Typ. Max. Units. Return Loss Off State DC - 20 GHz 13 db

Yole Developpement. Developpement-v2585/ Publisher Sample

TGV2204-FC. 19 GHz VCO with Prescaler. Key Features. Measured Performance. Primary Applications Automotive Radar. Product Description

Data Sheet. HLMA-KL00 & HLMA-KH00 SunPower Series T-1 (3 mm), High Performance AlInGaP LED Lamps. Description. Features.

Assembly Guidelines Sterling Silver & MacStan Immersion Tin Coated PCB s

HOW DOES PRINTED SOLDER PASTE VOLUME AFFECT SOLDER JOINT RELIABILITY?

The Design Challenge to Integrate High Performance Organic Packaging into High End ASIC Strategic Space Based Applications.

CPC3982TTR (SOT-23) N-Channel Depletion-Mode Vertical DMOS FET INTEGRATED CIRCUITS DIVISION

Transcription:

High Efficient Heat Dissipation on Printed Circuit Boards Markus Wille, R&D Manager, Schoeller Electronics Systems GmbH m.wille@se-pcb.de

Introduction 2 Heat Flux: Q x y Q z The substrate (insulation) material is a poor heat conductor, l ~ 0.2 W/mK The thermal conductivity of copper is much higher, l ~ 390 W/mK Depending on the copper distribution the heat flux in a circuit board is normally better in the x-y plane compared to the heat flux in the z-axis. A power or ground layer has a big influence on the heat flux. The heat flux and direction is mainly dominated by the thermal conductivity of the materials and the delta T in a given area. Tracks on or in a PCB are more or less useless for a good heat flux. The cross area is too low.

Introduction 3 The thermal situation of the complete system has to be taken into consideration P-BGA FC-BGA Components Casing Thermal interfaces Heat sinks Cooling Environmental and operating conditions Many microelectronics components are designed with a predetermined thermal pathway inside their packages

Introduction 4 Some classical methods for dissipating heat... PCB attached on heat sink PCB with thick copper layers

Methods for dissipating heat from printed circuit boards 5 Introduction of local copper coins Full Size Heatsink Local Heat Dissipation Internal External Thermal Vias Local Cu-Coin Metal-Core Layers Pre-bonded (e. g. IMS) Bonded Cu-Coin Thick-Copper Layers Post-bonded Embedded Cu-Coin Press-Fit Cu-Coin Local dissipation of heat loss by integration of copper coins

Local dissipation of heat loss by integration of copper coins 6 Adhesive bonded copper coin Adhesive Copper Coin Copper coin is bonded to the circuit board by adhesive (conductive or non-conductive) Alternative for soldered coins: - Increased reliability and flatness - No solder residues or undesired solder flow Feasible for double sided SMT assembly Feasible for lead-free soldering Very flexible in the design No special assembly processes required Coin can have cavity Copper Coin Adhesive preform

Local dissipation of heat loss by integration of copper coins 7 Example: Adhesive bonded copper coin with a flange The flange spreads the heat and enables a better thermal connection to a heat sink (enlargement of the surface area)

Local dissipation of heat loss by integration of copper coins 8 Embedded copper coin Copper Coin The coin is fully integrated in the layer construction of the PCB The surface of the copper coin can be in plane with both surfaces of the circuitry SMT power devices can be assembled easily Reliable and robust Coin can be connected to the circuitry either by vias and/or copper metallisation on the surface layers

Local dissipation of heat loss by integration of copper coins 9 Example: Embedded copper coin with cavity Bottom view Top view Copper metallisation connects coins with PCB Micro section The more layers the more difficult to control the proper fitting of the coin inside the PCB construction

Local dissipation of heat loss by integration of copper coins 10 Press-fitted copper coin Cu-Coin Very high thermal conductivity Very high robustness and reliability Strong press-fitting (push-out force typ. > 500 N) Copper coin can be electrically connected by edge metallisation (good grounding) Coin design can be matched for component footprint Can be placed nearly under any electrical component Already in practice in automotive electronics, telecom infrastructure, industrial electronics and defence

Local dissipation of heat loss by integration of copper coins 11 Example: Press-fitted copper coins for components with QFN and QFP packages Coins with dia. of 3 mm Coins with dia. of 2 mm The design of the coins and the integration require some specific know how. Therefore, a technical dialogue between PCB designer and manufacturer is needed and recommended.

Local dissipation of heat loss by integration of copper coins 12 Thermal vias vs. copper coin Example: Thermal conductivity of a thermal array of 5 mm x 5 mm Thermal-Via array of 5 mm x 5 mm with 25 Thermal-Vias of Ø 0.5 mm Thermal Pad of 5 mm x 5 mm with 1 Copper Coin of Ø 4 mm l = 14.5 W/mK R th = 4.14 K/W l = 194 W/mK R th = 0.31 K/W

Local dissipation of heat loss by integration of copper coins 13 How about filled thermal vias? Example: Thermal conductivity of a thermal array of 5 mm x 5 mm In practise a void-free filling of vias is very difficult to achieve A filling of vias with electrolytic deposited copper in mass production is only feasible at a low aspect ratio (typ. 1:1) Some figures... Vias plated with a 25 µm thick Cu barrel Vias plated with a 27 µm thick Cu barrel Vias plated with a 30 µm thick Cu barrel Vias (25 µm thick Cu) filled with conductive Silver paste Vias (25 µm thick Cu) filled with Solder l W/mK R th K/W 14.5 4.1 15.6 3.8 17.2 3.5 15.4 3.9 25.2 2.3 1 copper coin, Ø 4 mm 194 0.3

Local dissipation of heat loss by integration of copper coins 14 Risks associated with thermal via arrays The vias of a thermal via array may cause voids under a component package Example: QFN package soldered onto a thermal via array Large voids appearing inside the solder joint between the thermal pad of the component and the thermal via array of the PCB Voids are caused by solder wicking into the holes The voids are significantly increasing the thermal resistance in the heat dissipation pathway Tenting or plugging of vias may be considered (increasing costs) Source: Indium Corporation

Local dissipation of heat loss by integration of copper coins 15 Comparison: Thermal vias vs. Copper coin - Thermographic images Thermal Vias Copper Coin Note: A reduction of the component temperature by 10 C can double the component life time (Rule of Arrhenius)

Further designs of copper coins 16 Example: Copper coin with cavity for component insertion RF power transistor in SOT-502 package with straight leads High mechanical precision for a perfect integration of the electronic component

Further designs of copper coins 17 Chip-on-Coin: Bare die attachment on copper coins Higher miniaturisation Cost reduction of expensive packages Higher efficiency Lower number of thermal interfaces Reduced thermal resistance in the thermal pathway CTE matching by selected coin materials

Further designs of copper coins 18 Chip-on-Coin: Bare die attachment on copper coins Thermal interfaces in the thermal pathway with housed components: Copper Coin Chip Die Attach Paste Thermal Flange Solder Coin Thermal interfaces in the thermal pathway with bare die attachment: Chip Die Attach Paste Coin Bare die attached on Cu coin For bare die attachment on PCBs low temperature sintering compounds based Copper Coin on nano-scaled silver particles are available

Further designs of copper coins 19 Rigid-flexible circuit boards with integrated copper coins The solid copper coin provides approx. 10 times higher thermal conductivity than thermal via arrays High push-out forces: typ. > 500 N to 1000 N Suitable for circuit thicknesses 0.8 mm Size of coins: from ca. Ø 2 mm to 40 mm x 40 mm Very robust and reliable

RF power module pallets 20 The pallets include already the complete bias network for an application First product launched by NXP (BLS6G2933P-200) Plug-and-Play modules using special materials matching CTE values of packaging and die

Tailored coin design 21 The design of the coins are customised to match perfectly to the footprint of the components and the entire system Selection of the coin attachment (e. g. bonded, embedded or press-fit) SES provides design proposal based on the component footprint and system considerations Tolerance evaluation Design optimisation if necessary Surface finishes as required Prototypes usually machined Choice of suitable methods for mass production (e. g. punching, milling or combinations)

Tailored coin design 22 Example: Copper coin design for QFN packages Component Footprint Concept Real product

Reliability 23 Summary of some reliability test results. More data available upon request. Test Parameter Result Lead-free reflow soldering (10 x) J-STD-003A passed Thermal shock 100 cycles: - 55 C to + 125 C 1000 cycles: - 55 C to + 125 C passed Thermal stress 6 x 10 sec. on 288 C solder float bath passed Ageing (Temperature storage) 1000 h at 125 C passed Electrochemical migration (Humidity storage) 1000 h at 85 C and 85 % r. h. passed Delamination test Push-out force pre-cond. 72 h at 40 C, 92 % r. H. solder stress 20 sec. at 288 C typ. > 500 N (dep. on coin design and size) passed passed

Reliability 24 Measurement of Push-Out Force A high push-out force of the coin is required for assembly and further installation

Reliability 25 Measurement of Contact Resistance Very low resistance added to the current return loop Contact resistance of the coins << R DSON of the power transistors

Conclusion 26 Electronics cooling is becoming a more important subject with continuing miniaturisation and increasing functionality Standard techniques such as thermal via arrays have only a limited thermal conductivity Local copper coins provide a very high thermal conductivity on a small area; their thermal conductivity is typ. about 10 times higher compared to thermal via arrays of similar sizes Local copper coins are reducing weight and costs compared to conventional attached heat sinks and providing the opportunity of assembling components on both sides of the PCB Simplifying assembly process, increasing first pass yield The integration of local copper coins into the PCB constructions is an established process PCB s with integrated local copper coins are very reliable and robust The designs of the copper coins are very flexible, can be tailored for specific components and requirements and are also suitable for direct die attach

Thank you very much for your attention.