Drive and Layout Requirements for Fast Switching High Voltage MOSFETs

Drive and Layout Requirements for Fast Switching High Voltage MOSFETs

Contents Introduction SuperJunction Technologies Influence of Circuit Parameters on Switching Characteristics Gate Resistance Clamp diodes Ferrite Bead Drive IC External C gd Source Inductance Practical Layout Requirements Summary 2

EField Distribution of SJ Technology SJ Technology Allows Twice BV for Same Doping Planar MOSFET SuperJunction MOSFET EField EField A B A B BV B A A B BV Area is proportional to BV Si limitation : On resistance and BV is tradeoff Area is twice so BV is twice for same doping thanks to charge balance On resistance is in linear relation on BV 3

Specific Rdson [mohmcm 2 ] Silicon Limit of HV MOSFETs? 60 55 50 45 40 35 30 25 20 15 10 5 0 5 Ron A near linear relation between Rds(on) and Breakdown Voltage A significant reduction of conduction and switching losses High power density for highend application. 0 100 200 300 400 500 600 700 Breakdown Voltage (V) 9 2.5, sp 6 10 BV Rds(on)is linear relation on BV Results in 10times lower Rds(on) at 600V Planar MOSFET A ` B EField BV A B Area is proportional to BV SuperJunction MOSFET A B EField BV A B Area is twice so BV is twice for same doping thanks to charge balance 4

Nonlinear Coss in SJ MOSFET C o r A d a b c Coss curve of superjunction MOSFET is highly nonlinear Extremely fast dv/dt and di/dt and voltage and current oscillation 10000 SJ MOSFET Planar MOSFET Vgs : 5V/div 50ns/div Coss [pf] 1000 100 Vds:100V/div Id:2A/div SJ MOSFET @ Ron=120Ω, Roff=30Ω vs Planar MOFET @ Ron=22Ω, Roff=10Ω(Ref.) a b c 0.1 1 10 100 Vds [V] 5

SuperFET3 vs SuperFET2 DUTs SuperFET 3 SuperFET 2 FCH040N65S3 FCH041N60E BV DSS @ T J =25 650 V 600 V I D @ T C =25 68.0A 77.0 A R DS(ON) max. I D =34A 40mΩ 41mΩ V GS(th) 2.5V ~ 4.5V 2.5V ~ 3.5V V GSS @ DC ±30V ±20V *Q g @ V dd =400V, I D =34A, V gs =10V * 158 nc * 330 nc *R g @ f = 1 MHz * 0.7 Ω 1.2 Ω *E OSS @ 400V DS * 13.7 uj * 25.7 uj *Q OSS @ 400V DS * 521 nc * 596 nc Peak diode recovery dv/dt 20V/ns 52% 47% 13% 20V/ns MOSFET dv/dt 100V/ns 100V/ns 6

Gate Charge Characteristic SuperFET3 Low Gate Charge and Input Capacitance Vgs [V] 12 10 SuperFET3 SuperFET2 30000 25000 SuperFET 3 SuperFET 2 20000 8 6 4 Ciss [pf] 15000 10000 2 0 0 50 100 150 200 250 300 350 Gate Charge [nc] FCH040N65S3 FCH041N60E C iss = C gs C gd (C ds = shorted) Notes : 1. V GS = 0 V 2. f = 1 MHz 5000 0.1 1 10 100 V DS, DrainSource Voltage [V] DUTs FCH040N65S3 FCH041N60E Q gs 39.8 57.1 Q gd 63.8 121.0 Q g 157.9 330.2 7

Clamped Inductive Switching Circuit & Waveforms and Loss Definition Test Circuit which is used for the following measurements. 8

Effects of Gate Resistance at Turn On Transient GateSource Voltage [V] 30 20 10 0 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm Pon [W] 12000 10000 8000 6000 4000 2000 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm 10 0 100 80 60 40 20 0 20 40 Time [ns] 2000 100 80 60 40 20 0 20 40 Time [ns] 40 400 DrainSource Voltage [V] 300 200 100 0 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm Drain Current [A] 30 20 10 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm 0 100 100 80 60 40 20 0 20 40 Time [ns] 100 80 60 40 20 0 20 Time [ns] 9

Effects of Gate Resistance at Turn Off Transient GateSource Voltage [V] 20 10 0 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm Poff [W] 6000 5000 4000 3000 2000 1000 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm 0 10 100 80 60 40 20 0 20 40 60 Time [ns] 1000 100 80 60 40 20 0 20 40 60 Time [ns] 600 20 DrainSource Voltage [V] 500 400 300 200 100 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm Drain Current [A] 18 16 14 12 10 8 6 4 2 0 Rg=3.3ohm Rg=6.8ohm Rg=10ohm Rg=27ohm Rg=47ohm 2 0 100 80 60 40 20 0 20 40 60 Time [ns] 4 100 80 60 40 20 0 20 40 60 Time [ns] 10

Effects of Gate Resistance 120 110 100 90 80 Eon Eoff Eon& Eoff @ Id=9A, Vds=380V Eon[uJ] 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 R g, Gate Resistor [ohm] Critical control parameter in gatedrive design is external series gate resistor (Rg). From an application standpoint, selecting the optimized Rg is very important. Efficiency vs dv/dt or voltage spikes. 11

Reverse Recovery Effect Si Diode vs SiC Schottky Diode 10 8 6A SiC Schottky diode 8A Si diode 6 Current [A] 4 2 0 2 4 6 80.0n 60.0n 40.0n 20.0n 0.0 20.0n 40.0n 60.0n 80.0n 100.0n Time[s] 12

Effect of Clamp Diodes at Turn On Si Diode vs SiC Schottky Diode IF : 2A/div. Vds : 100V/div. Eon=50.72uJ Vr: 100V/div. Id : 2A/div. Time : 20ns/div. Diode & MOSFET waveforms @ Turnon with SiC Schottky diode Eon=90.33uJ Diode & MOSFET waveforms @ Turnon with Si diode 13

Effect of Clamp Diodes at Turn Off Si Diode vs SiC Schottky Diode Vgs : 5V/div. Eoff Id : 0.5A/div. Vds : 100V/div. 6A SiC SBD 8A Si Diode Time : 100ns/div. 6A SiC diode Turn off @ Id=1A, Rg=4.7 Ω with 6A SiC SBD (Ref : 8A Si Diode) 8A Si Diode 14

Effect of Clamp Diodes Si Diode vs SiC Schottky Diode 80 70 With Si Diode With SiC Schottky MOSFET Eon @ Id=9A, Vdd=380V 100 With Si Diode With SiC Schottky Diode 60 80 Eon[uJ] 50 40 dv/dt [V/ns] 60 30 20 40 10 20 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 R g, Gate Resistor [ohm] Rg [ohm] SiC Schottky diode is optimized device for extremely fast switching MOSFET. 15

Effects of Ferrite Bead Vgs with ferrite bead Vgs without ferrite bead Vgs : 10V/div. Vgs without ferrite bead Vgs : 10V/div. Vgs with ferrite bead Time :10ns/div. (a) Vgs at Turnon Transient (b) Vgs at Turnoff Transient 16

Equivalent Circuit of Ferrite Bead Z Gate Ferrite Bead C para R X R bead L bead R para Z R jx 17

Effects of Current Capability of Driver IC TABLE I. Comparisons of Critical Specification of Gate Drivers DEVICE CONDITION I PK_SINK I PK_SOURCE FAN3122T C LOAD =1.0uF,f=1kHz,Vdd=12V 11.4[A] 10.6[A] FAN3224T C LOAD =1.0uF,f=1kHz,Vdd=12V 5.0[A] 5.0[A] FAN3111C C LOAD =1.0uF,f=1kHz,Vdd=12V 1.4[A] 1.4[A] * DUT : FCP16N60N with 6A SiC SBD 12.0 11.5 11.0 FAN3122T FAN3224T FAN3111C Eoff @ Rg=2.2ohm 36 33 30 FAN3122T FAN3224T FAN3111C Eon @ Rg=20ohm 10.5 27 10.0 24 Eoff[uJ] 9.5 9.0 Eon[uJ] 21 18 8.5 15 8.0 12 7.5 9 7.0 0 2 4 6 8 10 Drain Current [A] 6 0 2 4 6 8 10 Drain Current [A] 18

Effects of Gate Drive Circuit Vcc OUT GND Don Ron Doff Roff Vcc OUT GND Don Ron Roff Qoff PNP Tr turnoff can reduce gate ringing. It s possible to reduce parasitic components in PCB. Keep loop area as small as possible to avoid worse EMI and switching behavior. * Ron=10hom, Roff=4.7ohm 19

Measurement Technique R L Probe C C Oscilloscope R L Ground Lead Probes are circuits composed of distributed R,L, and C for AC signals. A total probe impedance varies with switching frequency. Ringing Standard gate probing R 1 RL C P 8pF R P 10M L G The probe ground lead adds inductance to the circuit. 20

Keep the Loop Probe Small! 15 10 Measuremet with standard setup Measuremet with Probe tip Vgs pkpk =26V Measurement with standard setup S D G 5 Vgs [V] 0 Vgs pkpk =11.2V 5 Measurement with Probe Tip 10 S D G 15 100 80 60 40 20 0 20 40 60 80 100 Time [ns] 21

Package and Layout Parasitics Package parasitics 1cm / 0.25mm trace (L/W) 610nH L=10nH, di/dt=500a/μs V ind =5V L=10nH, di/dt=1,000a/μs V ind =10V Layout parasitics A lot of layout parasitic has to be considered! 22

MOSFET Oscillation Circuit L R Gext. =5.1O C gd_ext. L G Osc illation circuit given by external couple capacitance L g1 R g_int. C gd_int. C gs L D L d1 C ds D boost C O MOSFET R LOAD Cgd_ext. Rg Resonant circuit given by external coupling capacitance L G L G1 C GD C GS L D L D1 C DS L S1 MOSFET Resonant circuit L s1 L S L S A lot of layout parasitic has to be considered! 23

Layout Capacitance Example with High External C GD y d C x A x y 0 d r A Capacity between trace pitches Gate External C GD External C GD too high!! Drain Drain Gate External C GD (a) Single layer PCB External C GD External C GD (b) Double layer PCB 24

Layout Capacitance Examples with Reduced External C GD Gate Drain External C GD Drain Gate External C GD Gndplane or Shieldplane reduces C GD Minimized external C GD Minimized external C GD (a) double layer PCB Both solutions allow use of SJ Devices (b) multi layer PCB 25

Layout Example Large External C GD Vgs Shows Higher Spikes During Turn Off PCB example with large external C GD Coupling area Gate V DS Drain V GS DV GS ~ 18V 26

Layout Example Small External C GD Vgs Shows Lower Spikes During Turn Off PCB example with small external C GD Coupling area V DS Gate Drain V GS DV GS ~ 4V 27

Turnoff Gate Oscillation Mechanism VDS During T 2 LD Id 10000 SJ MOSFET RG VGS VGS_int Coss [pf] 1000 LG LG_int VGS_int 100 LS_int Discharging VGS VDS LS di VLS LS dt Id Negative di/dt 0.1 1 10 100 Vds [V] D t V GS : 5V/div V DS : 100V/div I D : 2A Keep the commutation loop as small as possible! Minimize the source inductance and sensing resistor inductance 28

Effects of Source Inductance LS=1n and 10nH V gs V gs (a) V gs waveform for low L S (b) V gs waveform for High L S V ds I d * Topology : 500W Interleaved CRM PFC * MOSFET : FCPF13N60N * Diode : FFPF20UP60DN * Gate Resistor : Ron=51ohm, Roff=10ohm (c) V ds and I d waveform 29

Gate oscillation vs Package Through hole vs SMD vs Kelvin source SMD I D =8A 600V/199mΩ, Power88 600V/199mΩ, D2PAK 600V/199mΩ, TO220 Kelvin Source SMD SMD Through hole Turnoff Transient Gate Oscillation Gate Oscillation 30

Design Tips Practical Layout Example Boost PFC Bad Layout: Good Layout: Increased external GD capacitance Driver and gate resistor far away from gate pin of MOSFET Connect the driverstage Gnd directly to the source pin to achieve best performance Driver & Rg as close as possible to the gate pin of MOSFET G D S G D S Ron Qoff Don Roff Ron Roff Long gate path Separate Power GND and gate driver GND 31

Design Tips Practical Layout Example Paralleling MOSFETs Minimized source inductance to reference Two independent totem pole drivers very close to MOSFET gate point for gate drive minimized Minimized Cgd: Gate and Drain trace at 90 angle 32

Summary How to Use SuperJunction MOSFET in Practical Layouts To achieve the best performance of SuperJunction MOSFETs, optimized layout is required Gate driver and Rg must be placed as close as possible to the MOSFET gate pin Separate POWER GND and GATE Driver GND Minimize parasitic C gd capacitance and source inductance on PCB For paralleling SuperJunction MOSFETs, symmetrical layout is mandatory Slow down dv/dt, di/dt by increasing Rg or using ferrite bead 33

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