SMPS MOSFET PD - 95536 IRFB23N20DPbF IRFS23N20DPbF IRFSL23N20DPbF HEXFET Power MOSFET Applications High frequency DC-DC converters Lead-Free l l V DSS R DS(on) max I D 200V 0.Ω 24A Benefits Low Gate-to-Drain Charge to Reduce Switching Losses Fully Characterized Capacitance Including Effective C OSS to Simplify Design, (See App. Note AN1) Fully Characterized Avalanche Voltage and Current l l l TO-220AB IRFB23N20D D 2 Pak IRFS23N20D TO-262 IRFSL23N20D Absolute Maximum Ratings Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, V GS @ V 24 I D @ T C = C Continuous Drain Current, V GS @ V 17 A I DM Pulsed Drain Current 96 P D @T A = 25 C Power Dissipation 3.8 W P D @T C = 25 C Power Dissipation 170 Linear Derating Factor 1.1 W/ C V GS Gate-to-Source Voltage ± 30 V dv/dt Peak Diode Recovery dv/dt ƒ 3.3 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range C Soldering Temperature, for seconds 300 (1.6mm from case ) Mounting torqe, 6-32 or M3 screw lbf in (1.1N m) Typical SMPS Topologies l Telecom 48V input Forward Converter Notes through are on page 11 www.irf.com 1 7/20/04
Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Voltage 200 V V GS = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Voltage Temp. Coefficient 0.26 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 0. Ω V GS = V, I D = 14A V GS(th) Gate Threshold Voltage 3.0 5.5 V V DS = V GS, I D = 250µA I DSS Drain-to-Source Leakage Current 25 V µa DS = 200V, V GS = 0V 250 V DS = 160V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage V GS = 30V na Gate-to-Source Reverse Leakage - V GS = -30V Dynamic @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units Conditions g fs Forward Transconductance 13 S V DS = 50V, I D = 14A Q g Total Gate Charge 57 86 I D = 14A Q gs Gate-to-Source Charge 14 21 nc V DS = 160V Q gd Gate-to-Drain ("Miller") Charge 27 40 V GS = V, t d(on) Turn-On Delay Time 14 V DD = V t r Rise Time 32 ns I D = 14A t d(off) Turn-Off Delay Time 26 R G = 4.6Ω t f Fall Time 16 V GS = V C iss Input Capacitance 1960 V GS = 0V C oss Output Capacitance 300 V DS = 25V C rss Reverse Transfer Capacitance 65 pf ƒ = 1.0MHz C oss Output Capacitance 2200 V GS = 0V, V DS = 1.0V, ƒ = 1.0MHz C oss Output Capacitance 120 V GS = 0V, V DS = 160V, ƒ = 1.0MHz C oss eff. Effective Output Capacitance 220 V GS = 0V, V DS = 0V to 160V Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energy 250 mj I AR Avalanche Current 14 A E AR Repetitive Avalanche Energy 17 mj Thermal Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 0.90 R θcs Case-to-Sink, Flat, Greased Surface 0.50 C/W R θja Junction-to-Ambient 62 R θja Junction-to-Ambient 40 Diode Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbol 24 (Body Diode) showing the A G I SM Pulsed Source Current integral reverse 96 (Body Diode) p-n junction diode. S V SD Diode Forward Voltage 1.3 V T J = 25 C, I S = 14A, V GS = 0V t rr Reverse Recovery Time 200 300 ns T J = 25 C, I F = 14A Q rr Reverse RecoveryCharge 1300 1940 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S L D ) 2 www.irf.com
I D, Drain-to-Source Current (A) 1 0.1 VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM5.0V 5.0V I D, Drain-to-Source Current (A) VGS TOP 15V 12V V 8.0V 7.0V 6.0V 5.5V BOTTOM 5.0V 5.0V 20µs PULSE WIDTH 0.01 T J = 25 C 0.1 1 V DS, Drain-to-Source Voltage (V) 20µs PULSE WIDTH T J = 175 C 1 0.1 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drain-to-Source Current (A) 1 T J = 175 C T J = 25 C V DS= 50V 20µs PULSE WIDTH 0.1 5.0 6.0 7.0 8.0 9.0.0 V GS, Gate-to-Source Voltage (V) R DS(on), Drain-to-Source On Resistance (Normalized) 3.5 I D = 24A 3.0 2.5 2.0 1.5 1.0 0.5 V GS= V 0.0-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3
C, Capacitance (pf) IRFB/IRFS/IRFSL23N20DPbF 000 00 0 V GS = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd Ciss Coss Crss 1 0 V DS, Drain-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) 20 16 12 8 4 I = D 14A V DS = 160V V DS = V V DS = 40V FOR TEST CIRCUIT SEE FIGURE 13 0 0 20 40 60 80 Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drain Current (A) 1 T J = 175 C T J = 25 C V GS = 0 V 0.1 0.2 0.5 0.8 1.1 1.4 V SD,Source-to-Drain Voltage (V) I D, Drain Current (A) 0 OPERATION IN THIS AREA LIMITED BY R DS(on) us us 1ms TC = 25 C TJ = 175 C ms Single Pulse 1 1 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com
25 V DS R D I D, Drain Current (A) 20 15 5 Fig a. Switching Time Test Circuit V DS 90% R G V GS V Pulse Width 1 µs Duty Factor 0.1 % D.U.T. - V DD 0 25 50 75 125 150 175 T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms 1 Thermal Response (Z thjc ) 0.1 D = 0.50 0.20 0. 0.05 t1 0.02 SINGLE PULSE 0.01 t (THERMAL RESPONSE) 2 Notes: 1. Duty factor D = t 1 / t 2 0.01 2. Peak T J = P DM x Z thjc TC 0.00001 0.0001 0.001 0.01 0.1 1 t 1, Rectangular Pulse Duration (sec) PDM Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5
15V V DS L DRIVER R G D.U.T I AS - V DD A 20V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V (BR)DSS tp E AS, Single Pulse Avalanche Energy (mj) 600 500 400 300 200 TOP BOTTOM I D 5.9A A 14A 0 25 50 75 125 150 175 Starting T, Junction Temperature ( J C) I AS Fig 12c. Maximum Avalanche Energy Vs. Drain Current Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. V Q GS Q G Q GD 12V.2µF 50KΩ.3µF D.U.T. V - DS V G V GS 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - - R G dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET Power MOSFETs www.irf.com 7
TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.3).54 (.415).29 (.405) 3.78 (.149) 3.54 (.139) - A - 4.69 (.185) 4.20 (.165) - B - 1.32 (.052) 1.22 (.048) 15.24 (.600) 14.84 (.584) 14.09 (.555) 13.47 (.530) 1 2 3 4 6.47 (.255) 6. (.240) 1.15 (.045) MIN 4.06 (.160) 3.55 (.140) LEAD ASSIGNMENTS LEAD ASSIGNMENTS HEXFET IGBTs, CoPACK 1 - GATE 1- GATE 2 - DRAIN 1- GATE 2- DRAIN 3 - SOURCE 2- COLLECTOR 3- SOURCE 4 - DRAIN 3- EMITTER 4- DRAIN 4- COLLECTOR 3X 1.40 (.055) 1.15 (.045) 3X 0.93 (.037) 0.69 (.027) 0.36 (.014) M B A M 0.55 (.022) 3X 0.46 (.018) 2.92 (.115) 2.64 (.4) 2.54 (.) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information EXAMPLE: THIS IS AN IRF LOT CODE 1789 AS S E MB LE D ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INTE RNAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C 8 www.irf.com
D 2 Pak Package Outline Dimensions are shown in millimeters (inches) D 2 Pak Part Marking Information (Lead-Free) T H IS IS AN IR F 530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN THE ASSEMBLY LINE "L" N ote: "P " in as s embly line pos ition indicates "L ead-f ree" OR INT E R NAT IONAL RECTIFIER LOGO AS S E MB L Y LOT CODE F530S PART NUMBER DATE CODE YEAR 0 = 2000 WEEK 02 LINE L INT E R NAT IONAL R E CT IF IE R LOGO ASSEMBLY LOT CODE F530S PART NUMBER DATE CODE P = DE S IGNAT E S L E AD-F R E E PRODUCT (OPTIONAL) YEAR 0 = 2000 WE EK 02 A = AS S E MB L Y S IT E COD E www.irf.com 9
TO-262 Package Outline TO-262 Part Marking Information EXAMPLE: T H IS IS AN IR L 33L LOT CODE 1789 AS S E MB L ED ON WW 19, 1997 IN THE ASSEMBLY LINE "C" Note: "P " in as s embly line pos ition indicates "L ead-f ree" OR INT E R NAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C INT E R NAT IONAL RECTIFIER LOGO ASSEMBLY LOT CODE PART NUMBER DATE CODE P = D E S IGN AT E S L E AD -F R E E PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = ASSEMBLY SITE CODE www.irf.com
D 2 Pak Tape & Reel Infomation TRR 1.60 (.063) 1.50 (.059) 4. (.161) 3.90 (.153) 1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135) FEED DIRECTION TRL 1.85 (.073) 1.65 (.065).90 (.429).70 (.421) 11.60 (.457) 11.40 (.449) 16. (.634) 15.90 (.626) 1.75 (.069) 1.25 (.049) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) 4.72 (.136) 4.52 (.178) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. 60.00 (2.362) MIN. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 2.6mH R G = 25Ω, I AS = 14A. ƒ I SD 14A, di/dt 130A/µs, V DD V (BR)DSS, T J 175 C 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Pulse width 300µs; duty cycle 2%. C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS This is only applied to TO-220AB package This is applied to D 2 Pak, when mounted on 1" square PCB ( FR-4 or G- Material ). For recommended footprint and soldering techniques refer to application note #AN-994. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information.07/04 www.irf.com 11
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/