Plasma Charging Damage Induced by a Power Ramp Down Step in the end of Plasma Enhanced Chemical Vapour Deposition (PECVD) Process Zhichun Wang 1,3, Jan Ackaert 2, Cora Salm 1, Fred G. Kuper 1,3, Klara Bessemans 2, Eddy De Backer 2 1 MESA + Research Institute / University of Twente, Semiconductor Components Group P.O. Box 217,7500 AE Enschede, The Netherlands, E-mail: Z.Wang@utwente.nl 2 AMI Semiconductor, Westerring 15, B-9700 Oudenaarde,Belgium 3 Philips Semiconductor, Nijmegen, The Netherlands Abstract Plasma Enhanced Chemical Vapour Deposition (PECVD) is one of the main plasma processes which induce charging damage to gate oxides during the VLSI processes. All the previous studies, however, describe the charging phenomena only at the beginning of PECVD process, when a very thin oxide layer covers the metal lines. We present and analyze in this paper, a new strong charging phenomenon in the end of PECVD process when a thick oxide layer already covers and insulates the metal lines. The damage occurs during a plasma power ramp down (PPRD) step. The simultaneous presence of elevated temperatures, UV light, a large perimeter conductor and a highly non uniform plasma during PPRD step, causes the damage of gate oxide. Keywords plasma charging damage; Plasma Enhanced Chemical Vapour Deposition (PECVD); gate oxide I. INTRODUCTION Plasma Enhanced Chemical Vapour Deposition (PECVD) is one of the main plasma processes which induce charging damage to gate oxides during the VLSI processes [1]. Plasma non-uniformity [2], high wafer temperature [3] and the shape of the first oxide layer [4,5] have been identified as the main causes of the damage. In [6], the plasma charging damage caused by dechuck has been investigated for a High Density Plasma (HDP)-CVD process. All the previous studies, however, describe the charging phenomena only at the beginning of PECVD process, when a very thin oxide layer covers the metal lines. We present and analyze in this paper, a new strong charging phenomenon in the end of PECVD process when a thick oxide layer already covers and insulates the metal lines. The damage occurs during a plasma power ramp down (PPRD) step, which is used in order to prevent the deposition on the chamber walls releasing and affecting the wafer surface. 766 The evaluation is performed with non contact surface potential measurement on an in-line Plasma Damage Monitor (PDM) system, and gate oxide integrity measurements on antenna test structures. The mechanism of the damage is discussed in this paper. II. EXPERIMENTAL DETAILS The test structures have been subjected to an experimental 0.5 µm CMOS backend-of-line process, with a gate oxide thickness of 8 nm. Specific antenna structures have been designed. They are NMOS transistors (W/L = 0.8/0.5 µm) with different antennas connected to the gate of the NMOS transistors. The antenna is a conductive surface, which is exposed to plasmas during processing. It collects charges from the plasma, explaining the name antenna. The antennas are designed in plate shape and finger shape and different size in order to simulate the interconnects of the devices. The top area of the antennas ranges from 100 to 100,000 µm 2. For the finger-shaped antennas, the space between the 0.8 µm metal lines ranges from 0.8 to 1.6 µm. A sample with a metal 2 antenna is shown in Figure 1. This antenna structure is sensitive to the cumulative charging of all processes during metal 2 manufacturing, including plasma clean, plasma etching, plasma deposition of inter metal dielectric (IMD) and etc.. A protection diode is connected to metal layers above the antenna in order to avoid the influence of other plasma processes after metal 2 manufacturing.
M2 M2 Transistor M3 Protection diode Transistor M3 Protection diode Figure 1: Schematic layout of tester with metal2 finger antenna. The inter metal dielectric (IMD), a 0.5um thick SiO 2 layer on metal lines (antennas), is deposited by a PECVD tool. The PECVD tool is a medium density plasma reactor. The source frequency is 13.56 MHz. The PECVD deposition processes with an extra plasma power ramp down (PPRD) step and without PPRD step are investigated. This PPRD step is added in the end of PECVD process in order to prevent the deposition on the chamber walls releasing and affecting the wafer surface. The location and magnitude of the charge are studied by plasma damage monitor (PDM, Semiconductor Diagnostics Inc.). PMD is a contactless and damage-free tool to determine the amount of charge built-up on an oxide layer. Unpatterned wafers with a blanket oxide layer (>100 nm) are used as test wafers. After PECVD process, the potential on the oxide surface has been measured by PDM. The absolute potential (V pdm ) and the potential difference ( V pdm ) between the edge and center reflect the charging contributed by the final stages of PECVD process. The gate leakage current (I g,leak ) of antenna structures have been measured at 3.85 V (V g ). An antenna structure is considered to fail when the gate leakage current (I g,leak ) measured through its gate oxide exceeds 1 na, indicating that (soft or hard) breakdown occurred. The failure fraction of the antenna structures processed with and without PPRD step has been compared. Figure 2. PDM mapping of oxide layer deposited by PECVD process without PPRD step. Figure 3. PDM mapping of oxide layer deposited by PECVD process with PPRD step. For the wafer processed without PPRD step, a small potential difference (2.3 V) is measured. For the wafer processed with PPRD step, however, a large potential difference (63 V) is detected between the edge and center of the wafer. In the center of the wafer a minimum voltage of 43 V is measured. On the edges a maximum voltage of 20 V is measured. This large potential difference is enough to break 8 nm gate oxide, leading the failure of the devices. III. RESULTS A. Plasma damage monitor results In Figure 2 and Figure 3, the charging of a deposited oxide layer with and without the plasma power ramp down (PPRD) step is compared. 767 B. Antenna structure failure The failure fraction of the antenna structures is presented in Figure 4. The antenna structures processed with PPRD step failed more than those processed without PPRD step. The failure fraction of finger-shaped antennas shows a sharp increase, if the PPRD step is added to the end of PECVD process. This effect does not occur on the plate-shaped antennas with the same area:
the increase of plasma damage is correlated with the perimeter of the antenna rather than with the area of the antenna. % failure fraction 45 40 35 30 25 20 15 10 5 0 without PPRD step with PPRD step plate antenna finger antenna Figure 4. Failure fraction of antenna structures with and without PPRD step. C. Wafer Mapping of I g,leak To correlate the location of the highly charged regions, with the location of the failing sites, two wafer mappings have been made. Figure 5 is the I g,leak mapping of a wafer processed without PPRD and Figure 6 is the I g,leak mapping of a wafer processed with PPRD. The value presented in the map is the log value of I lk (A). Dark/red area indicates the failure (I lk >1 na). The failure occurs mainly in the center and on the edges of the wafer. The I g,leak at the edges of the wafers is the same for both wafers. This edge effect is proven to be caused by the metal patterning prior to the IMD deposition, which is not the subject in this paper. However, the failure in center region is caused by the charging during the PPRD step. The location coincides very well with the charged area as measured with the PDM. The I g,leak mapping confirms the relation between the charges measured by the PDM and the failure of antenna structures. -7-6 -11-11 -8-11 -8-8 -11-11 -11-6 -8-11 -11-11 -7-6 -7-11 -11-7 -6-11 -11-11 -6-6 -11-11 -11-6 Figure 5. Typical I g,leak mapping of a wafer processed without PPRD step. -8-6 -8-11 -11-8 -11-8 -6-11 -6-6 -11-6 -11-11 -8-7 -6-6 -6-6 -11-11 -11-6 -6-11 -11-11 -8-6 -6-6 -6-6 -11-11 -11-6 -11-11 -8-7 -6-11 -11-6 -8-11 -11-11 -6 Figure 6. Typical I g,leak mapping of a wafer processed with PPRD step. -7 IV. DISCUSSION The failure mechanism could have two causes: the first is a charge induced into the antenna, mirroring the charge on top of the oxide surface; the second is a leakage current through the IMD. A. Mirror charge A charge on an insulator can induce a mirror charge in any conductor on the other side of the insulator. When this charge is exceeding the Q BD of the gate oxide connected to the conductor, this gate oxide is damaged and starts to leak. The Q BD of the gate oxide, especially for small area, is typically larger than 10 C/cm 2 [8]. With 768
a given gate area of 0.4 µm 2, 4x10-8 C is needed to break the gate oxide. The mirror charge (Q mirror ) in our experiment can be calculated. First the capacitance of the IMD (C IMD ) between the antenna and the oxide surface that exposed to plasma can be calculated by equation (1), C ξ ξ o ox IMD = Aantenna (1) TIMD where T IMD is the thickness of IMD (500 nm) and A antenna is the area of the antenna connected to the gate of transostor. Taking the maximum antenna area, 100,000 µm 2 into equation (1), the maximum C IMD is therefore 6.7 PF. By equation (2), the Q mirror can be calculated, Q = C V (2) mirror IMD ox where V ox is the surface potential of the IMD. According the PDM measurement, the V ox detected is around 43V. The charge induced in the antenna Q mirror becomes 3.5x10-10 C, which is less than 1% of the Q BD. Although Q BD is reported to reduce to some extend at elevated temperature, it is not being reduced by 2 orders of magnitude [3]. The mirror charge is not the cause of the damage we observed. Furthermore, plate-shaped antenna and finger-shaped antenna with the same area should induce the same amount of mirror charge. However, the failure fraction of finger-shaped antenna structures is much higher than that of plate-shaped antenna structures. This fact proves again that the mirror charge is not the main cause of damage. B. Photoconduction through IMD The charging damage caused by photoconduction through IMD has been reported in literature before and was contributed in one case to the elevated temperature [3] and in another case by the presence of high energetic UV photons [7]. In both cases the effects were observed for very thin IMD at the beginning of the PECVD deposition. The damage induced by photo conduction is dependent on the perimeter of the antenna. This perimeter effect is explained by nonconformality of the deposition of IMD. The IMD oxide is thinner at the corner of metal lines. These sites are therefore more sensitive to photoconduction. The longer the perimeter of the metal lines, the more those sensitive sites are [6]. In this study, the charging damage is observed in the end of the PECVD process, when a thick IMD layer (0.5 µm) already covers the metal lines. The photoconduction through this thick IMD layer can be explained by the simultaneous presence of four factors, which are quite common with commercial PECVD tools. 1. Elevated temperatures. The process temperature of PECVD ranges from 350 ºC to 400 ºC. 2. A conductor with large perimeter connected to the gate of a transistor. 3. UV light. UV light is inevitable in a PECVD process. 4. A highly non uniform plasma. In order to improve the particle performance of the process, plasma power is reduced at the end of the PECVD process. This reduced plasma power however, is no longer capable of supporting a plasma over the full wafer surface. Plasma remains only in the center of the wafer. The center of the wafer is therefore charged highly negative, as confirmed by the PDM measurements. The photoconduction of the IMD layer enable the plasma current to leak through and stress the underlying gate oxide. Hence the gate oxide degrades or even breaks down in worse cases. Like the previous observed damage during PECVD process, the damage is dependent on the perimeter of the metal lines. The finger-shaped antenna structures therefore fails more than plate-shaped antenna structures. V. CONCLUSIONS In the paper, we investigated the charging damage in the end of the PECVD process. It is observed that the damage occurs at the PPRD step, when a thick IMD layer (0.5 µm) already covers the metal lines. The location and magnitude of the charge is measured by a PDM tool and confirmed by gate leakage measurements on antenna structures. The extent of damage is proportional to the perimeter of metal lines connected to the gate. It is believed that the simultaneous presence of elevated temperatures, UV light, a large perimeter conductor and a highly non uniform plasma during PPRD step, leads the plasma current to go through this thick IMD layer, stress the gate oxide and therefore degrade the gate oxide. 769
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