High quality standard frequency transfer, Mattia Rizzi, Tjeerd Pinkert, Peter Jansweijer, Guido Visser 1
WR calibration jitter spec Tjeerd Pinkert will talk more about jitter measurements 2
Introduction: Phase noise & Jitter Real Oscillator PSD PSD Ideal Oscillator
Introduction: Phase noise & Jitter (2) (dbc) PSDPSD (rad^2/hz) Random walk frequency Flicker frequency White frequency Flicker phase White phase Time-keeping High speed electronics
Introduction: Phase noise & Jitter (3) PSD (dbc) Random walk frequency The limits of integration are chosen depending on the application Flicker frequency White frequency Flicker phase White phase Jitter power
Introduction: Phase noise & PLLs PLLs can filter out an high-frequency phase-noise of a clock, improving the jitter over a wide bandwidth But cannot clean a noise close to the carrier Can easily clean a noise located above the bandwidth of the PLL Phase Detector PI controller Real VCO + Ideal VCO Inside an FPGA the jitter cleaning feature may be compromised by clock-tree power noise
Spec 7
Spec serdes RX clock 300KHz sidebands from DC-DC powerconverter. 8
Spec EDA-021890V4-0 10uH 0.2A 0.1Ω Reject 300KHz sidebands from DC-DC powerconverter. 9
Spec serdes RX clock 30Hz sidebands near 125MHz carrier. 10
WHITE RABBIT SWITCH: Grand Master phase noise Ø Ø Ø Ø Grand Master locked to Cesium, RMS Jitter of 9ps (1Hz-100kHz) Locking throught SoftPLL, sample/correction rate of 3.8kHz Most of the jitter lies inside the SoftPLL bandwidth! Error signal from the PFD shows 44ps RMS of phase noise, the sprectum looks like white noise Ø Where is the source of the noise? Ø Ø Ø Ø Ø 9ps RMS Ø Ø
WRS BOARD XILINX VIRTEX-6 FPGA 10MHz jack 10MHz to 100MHz PLL 100MHz to 62.5MHz PLL SoftPLL 1.5ps RMS
WRS BOARD XILINX VIRTEX-6 FPGA 10MH z jack 10MHz to 100MHz PLL 100MHz to 62.5MHz PLL SoftPLL <2ps RMS
WRS BOARD XILINX VIRTEX-6 FPGA 10MHz jack 10MHz to 100MHz PLL 100MHz to 62.5MHz PLL SoftPLL <2ps RMS 42ps RMS
DDMTD Full digital phase detector It s a sampled system! Unfiltered high-frequency clock noise is aliased in the PLL bandwidth High-frequency noise appears in the PLL bandwidth as white noise What is the filtering frequency of the phase detector? Phase-detector has non-linear low-pass filtering function Cut-off frequency depends on the size of the transition window (which depends on input jitter power!) Cut-off above 70kHz Noisy Input clock jitter Transition window DDMTD clock 0000000000000000101010111111111111111111 Bit-median deglitch «true» edge
How to reduce the impact of the high frequency noise? 1. Exploit the non-linearity of the DDMTD (DONE) Introduce a very high frequency noise which increase the cut-off frequency Done with CLOCK BUFFER switching primitives Less than 6ps RMS is not feasible No hardware modification 2. Use AD9516 to multiply the 10MHz input clock instead of Xilinx DCM (ON GOING) High frequency spurs degrades to 5ps Simple hardware modification RMS, but Less than 2ps RMS in SoftPLL BW These spurs are not transferred down the chain Allan Deviation @1s = 1e-12 A slave can synchronize itself with a jitter (vs 1.3e-11 with current G.M) 3. less than 4ps (vs 10ps with current G.M.) AD9516 fine tuning is very limited, less than half of a period Avoid external clock multiplication by using a slower DDMTD beat frequency (ON EVALUATION) No hardware modification 4. VCXO correction rate (152Hz), Low probably a better VCXO is required Additional external PLL (AD9516?) to multiply the external reference
WR frequency transfer aim WR carrier signals are for some applications to noisy Carrier signals are very sensitive for noise. Every component must be qualified Printed circuit layout becomes very critical Extra local screening may be required The most electronic signals are by approach 1 Volt. 1mV noise 60dB signal to noise 0.1 mv noise 80dB signal to noise 0.01 mv noise 100dB signal to noise What are the most needed requirements? Phaselock of the local 125MHz VCXO Carrier recovery Printed circuit layout 17
Down and up conversion Digital logic is not linear A signal is sampled at the threshold level. Down conversion Nyquist: The bandwidth is half the sample rate. Input frequencies above the half sample rate are folded back to the half sample rate bandwidth. To prevent this fold back, the input signal has to be high pass filtered before the sampling. Up conversion (Low) frequency noise will be up converted as carrier sidebands. 18
Current WR carrier recovery Single phaselock loop The DMTD limit the loop bandwidth
Fast WR carrier recovery Master slave phaselock loop The DMTD generates the accuracy The phase detector generates the loop bandwidth 20
π fast phase detector Uo Uφ Phase detector Phase flip Uφ 0 π 2π Xor gate phase detector Phase flip extend the range 3π 4π 21
2π fast phase detector Uo Uφ Phase detector Phase flip Uφ Uphase setpoint 0 π 2π 3π I and Q, ½π offset, phase detector 2π extend phase detector range 4π 22
WR carrier recovery Analog phaselock reference avoids the noisy serdes phaselock 23
Power supply decoupling Current practice: VCC and GND are separate foils in a multilayer print. Local power supply decoupling 24
Power supply decoupling Current practice: VCC and GND are foils in a multilayer print Decoupling current flows also to non local decoupling capacitors. 25
Power supply decoupling Current practice: VCC and GND are foils in a multilayer print All decoupling current flows through the local decoupling capacitors Almost no decoupling ground current 26
Power supply decoupling Current practice: VCC and GND are foils in a multilayer print All decoupling current flows through the local decoupling capacitors No decoupling ground current 27
Feedback Reduction with Filter Glued on Chip S-curves Before Filter: After Filter: Filter Circuit glued to ABCD Chip Joop Roverkamp/ 8th Workshop on Electronics for LHC Experiments, Colmar, France, 9-13 Sep 2002, pp.400-403 (-2002-003) DOI 10.5170/-2002-003.400 28
KM3net photomultiplier base 1500V Cockcroft Walton DC-DC converter on the backside Histogram of photomultiplier dark pulses with a charge discriminator setting of 80 femtocoulomb (⅓photon) 29